Method of making infrared detector with channel stops

Abstract

Channel stops for MIS infrared photodetector devices in Hg.sub.1-x Cd.sub.x Te by lattice damage (454) between and automatically aligned to MIS gates (408). Also, field plates and guard rings are automatically aligned to MIS gates.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to infrared radiation detectors and, more particularly, to small bandgap semiconductor infrared detectors and methods of fabrication.

2. Description of the Related Art

Detection of infrared radiation emitted by warm bodies provides an important method for night vision (perception without visible light). Infrared detectors are of various types and include small bandgap semiconductors structured as photodiodes or photocapacitors. Alloys of mercury telluride and cadmium telluride, generically denoted Hg.sub.1-x Cd.sub.x Te, are extensively employed as the photosensitive semiconductor in such detectors. Indeed, Hg.sub.0.8 Cd.sub.0.2 Te has a bandgap of about 0.1 eV which corresponds to a photon wavelength of 12 .mu.m and Hg.sub.0.73 Cd.sub.0.27 Te has a bandgap of about 0.24 eV corresponding to a photon wavelength of 5 .mu.m; and these two wavelengths are in the two atmospheric windows of greatest interest for infrared detectors.

An-infrared imager incorporating an array of MIS photocapacitor detectors in Hg.sub.1-x Cd.sub.x Te is disclosed in U.S. Pat. No. 4,684,812 (Tew and Lewis). FIGS. 1a-b are cross sectional elevation and plan views of a single photocapacitor and illustrate the anodic oxide passivation of the Hg.sub.1-x Cd.sub.x Te. Anodic oxidation of Hg.sub.1-x Cd.sub.x Te provides a passivation layer made of primarily HgTeO.sub.3, CdTeO.sub.3, and TeO.sub.2 on the surface of the Hg.sub.1-x Cd.sub.x Te (typically the layer is grown to a thickness of 700 .ANG.), and this oxide passivation layer typically includes substantial trapped positive charge with density of roughly 1.times.10.sup.12 /cm.sup.2. The trapped charge acts as a channel stop in that it accumulates electrons at the oxide Hg.sub.1-x Cd.sub.x Te interface and deters inversion in n type Hg.sub.1-x Cd.sub.x Te. This achieves maximum usable potential well capacity and integration time.

However, the anodic oxide passivation layer is thermodynamically unstable and sulfide passivation layers (primarily CdS plus some HgS) are replacing oxide passivation layers; see U.S. Pat. No. 4,632,886 (Teherani and Simmons). Sulfide passivation layers have the drawback of not incorporating substantial positive fixed charger, and various approaches have been used to control surface currents. One approach is to etch away the sulfide passivation layer in channel stop areas and grow anodic oxide to regain the fixed positive charge, but this has the problem of extra wet processing steps. Alternatively, a field plate may be incorporated into the imager and biased to induce a channel stop, but this has the problems of a more complicated structure and processing sequence.

Infrared detectors based on photodiodes in Hg.sub.1-x Cd.sub.x Te require formation of p-n junctions in Hg.sub.1-x Cd.sub.x Te, and such junctions are frequently made by ion implanting species such as boron into p type Hg.sub.1-x Cd.sub.x Te. Prior to annealing, the implanted region has strong n type doping even for very small implanted doses of each kind of implanted ion (donor, acceptor, inert) and the carrier concentration increases with implant dose but rapidly reaches a saturation in sheet donor concentration of 2.times.10.sup.14 /cm.sup.2. See, G. Destefanis, 86 J.Crystal Growth 700 (1988) at 705.

SUMMARY OF THE INVENTION

The present invention provides optimal methods of implementing channel stops in Hg.sub.1-x Cd.sub.x Te and related compounds by ion implants, ion milling, or field plate formation. In preferred embodiments, a gate photoresist pattern is undercut using an isotropic etch of the gate material to leave a buffer area between the gate and adjacent channel stop locations, then with the photoresist still in place either (1) boron is implanted through sulfide (CdS, HgS) passivation and/or ZnS dielectric on Hg.sub.1-x Cd.sub.x Te or (2) field plate metal is deposited and lifted-off using the photoresist to form channel stops aligned to the gate without additional patterning steps. This solves the problems of the known methods of channel stop formation with non-anodic oxide passivation.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings are schematic for clarity.

FIGS. 1a-b are cross sectional elevation and plan views of a prior art infrared, photo capacitive detector;

FIG. 2 shows the anodic oxide channel stop of the prior art detector;

FIG. 3 shows a prior art field plate channel stop;

FIGS. 4a-c (illustrate a lattice damage channel stop and the steps of a method of fabrication;

FIGS. 5a-b show steps in a first preferred embodiment method of lattice damage channel stop;

FIG. 6 shows a first preferred embodiment field plate;

FIG. 7 illustrates the effect of a preferred embodiment field plate; and

FIGS. 8a-c show steps in a second preferred embodiment method.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1a-b illustrate in cross sectional elevation and plan views a single pixel (denoted by reference numeral 100) of a prior art Hg.sub.1-x Cd.sub.x Te photocapacitive infrared imager and show anodic oxide passivation 102 of Hg.sub.1-x Cd.sub.x Te 104 together with ZnS gate dielectric 106 and nickel gate 108. FIG. 1a is a section taken along line a--a in FIG. 1b. The Figures also indicate the underlying silicon processor 110 for the imager, the metal connection (112-114-116) of gate 108 to silicon processor 110, ZnS insulation 120, and epoxy 122 axing the Hg.sub.1-x Cd.sub.x Te to the silicon processor.

FIG. 2 is an enlarged portion of the cross sectional elevation view as in FIG. 1a, but showing two adjacent gates, 108 and 108', of two adjacent pixels together with the accumulated channel stop between them. Anodic oxide 102 is about 700 .ANG. thick, gate dielectric ZnS 106 is about 1500 .ANG. thick, semitransparent nickel gates 108 and 108' are each about 70 .ANG. thick and separated laterally by about 10 .mu.m. Each pixel is about 50 .mu.m square (including the channel stop). The fixed positive charge in anodic oxide 102 is heuristically indicated by the +'s 150, the negative bias on gates 108 and 108' by the .crclbar.'s 152, the accumulated electrons in Hg.sub.1-x Cd.sub.x Te 104 forming the channel stop by .crclbar.'s 154, and the potential wells in the Hg.sub.1-x Cd.sub.x Te under the gates by +'s 156. Without the fixed positive charge in anodic oxide 102, the surface region of Hg.sub.1-x Cd.sub.x Te 104 between the gates 108 and 108' would be neutral or slightly depleted, and minority carrier holes in Hg.sub.1-x Cd.sub.x Te 104 which are stored in the potential well created by the bias on gate 108 could diffuse along the surface to the potential well created by the bias on gate 108', and vice versa, and thereby disrupt the infrared detection.

FIG. 3 is analogous to FIG. 2 but shows a prior art field plate channel stop; the elements in FIG. 3 are numbered the same as their analogs in FIG. 2. The field plate 160 is biased relative to Hg.sub.1-x Cd.sub.x Te 104 to accumulate electrons to form the channel stop indicated by the .crclbar.'s 154. Field plate 160 is typically opaque and made of thick metal. Both gate insulator 106 and interlevel insulator 120 are made of ZnS, semitransparent gates 108 and 108' are 70 .ANG. thick nickel, and Hg.sub.1-x Cd.sub.x Te 104 may have a sulfide passivation.

The lattice damage channel stop is illustrated in FIG. 4a (a view analogous to that of FIGS. 2 and 3) which shows n type Hg.sub.1-x Cd.sub.x Te 204 with passivation sulfide 202 (typical thickness 50-100 .ANG.), ZnS dielectric 206 of thickness 1500 .ANG., semitransparent nickel gates 208 and 208' of thickness 70 .ANG. which are laterally separated by about 10 .mu.m, and insulation ZnS 220. Again, the negative bias on gates 208 and 208' is heuristically indicated by .crclbar.'s 252, the induced potential wells in Hg.sub.1-x Cd.sub.x Te 204 by +'s 256, and boron implanted into Hg.sub.1-x Cd.sub.x Te 204 between gates 208 and 208' by .crclbar.'s 254. The sulfide passivation 202 fails to provide a fixed positive charge to accumulate the surface of Hg.sub.1-x Cd.sub.x Te 204 between gates 208 and 208'. However, the implanted boron converts Hg.sub.1-x Cd.sub.x Te 204 to n.sup.+ (suggested by the .crclbar.'s 254) which possesses a higher threshold voltage for surface inversion (but still has the same flatband voltage) and hence provides a channel stop between the potential wells.

FIGS. 4b-c illustrate the following steps in a method of fabrication of the channel stops (and imagers).

(a) Begin with sulfide passivated substrate 204 of n type Hg.sub.0.8 Cd.sub.0.2 Te with a carrier concentration of about 105.sup.15 /cm.sup.3 at 77K; substrate 204 may already be epoxied to a silicon processor and have vias for fabrication of a hybrid imager. Sulfide passivation layer 202 may have been formed by any convenient method such as anodic sulfidization or plasma sulfidization, and has a composition of primarily CdS with some HgS, depending upon the method of formation used. Next deposit 1500 .ANG. of ZnS 206 gate dielectric by any convenient method. Deposit by evaporation a nickel layer of thickness about 70 .ANG.. Spin on photoresist 230, and expose it to define the locations for the gates of the imager. Develop photoresist 230, and use it as an etch mask to etch the nickel layer to form the gates; gates 208 and 208' are shown in FIG. 4b. Sulfide 202 may have a small, negative fixed charge, and the Hg.sub.0.8 Cd.sub.0.2 Te at the interface of sulfide 202 and substrate 204 may be depleted or even possibly inverted. This is suggested by the +s and -'s.

(b) Strip photoresist 230 and spin on photoresist 232; expose photoresist 232 to define the channel stops. Implant boron (isotope 11) at 75 KeV and a dose of 10.sup.13 ions/cm.sup.2. The boron has a projected range of about 2000 .ANG., and penetrates ZnS 206 and sulfide 202 with the peak boron concentration about at about 300 .ANG. below the interface of sulfide 202 and substrate 204. The projected straggle of the implant is about 800 .ANG., so at least 1100 .ANG. of Hg.sub.1-x Cd.sub.x Te 204 at the interface is heavily implanted and consequently doped n.sup.+ with a carrier concentration on the order of about 10.sup.17 /cm.sup.3 near the surface and at 77K. See FIG. 4c which indicates the boron implant caused doping with (.crclbar.'s 254. Note that photoresist 230 could not have been used for the boron implant because the channel stop then would have extended (due to lateral straggle) under the gates 208 and 208' and degraded performance. Photoresist 232 extends about 2.5 .mu.m beyond gates 208 and 208' to provide an offset between channel stop 254 and depletion regions under the gates.

(c) Strip photoresist 232 and deposit ZnS insulation layer 220 of thickness 3000 .ANG.. Use photoresist to etch openings in ZnS 220 to the gates and to the underlying silicon processor. Deposit metal and pattern it with photoresist and etch it to form the connections from the gates to the silicon processor. This completes the imager.

First preferred embodiment method of fabrication of the first preferred embodiment channel stops (and imagers) includes the following steps which are illustrated in FIGS. 5a-b:

(a) Begin with sulfide passivated substrate 304 of n type Hg.sub.0.8 Cd.sub.0.2 Te; sulfide passivation layer 302 has a composition (primarily CdS with some HgS) and fixed charge (from essentially zero to negative about 2.times.10.sup.11 /cm.sup.2) depending upon the method of formation used. Next deposit 1500 .ANG. of ZnS 306 gate dielectric by any convenient method. Deposit by sputtering a tantalum (or other refractory metal) layer of thickness about 1000 .ANG.. Spin on photoresist 330, and expose it to define the locations for the gates of the imager. Develop photoresist 330, and use it as an etch mask to plasma etch the tantalum layer with CF.sub.4 to form the gates. This etch is isotropic and undercuts the tantalum as illustrated in FIG. 5a; overetching by 1500% yields an undercut of about 1.0-1.5 .mu.m. The selectivity of the etch for tantalum relative to ZnS 306 is about 200 to 1; but even if a few hundred .ANG. of ZnS 306 are removed during the overetch, the subsequent deposition of ZnS 320 will compensate for the loss. See FIG. 5a showing gates 308 and 308'.

(b) Implant boron (isotope 11) at 75 KeV and a dose of 10.sup.13 ions/cm.sup.2 using photoresist 330 as the implant mask. The boron has a projected range of about 2000 .ANG., and penetrates ZnS 306 and sulfide 302 with the peak boron concentration about at about 300 .ANG. below the interface of sulfide 302 and substrate 304. The projected straggle of the implant is about 800 .ANG., so at least 1100 .ANG. of Hg.sub.1-x Cd.sub.x Te 304 at the interface is heavily implanted and consequently doped n.sup.+. Experimental results indicated that the lateral damage is about 1.0 .mu.m as C-V characteristic similar to that of low frequency occurred at <1.0 .mu.m of overhang. Thus a 1.5 .mu.m overhang of photoresist 330 on gates 308 and 308' is sufficient to prevent the implant from extending under the gates and to produce channel stop effects. See FIG. 5b which indicates the boron implant caused doping with .crclbar.'s 354. Note that with only a 0.5 .mu.m overhang by photoresist 330 this implant schedule would not yield an effective channel stop.

(c) Strip photoresist 330 and deposit ZnS insulation layer 320 and complete the imager as previously described.

The first preferred embodiment imager is similar to the prior art imager with pixels illustrated in FIGS. 1a-b, but with sulfide passivation and first preferred embodiment channel stops.

Note that the same undercut etch of the gate level metal can be used to form a self-aligned field plate or guard ring: in place of the implant of boron in step (b) a deposition of gate metal (see FIG. 6) followed by liftoff of the photoresist will yield a field plate 370 aligned to the gates 308 and 308'. The separation between gate 308 and field plate or guard ring 370 is controlled by the amount of undercut during the etch of the gate level metal. Because there is no implant, the separation between gate 308 and field plate 370 will not be limited by implant lateral straggle.

A measure of the effectiveness of field plate 370 as a channel stop source for a 0.5 .mu.m separation between gate 308 and field plate 370 is shown in FIG. 7 which graphs the MIS diode semiconductor resistance (R.sub.o A) as a function of the bias applied to the field plate. That is, the MIS diode formed by gate 308, insulator 302-306, and semiconductor 304 is modelled as a capacitor C.sub.i in series with a parallel capacitor C.sub.p and resistance R.sub.o A where C.sub.i represents the insulator capacitance and the parallel C.sub.p and R.sub.o A represent the semiconductor. The capacitances and resistance measured depend upon the gate bias and the frequency of the signal applied across the MIS diode due to factors such as recombination rates. An increase in R.sub.o A typically indicates a lessening of currents that are generated within Hg.sub.1-x Cd.sub.x Te 304 laterally away from gate 308 and propagate along the interface of Hg.sub.1-x Cd.sub.x Te 304 with sulfide 302 to under gate 308. As FIG. 7 illustrates, once the field plate 370 bias is greater than about -1 volt a channel stop has been induced that deters these interface currents and increases R.sub.o A.

Second preferred embodiment method of fabrication of the preferred embodiment channel stops (and imagers) includes the following steps illustrated in cross sectional elevation view:

(a) Begin with sulfide passivated substrate 404 of n type Hg.sub.0.8 Cd.sub.0.2 Te; sulfide passivation layer 402 has a composition (primarily CdS with some HgS) and fixed charge (from essentially zero to negative about 2.times.10.sup.11 /cm.sup.2) depending upon the method of formation used. Next deposit 1000 .ANG. of ZnS 406 gate dielectric by any convenient method. Deposit a conductive layer of thickness about 5000 .ANG.. Spin on photoresist and expose it to define the locations for the gates of the imager. Develop the photoresist and use it as an etch mask to plasma etch the conductive layer to form the gates. Deposit conformal layer 430 of silicon dioxide or silicon nitride (or silicon oxynitride) of thickness about 10,000-15,000 .ANG.; see FIG. 8a showing gates 408 and 408'.

(b) Anisotropically etch layer 430 to leave sidewall filaments 432 on the edges of the gates. See FIG. 8b; the sidewall filaments are about 10,000-15,000 .ANG. wide.

(c) Implant boron at 50 KeV and a dose of 10.sup.13 ions/cm.sup.2 using the gates plus sidewall filaments as the implant mask. This is analogous to the sidewall oxide spacer approach to source/drain implantation in MOSFET fabrication. The boron has a projected range of about 1500 .ANG., and penetrates ZnS 406 and sulfide 402 with the peak boron concentration about at about 300 .ANG. below the interface of sulfide 402 and substrate 404. The projected straggle of the implant is about 600 .ANG., so at least 900 .ANG. of Hg.sub.1-x Cd.sub.x Te 404 at the interface is heavily implanted and consequently doped n+. The lateral straggle is somewhat less than the projected straggle, so the 10,000 .ANG. width of sidewall filaments 432 on gates 408 and 408' is sufficient to prevent the implant from extending under the gates. See FIG. 8c which indicates the boron-implant-caused doping with .crclbar.'s 454. Note that gate 408 must be thick enough to prevent the implant from penetrating the gate plus ZnS and doping the Hg.sub.1-x Cd.sub.x Te beneath the gate. However, a thick gate absorbs a greater fraction of the incident infrared radiation, so a thinning of gate 408 by a timed etch may be used after the implant.

(d) Deposit ZnS insulation layer 420 and complete the imager as previously described.

An alternative self-aligned channel stop by lattice damage doping of Hg.sub.1-x Cd.sub.x Te may be created by using ion milling of the insulator and passivation layers with mask being either the undercut photoresist 330 of the first preferred embodiment (FIG. 5b would have the boron ions replaced by argon ions that sputter away ZnS 306 and sulfide 302 and lattice damage dope Hg.sub.1-x Cd.sub.x Te 304) or the unthinned gate 408 plus sidewall filaments 432 of the second preferred embodiment (FIG. 8c would have the boron ions replaced by argon ions that sputter away ZnS 406 and sulfide 402 and lattice damage dope Hg.sub.1-x Cd.sub.x Te 404). Of course, photoresist 330 and unthinned gate 408 plus sidewall filaments 432 are also sputtered and must be of sufficient thickness to survive.

MODIFICATIONS AND ADVANTAGES

Various modifications of the preferred embodiment devices and methods may be made while retaining the features of self-aligned lattice damage channel stops and field plates or guard rings.

For example, the dimensions and shapes of the detectors may be varied, the material may be HgCdZnTe, HgMnZnTeSe, or other II-VI narrow bandgap semiconductors, the insulator such as ZnS may be formed directly on the semiconductor without a separate passivation layer, the implanted species or ion milling species may be any convenient ion, although light ions such as boron have a greater projected range for the same energy, and the gate and field plate or guard ring may be made of any convenient materials. The overhang can vary depending upon the amount of lateral straggle damage or the field plate bias relative to gate bias.

The invention provides the advantages of simple and process-compatible channel stops and field plates aligned to gates for high packing density.

Claims

1. A method of processing at least one semiconductor device, comprising the steps of:

forming a gate layer on an insulated semiconductor layer;

patterning resist on said gate layer;

forming gates from said gate layer by removal of portions of said gate layer using said resist as a mask; and

forming a channel stop by implanting ions using said resist as a mask.

2. The method of claim 1, wherein:

(a) said removal is by plasma overetching.

3. A method of forming channel stops between semiconductor devices, comprising the steps of:

providing an n-type mercury cadmium telluride semiconductor layer with two devices formed therein, each of said devices including a gate element with a sidewall insulator formed thereon; and

damaging a lattice within a region of said semiconductor layer between said two devices, said damaging by implanting ions into said layer.

4. The method of claim 3 wherein said step of implanting ions comprises implanting boron ions.

5. The method of claim 3 wherein said ions are implanted through at least one insulation layer on said semiconductor layer.

6. A method of processing semiconductor devices, said method comprising the steps of:

forming a gate layer on an insulated semiconductor layer;

patterning resist on said gate layer;

forming gates from said gate layer by removal of portions of said gate layer using said resist as a mask; and

depositing a conductive material on said semiconductor layer using said resist as a mask.

7. The method of claim 6 wherein said removal is by plasma overetching.

8. The method of claim 6 wherein said step of depositing a conductive material comprises a step of forming a field plate.

9. The method of claim 6 wherein said step of depositing a conductive material comprises a step of forming a guard ring.

10. The method of claim 1 wherein said semiconductor, layer comprises a mercury cadmium telluride layer.

11. A method of processing at least one semiconductor device, comprising the step of:

damaging a lattice of an n-type mercury cadmium telluride semiconductor layer in a region between gates of two devices formed in said layer, said damaging by implanting boron ions into said semiconductor layer such that said damaged region is offset from said devices.

12. The method of claim 11, wherein each of said two devices includes a gate layer and wherein a mask is used for both overetching of said gate layer to form said devices and said implanting ions.

13. The method of claim 11 wherein said boron is implanted through at least one insulation layer on said semiconductor layer.

14. The method of claim 3 wherein said sidewall insulator is selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride.