Claims
- 1. A method for forming a bipolar junction transistor on an integrated circuit comprising:providing a semiconductor substrate: forming a p-well region in said semiconductor substrate by performing p-well ion implantation comprising p-type dopant species; forming a n-well region in said semiconductor substrate by performing n-well ion implantation comprising n-type dopant species; and forming a compensated base region of said bipolar junction transistor by allowing said p-well ion implantation and said n-well ion implantation to enter a common region of said semiconductor substrate.
- 2. The method of claim 1 wherein at least one NMOS transistor is formed in said p-well region.
- 3. The method of claim 1 wherein at least one PMOS transistor is formed in said n-well region.
- 4. The method of claim 1 wherein said n-well region and said p-well region have offset doping concentration profiles.
- 5. The method of claim 4 wherein for a PNP bipolar junction transistor, the depth of the p-well region is greater than the depth of the n-well region.
- 6. The method of claim 4 wherein for a NPN bipolar junction transistor, the depth of the n-well region is greater than the depth of the p-well region.
- 7. The method of claim 1 further comprising forming an emitter region of the bipolar junction transistor by simultaneously implanting the compensated base region of said bipolar junction transistor with an ion implantation process used to form the source and drain region of the PMOS transistor or the NMOS transistor.
- 8. A method for forming a bipolar junction transistor on an integrated circuit comprising:providing a semiconductor substrate; forming a p-well region in said semiconductor substrate by performing p-well ion implantation comprising p-type dopant species; forming a n-well region in said semiconductor substrate by performing n-well ion implantation comprising n-type dopant species; forming a deep well region in said semiconductor substrate by performing deep well ion implantation comprising p-type dopant species, n-type dopant species, or both p-type and n-type dopant species; and forming a compensated base region of said bipolar junction transistor by allowing said p-well ion implantation and said n-well ion implantation to enter said deep well region of said semiconductor substrate.
- 9. The method of claim 8 wherein at least one NMOS transistor is formed in said p-well region.
- 10. The method of claim 8 wherein at least one PMOS transistor is formed in said n-well region.
- 11. The method of claim 8 wherein said n-well region and said p-well region have offset doping concentration profiles.
- 12. The method of claim 11 wherein for a PNP bipolar junction transistor, the depth of the p-well region is greater than the depth of the n-well region.
- 13. The method of claim 11 wherein for a NPN bipolar junction transistor, the depth of the n-well region is greater than the depth on the p-well region.
- 14. The method of claim 8 further comprising forming an emitter region of the bipolar junction transistor by simultaneously implanting the compensated base region of said bipolar junction transistor with an ion implantation process used to form the source and drain region of the PMOS transistor or the NMOS transistor.
Parent Case Info
This application claims priority under 35 USC §119(e)(1) of provisional application Serial No. 60/244,543, filed Oct. 31, 2000.
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Provisional Applications (1)
|
Number |
Date |
Country |
|
60/244543 |
Oct 2000 |
US |