Claims
- 1. A multi-layered ceramic circuit board comprising hybrid-laminated ceramic layers of a first ceramic powder material containing hollow silica and of a second ceramic powder material containing no hollow silica, the ceramic layers having resulted from firing the hybrid-laminated layers of green sheets of the first ceramic powder material containing hollow silica interposed between overlaying and underlying layers of green sheets of the second ceramic powder material containing no hollow silica, and electrically conductive layers being disposed in contact with at least the ceramic layers resulting from firing the green sheets of the first ceramic powder material containing the hollow silica, wherein the compositions of the first and second ceramic powder materials are controlled, so that the difference between the percentage of shrinkage of both green sheets during the firing thereof is within 1%; wherein the first ceramic powder material contains, as inorganic ingredients, 10 to 50% by volume of hollow silica, 20 to 50% by volume of borosilicate glass, more than 0% and not greater than 55% by volume of quartz glass, and 10 to 30% by volume of alumina; and the second ceramic powder material contains, as inorganic ingredients, 20 to 60% by volume of borosilicate glass, more than 0% and not greater than 65% by volume of quartz glass, and 10 to 50% by volume of alumina.
- 2. The circuit board of claim 1, which is free from failure resulting from the firing of the hybrid-laminated green sheets.
- 3. The circuit board of claim 1, wherein the first ceramic powder material contains, as inorganic ingredients, 10 to 30% by volume of hollow silica, 30 to 45% by volume borosilicate glass, 10 to 40% by volume of quartz glass, and 10 to 20% by volume of alumina.
- 4. The circuit board of claim 1, wherein the second ceramic powder material contains, as inorganic ingredients, 30 to 45% by volume of borosilicate glass, 20 to 50% by volume of quartz glass, and 10 to 30% by volume of alumina.
- 5. The circuit board of claim 1, wherein at least one surface of the multi-layered ceramic circuit board is polished, and has a surface roughness of approximately 0.01 micrometers.
- 6. The circuit board of claim 1, which has a dielectric constant of approximately 3.5.
Priority Claims (1)
Number |
Date |
Country |
Kind |
4-041098 |
Feb 1992 |
JPX |
|
Parent Case Info
This is a division of application Ser. No. 08/021,575 now U.S. Pat. No. 5,324,370, filed Feb. 24, 1993.
US Referenced Citations (9)
Foreign Referenced Citations (12)
Number |
Date |
Country |
59-111345 |
Jun 1984 |
JPX |
60-136294 |
Jul 1985 |
JPX |
60-254697 |
Dec 1985 |
JPX |
61-83674 |
Apr 1986 |
JPX |
62-206861 |
Sep 1987 |
JPX |
62-287658 |
Dec 1987 |
JPX |
2-83995 |
Mar 1990 |
JPX |
3-15160 |
Jun 1991 |
JPX |
4-119972 |
Apr 1992 |
JPX |
4-124074 |
Apr 1992 |
JPX |
4-217392 |
Aug 1992 |
JPX |
4-290492 |
Oct 1992 |
JPX |
Divisions (1)
|
Number |
Date |
Country |
Parent |
21575 |
Feb 1993 |
|