Claims
- 1. A method of manufacturing a non-volatile memory device having a part of a floating gate overlapping a part of a drain region formed in a semiconductor substrate, said method comprising the steps of:
- (a) forming a first insulation layer on the semiconductor substrate;
- (b) introducing impurity atoms into a part of the semiconductor substrate corresponding to the drain region, through the first insulation layer formed on the semiconductor substrate;
- (c) removing a portion of the first insulation layer overlapping the drain region on which the floating gate is to be formed, after the impurity atoms have been introduced into the semiconductor substrate, exposing a portion of the semiconductor substrate;
- (d) forming a second insulation layer on the exposed portion of the semiconductor substrate; and
- (e) forming the floating gate over the first insulation layer and on the second insulation layer.
- 2. A method of manufacturing a non-volatile memory device having a floating gate formed overlapping a portion of a drain formed in a semiconductor substrate of a first conductivity type, said method comprising the steps of:
- (a) forming a first insulation layer on the semiconductor substrate;
- (b) introducing ions, having a second conductivity type opposite the first conductivity type, through the first insulation layer and into a selected area of the semiconductor substrate;
- (c) removing a portion of the first insulation layer overlapping the selected area of the semiconductor substrate on which the floating gate is to be formed after the ions have been introduced into the semiconductor substrate;
- (d) forming a second insulation layer on the selected area of the semiconductor substrate;
- (e) forming the floating gate overlapping a portion of the selected area of the semiconductor substrate;
- (f) forming a third insulation layer on the floating gate;
- (g) forming a control gate on the third insulation layer overlapping the floating gate; and
- (h) forming a source region and the drain region adjacent to the selected area of the semiconductor substrate and separated by the selected area of the semiconductor substrate by introducing ions having the second conductivity type into the semiconductor substrate.
Priority Claims (1)
Number |
Date |
Country |
Kind |
55-187914 |
Dec 1980 |
JPX |
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Parent Case Info
This is a continuation of co-pending application Ser. No. 699,229 filed on Feb. 7, 1985, which is a continuation of application Ser. No. 583,782, filed Feb. 29, 1984, which is a continuation of application Ser. No. 333,813, filed on Dec. 23, 1981, all abandoned.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
4203158 |
Frohman-Bentchkowsky et al. |
May 1980 |
|
4302766 |
Gutterman et al. |
Nov 1981 |
|
4361847 |
Harari |
Nov 1982 |
|
Non-Patent Literature Citations (4)
Entry |
Carter, G. et al., Ion Implanatation of Semiconductors, John Wiley & Sons, New York, 1976, pp. 193-194. |
Scheibe et al., "Technology of . . . SIMOS", in IEEE Transactions on Electron Devices, vol. ed. 24, No. 5, May 1977, pp. 600-606. |
Rossler, B., "Electrically Erasable . . . SIMOS One-Transistor Cell", in IEEE Trans. on Electron Devices, 24(5), May '77, pp. 606-610. |
Beyer et al, "Reduction of Oxidation-Induced Defects Using Reactive Ion Etching", IBM Tech. Discl. Bulletin, vol. 22, #2, 7/79. |
Continuations (3)
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Number |
Date |
Country |
Parent |
699229 |
Feb 1985 |
|
Parent |
583782 |
Feb 1984 |
|
Parent |
333813 |
Dec 1981 |
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