Patent Application
20180277693
The invention relates to a method of manufacturing a solar cell comprising the steps of:
The invention also relates to a solar cell comprising a semiconductor substrate with a first side and an opposed second side, wherein a doped silicon layer overlies said electrically conductive region, and at least one metal contact is coupled to said doped silicon layer.
To advance solar cell manufacturing, particularly with a silicon substrate, and to obtain higher cell efficiencies, it is deemed necessary to reduce the amount of recombination losses of charge carriers inside the solar cell. One of the main causes of recombination losses in commercially available solar cells with monocrystalline silicon substrates are the metal contacts. These are made by screen printing pastes that contact the substrate using a fire-through technique. A known method to lower such recombination losses is the provision of a doped polysilicon layer as a buffer layer in between the silicon substrate and the metal contact in order to avoid direct contact between the two. A thin dielectric layer is suitably provided underneath the polysilicon layer which serves as a passivation layer, while being sufficiently thin to allow for tunnelling transport of charge carriers between the substrate and the polysilicon layer.
Such a solar cell and a method of manufacturing thereof are known from US2015/0162483A1. In the known method, the doped silicon layer is a an amorphous layer that is separated from the semiconductor substrate over a tunnel dielectric layer, for instance a silicon oxide layer with typically a thickness of about 2 nm. The amorphous silicon layer is suitably a hydrogenated silicon layer formed using a plasma-enhanced chemical vapour deposition (PECVD) process and includes Si—H covalent bonds throughout the layer. Dopants are provided by means of implantation, performed by ion beam implantation or plasma immersion implantation. Species of opposed conductivity type are implanted in two subsequent steps through a first and a second shadow mask, to define first and second implanted regions. Thereafter, the remaining non-implanted regions of the amorphous silicon layer are removed with a hydroxide-wet etchant that further forms trenches and/or texturizes exposed portions of the substrate. Subsequently, the implanted regions are annealed to form doped polycrystalline silicon emitter regions. Conductive contacts are thereafter fabricated to contact the first and second doped polycrystalline emitter regions. Suitably, the contacts are fabricated by first depositing and patterning an insulating layer to have openings and then forming one or more conductive layers in the openings.
As specified in paragraph [0076] of the said application, it was discovered that boron ion implantation of the silicon layer with a dose of at least 4E15 and energies between 5-15 keV can automatically impart high resistance to alkaline Si etch chemistries. However, no comparable selectivity was found to be possible using phosphorus ion implant conditions useful for doping n+ emitter regions. Therefore, US2015/0162483A1 proposes the application of very thin robust etch mask compositions exemplified by SiN, SiC or the use of polycarbosilane masking layers or the use of additional ion implantation of non-dopant species such as nitrogen or carbon.
This need for the application of a masking layer of either SiN, SiC or polycarbosilane or the use of additional implantation of non-dopant species is deemed disadvantageous. As observed in paragraph [0076] of the application, switching between plasma source chemistries (i.e. to deposit SiN or SiC) leads to compromised performance and particles, with more manufacturable solutions likely to involve sequential implant steps as part of an inline process flow based on stationary shadow masks equilibrated under each ion beam source. The implantation of nitrogen or carbon brings additional complexity in the application and could affect the electrical properties of the polysilicon layer negatively. Furthermore, the stated requirements for low energy implantation with a high dose of 8E15 cm-2 should render an extremely low throughput process, which therefore becomes very costly to implement in solar cell production.
One embodiment involves the use of graphite shadow masks. Such a process flow requires dedicated equipment and, as can be understood from the disclosure in [0076], it still has to be developed, so that it may well not succeed. In case of using a carbosilane layer, the implantation would be divided between the carbosilane layer and the underlying amorphous silicon layer. The etching is then to be assumed to be selective also for the carbosilane layer. Optionally, the doped portions of the carbosilane layer may be removed selectively to the underlying amorphous silicon layer portions after the first etching step. It is not disclosed how to achieve such selective etching. Furthermore, it is not clear how much doping will get into the amorphous silicon layer when the implantation is performed through a carbosilane layer.
It is therefore an object of the present invention to provide an improved method and an improved process for the manufacture of solar cells that contain a doped polysilicon layer at the second side between the metal contact and the semiconductor, particularly silicon substrate, preferably separated from the substrate by means of a tunnel dielectric. Preferably, the manufacturing method should be efficient from a processing perspective, reducing yield loss and providing good quality at sufficiently low price.
According to a first aspect, the invention provides a method of manufacturing a solar cell comprising the steps of:
It has been understood in investigations leading towards the invention, that the stated problems may be resolved by generating a phase transition within deposited silicon material, so as to allow selective removal of part of the deposited silicon material by means of etching. The phase transition is particularly one between polycrystalline and amorphized material, but could alternatively be between amorphous and amorphized, doped material. In this manner, any unintentionally deposited silicon at the first side can be removed. Furthermore, the silicon layer at the second side may be selectively removed. It has been found by the inventors in investigations leading to the invention, that there is sufficient etch selectivity between the first areas and the second areas. It was furthermore found that the selective etch may be carried out without negative effects on a pre-existing dopant layer near to the first side of the substrate, for instance because this layer is still protected by a dopant layer (such as a silicate glass).
According to the invention, creation of amorphized first areas is achieved by ion implantation at the second side, which simultaneously results in doping of the silicon layer and suitably also doping of the underlying substrate. Particularly, the ion implantation is carried out in a directional manner, so as to apply the ion implantation only to the second side, or optionally to selective areas of the second side. Compared to the use of deposited dopant sources, a better control of dopant diffusion is achieved, and release of dopants into the surrounding atmosphere (i.e. substrate) during the anneal is prevented. Such release may lead to shunting effects, diminished solar cell performance and other artefacts.
In addition to achieving herewith an appropriate etch selectivity, it has been found that the use of implantation in a manner and with a doping dose configured for amorphisation, has a positive effect on the dopant distribution. Particularly, the amorphized silicon layer may be recrystallised by means of an anneal step. Such recrystallisation is based on solid phase epitaxial growth, for which some grains that survived the implantation process may serve as seeds. The dopant is integrated into the crystal lattice in this recrystallisation step. Therewith, the risk of recombination of charge carriers in the substrate is reduced.
More particularly, the silicon layer is provided in a Low-Pressure Chemical Vapour Deposition (LPCVD) process. The use of LPCVD has the advantage over other CVD processes such as plasma-enhanced CVD (PECVD), that better silicon layers are formed. Particularly, conformal layers are formed (conformal to any texture on the substrate). This reduces formation of pinholes. Such minimization of pinholes is relevant for the preferred embodiment of the present invention, wherein use is made of passivated contacts, because pinholes will lead to a higher recombination of charge carriers. The silicon layer is particularly deposited as polysilicon. However, because of subsequent amorphisation and recrystallisation in the course of an anneal, it is not deemed essential that the initially deposited layer is polysilicon or entirely polysilicon. Rather, it may be deemed beneficial to deposit the layer close to the transition temperature between amorphous and polysilicon. The benefit hereof is for instance that the grain size is quite uniform and not too big. In one embodiment, the deposition temperature is in the range of 500-650° C., for instance 520-600° C. or 580-620° C.
In this respect, it is believed by the inventor of the present invention that the application of hydrogenated amorphous silicon in the prior art may have a negative impact on the etch selectivity between phosphorus-implanted material and amorphous material. By using LPCVD for the deposition of the silicon layer, the resulting silicon layer has a different structure, and implantation of phosphorus will result in structural change resulting in etch selectivity between the amorphized material in the first areas and the material in the second areas. The use of LPCVD for the tunnel dielectric is deemed to contribute further to the excellent passivation properties achieved in the invention.
Furthermore, solar cells manufactured in accordance with the invention have been found to have an exceptionally good passivation performance for LPCVD poly-Si doped with ion implantation. Values for the open circuit voltage (Voc) of higher than 730 mV have been obtained in experiments. This passivation performance is deemed due to the use of LPCVD and the extension of the implanted ions into the substrate to form a second electrically conductive region, more particularly a back surface field. Preferably a PECVD SiNx:H layer is applied on top of the recrystallised silicon layer, so as to provide atomic hydrogen during a subsequent heating step that can help passivate defects inside the substrate and applied layers. In one implementation, the ion implantation step is carried out at the second side in a mask-less manner, particularly using directional ion beams. This effectively results therein that the first area is on the second side of the substrate, whereas the second area is the first side of the substrate with its unintentional polysilicon deposition. Such an approach is feasible for a variety of cell concepts, including for instance solar cells of the conventional H-type electrode design at the first side, and solar cells with through-wafer vias (MWT-cells).
In a further embodiment of the method of the invention, the deposited silicon material (to be implanted) is in situ doped, and the implantation is used to increase a doping level of this silicon material and preferably also the underlying substrate. Therewith, the implantation dose required to obtain a specified resistivity is lowered. Still the implantation may be used to achieve the amorphisation desired for the selective etching.
In an advantageous embodiment, the implanted dopant is applied into the silicon layer and into the substrate. This provision is the result of both the implantation step and the anneal step. Importantly, it was found by the present inventor that the implantation of phosphorus into the substrate does not deteriorate any dielectric between the substrate and the silicon layer, more particularly a tunnel dielectric, such as a tunnel oxide. Even though the tunnel dielectric may have some damage initially, such damage is again removed during the anneal step, particularly for a dopant of n-type conductivity, such as phosphorus. The benefit of the implantation into the substrate is a reduction of the substrate resistivity.
Preferably, the dopant concentration ratio of the dopant in the silicon layer and the second electrically conductive region at the opposed side of the tunnel dielectric is at least two, more preferably at least 10 and suitably in the range of 100-1000. Such a concentration ratio is deemed beneficial for the enhancement of the passivation properties of the cell. It is observed that the second electrically conductive region is herein defined as the substrate region at the interface with the tunnel dielectric, more particularly within the first micrometer of the substrate. Particularly, the doped silicon layer is highly doped, particularly at least 1E18/cm3, more preferably at least 1E19/cm3 or even 0.5-5E20/cm3. It is also with such high dopant concentrations that good passivating properties are obtained, and hence that there is no flow of dopant atoms through the tunnel dielectric into the bulk of the substrate.
More preferably, in one implementation, the thickness of the silicon layer at the second side is at most 50 nm, more preferably at most 30 nm. Such a thickness of the silicon layer has been found to provide sufficient implantation into the substrate. Alternatively, the silicon layer may be larger than 50 nm, for instance a thickness in the order of 50-400 nm, preferably 100-250 nm.
In again a further embodiment, the anneal treatment is carried out so as to generate a thermal oxide. On top of the thermal oxide one or more passivating layers of silicon nitride, silicon oxynitride and silicon oxide may be deposited. Use of silicon nitride, that also functions as an antireflection coating (ARC) is preferred.
In a further implementation, the doped polysilicon areas at the second side are contacted by means of metal contacts. One preferred way of providing such contacts is the use of a metal paste, more particularly a silver paste. Such pastes are also known as fire-through pastes, in that they may be applied by screen printing without a need to separately create openings in the passivation layer, i.e. the paste will go through the passivation layer by itself. Surprisingly, it was found that the use of such metal paste provides a good contact to the LPCVD deposited, amorphised and recrystallised silicon layer. Particularly, it was found that the paste does not extend through the silicon layer and does not damage the underlying tunnel dielectric. Notwithstanding this preferred option, it is not excluded that the contacts may be provided in a different manner, for instance in a process using electroplating.
According to a second aspect, the invention relates to a solar cell comprising a semiconductor substrate with a first side and an opposed second side, which semiconductor substrate is provided with a first electrically conductive region of a first conductivity type adjacent to the first side and with a second electrically conductive region adjacent to the second side. The first electrically conductive region herein preferably contains boron and the second electrically conductive region comprises phosphorus. The first electrically conductive region constitutes an emitter and the second electrically conductive region constitutes a back surface field, wherein a doped silicon layer overlies said electrically conductive region and is separated therefrom through a tunnel dielectric, and at least one metal contact is coupled to said doped silicon layer. Herein, the doped silicon layer is a recrystallized, ion-implanted layer and the second electrically conductive region is doped by ion implantation.
The solar cell of the present invention may be provided at a lower cost price without loss in quality, and particularly with an excellent open circuit voltage and passivation performance. The presence of a conductive region in the substrate underlying a tunnel dielectric and one or more (poly)silicon-based contact layer, results in a low series resistance, as desired. An additional advantage is that the passivation is no longer fully dependent on the tunnel dielectric, which can be vulnerable and may be disrupted with minor contamination.
In a further embodiment, the resulting solar cell comprises metallic conductors extending in through-holes from the first to the second side of the substrate. One embodiment of such a solar cell is known as a metal-wrap-through (MWT) solar cell. Variations of the MWT solar cell, such as the EWT (Emitter-wrap-through) are however by no means excluded. Such a solar cell with a metallic conductor more particularly comprises an isolation between the conductor and/or a contact thereof that is exposed at the second side, and the first areas of the doped polysilicon layers. Several implementations are feasible for generating such an electrical isolation. According to a first one thereof, the doped polysilicon layer is removed outside the first areas. This generates sufficient distance. Preferably, an insulating layer, such as an oxide or a nitride, is deposited on the second side prior to the provision of the metallic conductor. According to a second implementation, an insulating layer is deposited on top of the polysilicon layer, especially in a fourth area. The through-hole is generated within said fourth area, and the metal conductor is then provided. A metal contact terminating the conductor—constituting part of the conductor or being a separate element—is then defined on top of the insulating layer within the fourth area. The provision of the insulating layer may be effected in various manners. One suitable option is printing the insulating layer, for instance by screen printing. One further implementation resides in the use of a so-called electrically insulating polymer paste. Such a paste is for instance based on ceramic materials. As any conductive paste conventionally used in solar cell manufacture, such as paste is able to withstand a final anneal, and/or be converted therein to an inorganic material.
According to a further embodiment, a passivation is applied onto the silicon layer(s), such as the emitter contact layer and the base contact layer. This passivation comprises in one embodiment a silicon nitride layer. In an alternative embodiment, the passivation may contain a silicon oxynitride. In a further embodiment, the passivation comprises an oxide layer, such as a thermal oxide, and a nitride or oxynitride layer. The passivation may further contain a multiple layer comprising a nitride layer, an oxide layer and another nitride layer. In again a further embodiment, the passivation is applied both to the first side and to the second side. This is most suitably done in a chemical vapour deposition process, for instance a phase enhanced chemical vapour deposition process. The application of a passivation including a nitride layer is deemed suitable, as it may be used as an anti-reflection layer on the first side, and for the provision of a buffer layer on top of the polysilicon. Such a buffer layer is particularly desired when applying contacts in a fire-through technique by means of conductive paste. The buffer layer is deemed to improve adhesion. Moreover, hydrogen will be desorbed from the nitride layer during such a firing-through step. This desorbed hydrogen may migrate into the tunnel oxide, which will improve the quality thereof.
Most preferably, the passivation is locally opened and metal contacts are generated, which extend to the polysilicon material. If desired, a contact material may be applied first. Such a contact material most suitably forms a silicide with the polysilicon. The contact material is for instance a metal or alloy, such as nickel, tungsten, titanium tungsten, or a conductive oxide or particularly conductive nitride, such titanium nitride or the like. In a further embodiment, the passivation is locally opened by means of a firing-through technique. Herein, firing-through contacts are applied onto the nitride-containing passivation layer on the second side. The contacts will then be fired through the passivation, such that no separate opening of the passivation is required. More particularly, use is made of a silver-based conductive paste
In one further embodiment, the anneal treatment is carried out simultaneously with the formation of the oxide, which is then a thermal oxide. This anneal is then used to recrystallize the amorphized polysilicon and thus to increase the crystallinity of the deposited polysilicon. The anneal is further used to diffuse dopant of opposite polarity, if any into the silicon layer, to (further) diffuse any charge carriers within the semiconductor substrate and to generate the thermal oxide. It is further observed that the formation of this thermal oxide will reduce a thickness of the polysilicon layer. The consumed thickness is suitably at most 10% of the total thickness of the polysilicon layer as deposited.
These and other aspects of the method and the device of the invention will be further elucidated with reference to the FIGURES, wherein:
The Figures are not drawn to scale and are merely intended for illustrative purposes. Equal reference numerals in different FIGURES refer to equal or corresponding elements.
The silicon layer 5 is suitably deposited in a low-pressure chemical vapour deposition (LPCVD) process. The deposition temperature is suitably at least 500° C., for instance in the range of 500-650° C. It is deemed beneficial that the silicon material is at least partially polycrystalline, but that has been found not to be strictly necessary, not even to obtain a sufficient etch selectivity. The thickness of the silicon layer 5 is for instance a thickness of up to 200 nm, for instance 100-200 nm and preferably 50-150 nm. The substrates 1 are preferably loaded in the LPCVD reactor in a front-to-front configuration. Even though limitation of the silicon deposition is not strictly necessary in view of the subsequent etching process, the front-to-front loading is deemed beneficial so as to maximize the number of substrates per reactor.
The implantation is typically carried out in one-sided processing, by providing a ion bombardment from a source. As a consequence, the implantation will at least largely arrive at the second side 1b of the substrate 1. In one implementation, the stack of the dopant layer 4 and silicon layer 5 at the first side 1a of the substrate 1 may be used as a carrier for the substrate 1 in this implantation step, therewith further minimizing the implantation into the silicon layer 5 on the first side 1a of the substrate 1. The dose is chosen to achieve amorphisation of the silicon layer 5 at the second side 1b of the substrate 1. It is not excluded that part of the substrate 1 is also amorphized.
It is observed that the etch selectivity is also achieved between the amorphized and doped silicon layer and an amorphous silicon layer, particularly when using phosphorus ions for the ion implantation. The etch selectivity is further achieved between amorphized silicon layer on the one hand, and recrystallized silicon after amorphisation. The exact mechanism of the etch selectivity is not known. Possibly, the ion implantation removes a native oxide and modifies the crystal lattice, for instance by forming a kind of alloy, more particularly an allow between Si and P and/or Si and As. It may then be more difficult for the alkaline etch, particularly based on hydroxide ions, to attack the silicon, for instance because of selective oxidation of the dopant (especially phosphorus), or because that the free electrons of the oxygen are not able to attack a Si—Si molecular orbital.
Subsequently, a second etch step is carried out, wherein the dopant layer 4 is removed. Because the dopant layer comprises silicate glass, it can be selectively etched relatively to the doped silicon layer.
Experiments were carried out with test samples. Herein, a Czochralski-type and polished n-doped monocrystalline silicon substrate of a thickness of 200 μm was inserted into an LPCVD furnace and provided with a tunnel oxide of approximately 2 nm and a silicon layer, both on the first side and the second side. Deposition temperature was at about 580° C. and the silicon layers were deposited in a thickness of 100-120 nm. The silicon layers were thereafter treated by ion implantation to obtain a doping level of about 2E20 cm−3. The silicon layer was recrystallized and thermally oxidized, to generate a thermal oxide with a thickness of about 8 nm. Thereafter, a PECVD SiNx:H layer was deposited to a thickness of 80 nm, on both side of the substrate. A rapid firing step was carried out to release hydrogen out of the nitride.
Characterisation of the passivation quality was carried out by means of a QSSPC measurement using a WCT-120 tool available from Sinton Instruments. The passivation performance assessed by QSSPC measurement on test samples with an Phosphorus implant doped polysilicon layer on both sides showed that the lifetime reached 7.2 ms at an injection level of 1E15 cm−3, while the recombination current J0 became as low as 1.8 fA/cm2 per side extracted near to a 1E16 cm−3 injection level. These values demonstrate the high passivation quality that can be obtained with n-type doped LPCVD polysilicon layers. The implied Voc was around 740 mV.
Thus, in summary, the invention relates to a process for manufacturing a solar cell, which is provided with a so-called passivated contact based on a layer of polysilicon layer onto a tunnel dielectric, such as a tunnel oxide. The process for manufacturing a solar cell provides for so-called passivated contacts based on a layer of polysilicon layer onto a tunnel dielectric, such as a tunnel oxide. Herein, a treatment is carried out on the polysilicon layer as deposited by ion implantation so as to render it to an amorphized state. This ion implantation simultaneously allows the provision of doped regions, particularly of phosphorus. Selectively recrystallized areas and untreated areas are then removed by etching, including unintentionally deposited polysilicon at the first side of the substrate. Further process steps may be carried out prior to or subsequent to this provision of a patterned and ion implanted polysilicon layer, so as to provide for instance a cell with a metal wrap-through (MWT) structure.
The electrically conductive region in the first side of the substrate is suitably provided in a diffusion process. The resulting silicate glass, for instance a borosilicate glass is preferably removed from the first side after the implantation step. In this manner, the borosilicate glass acts as a protective layer to fully prevent that the implanted dopant reaches the first side of the substrate.
In one embodiment, the method further comprises the provision of a dielectric layer on the second side prior to deposition of the silicon material, said dielectric layer being sufficiently thin to act as a tunnel dielectric, and wherein the treatment step is carried out so that the implanted ions further create a doped layer in the substrate adjacent to the tunnel dielectric. This is particularly suitable if the implanted dopant is phosphorus.
In one embodiment, the silicon material is further deposited at the first side, which silicon material forms part of the second areas and is etched away in the etching step. Thus, the silicon deposited can be carried out in conventional manner, more especially in an LPCVD reactor, without need for single sided deposition. This enhances productivity, also because it allows for a large amount of substrates to be processed at the same time in the LPCVD reactor.
In one embodiment, the treatment further comprises selective recrystallisation of part of the amorphized and doped silicon layer at the second side, so as to create second crystalline areas at the second side, which are selectively removed in the etching step. This has the advantage that the ion implantation may be carried out in a mask-less manner, while yielding a doping pattern on the second side.
In one embodiment, the method further comprises the step of annealing the substrate, which step is carried out after the etching step.
In one embodiment, the method further comprises the provision of a metallic conductor extending in a through-hole from the first to the second side of the substrate, and terminating at the second side of the substrate in a contact that is electrically isolated from the doped silicon layer by means of an electrically insulating layer. Suitably, the insulating layer is patterned and arranged adjacent to metal contacts connected to the doped silicon layer.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015534 | Sep 2015 | NL | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/NL2016/000017 | 9/30/2016 | WO | 00 |
