Patent Application
20230296949
The present application is based on, and claims priority from JP Application Serial Number 2022-043555, filed on Mar. 18, 2022, the disclosure of which is hereby incorporated by reference herein in its entirety.
The present disclosure relates to a method of manufacturing an electro-optical device.
JP-A-2012-123142 discloses a structure of a capacitance element in which a dielectric layer is interposed between a first electrode at a lower layer and a second electrode at an upper layer.
A method of manufacturing a capacitance element includes forming the first electrode and also forming the dielectric layer at the first electrode. Next, an oxide film is formed. The oxide film functions as an etching stopper layer when the second electrode is formed. After this, a portion of the oxide film that is to be a capacitance element is removed, and a film that is to be the second electrode is formed on the dielectric layer and the oxide film. Lastly, by using the oxide film as an etching stopper layer, the second electrode is formed through an etching process, whereby a capacitance element is completed.
The capacitance element is formed along a protruding shape as in JP-A-2015-094880 or formed along a recessed shape, whereby it is possible to obtain capacitance while achieving miniaturization.
However, in a case of a typical capacitance element, when the capacitance element is formed especially along the recessed shape, there is a problem in that the oxide film used as the etching stopper layer cannot be removed in the capacitance element having the recessed shape, and is left there.
A method of manufacturing an electro-optical device includes forming a recessed portion at an insulating member, forming a first capacitance electrode, a capacitance insulation film, and a second capacitance electrode along the recessed portion, concurrently patterning the first capacitance electrode, the capacitance insulation film, and the second capacitance electrode, removing a portion of the second capacitance electrode, forming an interlayer insulating film, and etching, until a portion of the first capacitance electrode is exposed in plan view, a region where the portion of the second capacitance electrode is removed, to form a first contact hole penetrating through the interlayer insulating film and the capacitance insulation film.
In each of the following drawings, description will be made on the assumption that three axes perpendicular to each other are the X-axis, the Y-axis, and the Z-axis. The direction along the X-axis is the “X direction”. The direction along the Y-axis is the “Y direction”. The direction along the Z-axis is the “Z direction”. The arrowed direction is the +direction. The direction opposite to the +direction is the −direction. Note that the +Z direction may be referred to as “up” or “upward”. The −Z direction may be referred to as “down” or “downward”. The view from the +Z direction may be referred to as plan view or planar view. Furthermore, description will be made on the assumption that a surface located at the +side in the Z direction is an upper surface, and a surface that is located at the −side in the Z direction and is opposite from the upper surface is a lower surface.
In addition, in the following description, for example, description of a substrate as “on the substrate” represents a case of being disposed on the substrate in a contact manner, or a case of being disposed above the substrate with another structure being interposed therebetween, or a case of being disposed at the substrate such that a portion is in contact with the substrate and a portion is disposed above the substrate with another structure being interposed between the portion and the substrate.
First, with reference to
As illustrated in
For example, a substrate such as a glass substrate or a quartz substrate is used for a substrate 10a of the element substrate 10. For example, a transparent substrate such as a glass substrate or a quartz substrate is used for a substrate 20a of the counter substrate 20.
The shape of the element substrate 10 in plan view is greater than the counter substrate 20. The element substrate 10 and the counter substrate 20 are joined to each other with a seal material 14 being interposed therebetween. The seal material 14 is disposed along the outer edge of the counter substrate 20. Liquid crystal having positive or negative dielectric anisotropy is encapsulated in a gap between the element substrate 10 and the counter substrate 20 to provide the liquid crystal layer 13.
A display region E is provided inside of the seal material 14. The display region E contains a plurality of pixels P arrayed in a matrix manner. The outside of the display region E is a peripheral area F. In the peripheral area F, a partition portion 23 is provided between the seal material 14 and the display region E so as to surround the display region E. A dummy pixel area that does not contribute to displaying and is not illustrated in the drawing is provided at a portion of the peripheral area F that is located at the most display region E side.
A terminal portion including a plurality of external connection terminals 43 arrayed therein is provided in the peripheral area F of the element substrate 10. In the peripheral area F, a data line driving circuit 47 is provided between a first side portion extending along the terminal portion and the seal material 14. In addition, in the peripheral area F, an inspection circuit 41 is provided between the display region E and the seal material 14 along a second side portion that is opposed to the first side portion.
In the peripheral area F, a scanning line drive circuit 45 is provided between the display region E and the seal material 14 along a third side portion and a fourth side portion that are opposed to each other and are each perpendicular to the first side portion. Furthermore, a plurality of wiring lines 49 coupling two scanning line drive circuits 45 are provided between the inspection circuit 41 and the seal material 14 at the second side portion.
Wiring lines coupled to the data line driving circuit 47 and the scanning line drive circuit 45 are coupled to the plurality of external connection terminals 43 arrayed along the first side portion. Note that the arrangement of the inspection circuit 41 is not limited to that described above.
As illustrated in
The partition portion 23, an insulating film 25 formed by covering the partition portion 23, a counter electrode 21 provided as a common electrode and formed by covering the insulating film 25, and an alignment film 22 that covers the counter electrode 21 are provided at the front surface of the substrate 20a at the liquid crystal layer 13 side. The counter substrate 20 according to the present embodiment includes at least the partition portion 23, the counter electrode 21, and the alignment film 22. Note that the present embodiment gives an example in which the common electrode is provided as the counter electrode 21 at the counter substrate 20 side. However, the arrangement is not limited to this.
As illustrated in
The insulating film 25 is made, for example, of an inorganic material such as a silicon oxide (Si02) having optical transparency. The insulating film 25 is provided so as to cover the partition portion 23 and flatten the front surface at the liquid crystal layer 13 side.
The counter electrode 21 covers the insulating film 25, and is electrically coupled to an upward-downward conduction portion 7 provided at four corners of the counter substrate 20. The upward-downward conduction portion 7 is electrically coupled to a common wiring line 9 that will be described later.
The pixel electrode 15 and the counter electrode 21 are made, for example, of a transparent electrically conducting film made of indium tin oxide (ITO), indium zinc oxide (IZO), or the like. The alignment film 12 and the alignment film 22 are selected on the basis of optical design of the liquid crystal device 100. The material used to form the alignment films 12, 22 includes an inorganic alignment film made of silicon oxide or the like, and an organic alignment film made of polyimide or the like.
Such a liquid crystal device 100 employs optical design including a normally white mode in which the transmittance of a pixel P when no voltage is applied is greater than the transmittance when a voltage is applied, and a normally black mode in which the transmittance of a pixel P when no voltage is applied is lower than the transmittance when a voltage is applied. In the liquid crystal device 100, a polarizing element is disposed at a light entering side and a light outputting side in accordance with the optical design.
Hereinafter, the present embodiment describes an example in which an inorganic alignment film that has been described above is used as the alignment films 12, 22, liquid crystal having negative dielectric anisotropy is used, and the normally black mode is applied as the optical design.
In addition, the embodiment described above employs the liquid crystal device 100 of a transmissive type as an example of the electro-optical device. However, a reflective type liquid crystal device or a liquid crystal device of liquid crystal on silicon type (LCOS) may be used as the liquid crystal device 100.
Furthermore, description has been made of the liquid crystal device 100 as one example of the electro-optical device. However, the electro-optical device is not limited to this. For example, it may be possible to apply the present disclosure to an organic electro luminescence (EL) device, an electrophoretic display panel using a micro capsule, or the like.
Next, the configuration of the pixel P will be described with reference to
First, as illustrated in
The plurality of interlayer insulating films 11 include, in the order from below: a first interlayer insulating film 11a including a portion of the capacitance element 40; a second interlayer insulating film 11b including the scanning line 3; a third interlayer insulating film 11c including a semiconductor layer 30a; a fourth interlayer insulating film 11d including a gate electrode 30g; a fifth interlayer insulating film 11e including a relay electrode 5c; a sixth interlayer insulating film 11f including the data line 6 and a capacitance line 8; and a seventh interlayer insulating film 11g including the common wiring line 9.
The material of the plurality of interlayer insulating films 11 includes, for example, silicon oxide (None-doped Silicate Glass: NSG) or silicon nitride or the like. In the present embodiment, silicon oxide is used as the material used to form the interlayer insulating films 11.
In the capacitance element 40, a first capacitance electrode 40a, a capacitance insulation film 40b, and a second capacitance electrode 40c are stacked sequentially from the substrate 10a side. The material of the first capacitance electrode 40a and the second capacitance electrode 40c includes, for example, electrically conductive polysilicon. A dielectric material is used as the material of the capacitance insulation film 40b. The dielectric material includes, for example, silicon nitride, silicon oxide, hafnium oxide, aluminum oxide, tantalum oxide, and the like, and these films are used as a single layer or in combination.
As illustrated in
The scanning line 3 also functions as a light shielding film, and is provided at the first interlayer insulating film 11a. The scanning line 3 is provided along the X direction and between a pixel P and a pixel P in plan view as illustrated in
The transistor 30 includes: the semiconductor layer 30a provided at the second interlayer insulating film 11b; the third interlayer insulating film 11c functioning as a gate insulating film; and the gate electrode 30g provided at the third interlayer insulating film 11c. A lightly doped drain (LDD) structure is formed at the semiconductor layer 30a of the transistor 30. The semiconductor layer 30a is made, for example, of electrically conductive polysilicon. The gate electrode 30g is made, for example, of electrically conductive polysilicon. The semiconductor layer 30a extends along the Y direction that is the first direction in plan view as illustrated in
The gate electrode 30g is electrically coupled to the scanning line 3 through contact electrodes 51 and 52. The contact electrodes 51, 52 extend through the third interlayer insulating film 11c and the second interlayer insulating film 11b.
The relay electrode 5a is electrically coupled to a source drain region 30d and the first capacitance electrode 40a through a contact electrode 53 provided so as to extend through the third interlayer insulating film 11c, the second interlayer insulating film 11b, the first interlayer insulating film 11a, and the capacitance insulation film 40b.
The relay electrode 5b is electrically coupled to the second capacitance electrode 40c through a contact electrode 54 provided so as to extend through the third interlayer insulating film 11c, the second interlayer insulating film 11b, and the first interlayer insulating film 11a.
The data line 6 extends in the Y direction and between a pixel P and a pixel P as illustrated in
The capacitance line 8 and the common wiring line 9 are electrically coupled to the counter electrode 21, and are provided with a common potential. As with the data line 6, for the material used to form the capacitance line 8 and the common wiring line 9, it may be possible to use any material as long as the material is a wiring line material having electrical conductivity and low resistance, and the material includes, for example, a metal such as aluminum (Al) or titanium (Ti), or a metallic compound thereof.
The pixel electrode 15 is provided at the seventh interlayer insulating film 11g. The pixel electrode 15 is made, for example, of a transparent electrically conducting film such as ITO.
Although illustration is not given, the pixel electrode 15 is covered to provide the alignment film 12. The alignment film 12 of the element substrate 10 and the alignment film 22 of the counter substrate 20 described above are made of a collective body of columns obtained by depositing an inorganic material such as silicon oxide in a predetermined direction such as a diagonal direction to grow it into a column shape. Furthermore, liquid crystal molecules contained in the liquid crystal layer 13 illustrated in
Next, a method of manufacturing the liquid crystal device 100 will be described with reference to
Note that, basically, the element substrate 10 can be manufactured by using known methods in semiconductor processing including a low-pressure chemical vapor deposition (CVD) method, an atmospheric pressure CVD, a plasma CVD process, a photolithography method, a sputtering method, an etching method, a chemical mechanical planarization (CMP), or a combination thereof. Below, a preferred manufacturing method will be mainly described. However, it may be possible to employ different manufacturing methods, provided that an equivalent structure can be formed and functions and characteristics of the configuration can be satisfied.
In the process illustrated in
In the process illustrated in
In the process illustrated in
In the process illustrated in
In the process illustrated in
In the process illustrated in
First, the third interlayer insulating film 11c also functioning as a gate insulating film and made of silicon oxide or the like is formed at the substrate 10a. Next, the contact holes CNT1 and CNT2 are formed at positions that overlap with the extended portions 3a and 3b of the scanning line 3 in plan view, so as to extend through the third interlayer insulating film 11c and the second interlayer insulating film 11b, and a portion of the scanning line 3 is exposed.
In the process illustrated in
Specifically, the contact hole CNT3 is formed at a position that overlaps in plan view with the portion of the second capacitance electrode 40c removed in the process illustrated in
Note that, a portion of the third interlayer insulating film 11c covering the source drain region 30d of the semiconductor layer 30a is removed at the entrance side of the contact hole CNT3. This creates a state in which a portion of the source drain region 30d of the semiconductor layer 30a is exposed.
At the same time, the contact hole CNT4 is formed at a position that overlaps in plan view with the portion 40c2 of the second capacitance electrode 40c, so as to extend through the third interlayer insulating film llc, the second interlayer insulating film 11b, and the first interlayer insulating film 11a, and a portion of the second capacitance electrode 40c is exposed.
In the process illustrated in
This makes the gate electrode 30g electrically coupled to the scanning line 3 through the contact electrodes 51 and 52. The relay electrode 5a is electrically coupled to the source drain region 30d and the first capacitance electrode 40a through the contact electrode 53. That is, the contact electrode 53 also functions as a source drain electrode. The relay electrode 5b is electrically coupled to the second capacitance electrode 40c through the contact electrode 54.
In addition, as described above, since the first capacitance electrode 40a, the capacitance insulation film 40b, and the second capacitance electrode 40c are patterned concurrently, it is possible to improve the positional accuracy of the formed capacitance element 40. Furthermore, since the capacitance element 40 is formed at the recessed portion 10b, it is possible to obtain capacitance while achieving miniaturization. In addition, since the etching stopper layer for removing a portion of the second capacitance electrode 40c is not formed, it is possible to prevent the etching stopper layer from being left in the capacitance element 40.
In the process illustrated in
In the process illustrated in
The process illustrated in
As described above, the method of manufacturing the liquid crystal device 100 according to the present embodiment includes steps of: forming the recessed portion 10b in the substrate 10a; forming the first capacitance electrode 40a, the capacitance insulation film 40b, and the second capacitance electrode 40c along the recessed portion 10b; concurrently patterning the first capacitance electrode 40a, the capacitance insulation film 40b, and the second capacitance electrode 40c; removing a portion of the second capacitance electrode 40c; forming the interlayer insulating films 11a, 11b, 11c; and etching a region where a portion of the second capacitance electrode 40c is removed, until a portion of the first capacitance electrode 40a is exposed in plan view, to form the contact hole CNT3 extending through the interlayer insulating films 11a, 11b, 11c and the capacitance insulation film 40b.
With this method, the first capacitance electrode 40a, the capacitance insulation film 40b, and the second capacitance electrode 40c are concurrently patterned. This makes it possible to improve the positional accuracy of the formed capacitance element 40. In addition, as the capacitance element 40 is formed along the recessed portion 10b, it is possible to obtain capacitance while achieving miniaturization. In addition, since the etching stopper layer for removing a portion of the second capacitance electrode 40c is not formed, it is possible to prevent the etching stopper layer from being left in the capacitance element 40.
In addition, in the method of manufacturing the liquid crystal device 100 according to the present embodiment, it is preferable that the capacitance insulation film 40b contains silicon nitride. With this method, as the capacitance insulation film 40b contains silicon nitride, it is possible to improve the performance of the capacitance element 40.
In addition, in the method of manufacturing the liquid crystal device 100 according to the present embodiment, it is preferable that the step of forming the contact hole CNT3 includes concurrently forming the contact hole CNT4 for electrically coupling the second capacitance electrode 40c and the capacitance line 8. With this method, the contact holes CNT3 and CNT4 coupled to the two capacitance electrodes 40a and 40c, respectively, are concurrently formed. This makes it possible to reduce the number of steps.
In addition, in the method of manufacturing the liquid crystal device 100 according to the present embodiment, it is preferable that the recessed portion 10b extends along the Y direction at a position overlapping the semiconductor layer 30a of the transistor 30 that extends along the first direction. With this method, the recessed portion 10b is formed so as to overlap with the semiconductor layer 30a. This makes it possible to maintain the opening ratio without reducing the opening area between a pixel P and a pixel P.
In addition, in the method of manufacturing the liquid crystal device 100 according to the present embodiment, it is preferable that, after forming the first interlayer insulating film 11a, the method includes forming the scanning line 3 and forming the transistor 30 at a position overlapping the scanning line 3 in plan view, and before the gate electrode 30g of the transistor 30 is formed, the contact hole CNT3 is formed. With this method, the contact hole CNT3 is formed before the gate electrode 30g is formed. This makes it possible to form the contact electrode 53 at the same time as the gate electrode 30g.
In addition, in the method of manufacturing the liquid crystal device 100 according to the present embodiment, it is preferable that the contact electrode 53 also functioning as a source drain electrode is formed concurrently with the gate electrode 30g so as to be in contact with the first capacitance electrode 40a through the contact hole CNT3. With this method, it is possible to also form the source drain electrode concurrently with the gate electrode 30g, which makes it possible to reduce the number of steps.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-043555 | Mar 2022 | JP | national |
