Method of manufacturing optical devices and related improvements

Description

FIELD OF INVENTION

[0001] This invention relates to a method of manufacturing of optical devices, and in particular, though not exclusively, to manufacturing integrated optical devices or optoelectronic devices, for example, semiconductor optoelectronic devices such as laser diodes, optical modulators, optical amplifiers, optical switches, and the like. The invention further relates to Optoelectronic Integrated Circuits (OEICs) and Photonic Integrated Circuits (PICs) including such devices.

BACKGROUND OF INVENTION

[0002] Quantum Well Intermixing (QWI) Well Intermixing (QWI) is a process which has been reported as providing a possible route to monolithic optoelectronic integration. QWI may be performed in III-V semiconductor materials, eg Aluminium Gallium Arsenide (GaAs) Arsenide (AlGaAs) and Indium Gallium Arsenide (GaAs) Arsenide Phosphide (InGaAsP), which may be grown on binary substrates, eg Gallium Arsenide (GaAs) Arsenide (GaAs) or Indium Phosphide (InP). QWI alters the band-gap of an as-grown structure through interdiffusion of elements of a Quantum Well Intermixing (QWI) and associated barriers to produce an alloy of the constituent components. The alloy has a band-gap which is larger than that of the as-grown Quantum Well (QW). Any optical radiation (light) generated within the Quantum Well (QW) where no QWI has taken place can therefore pass through a QWI or “intermixed” region of alloy which is effectively transparent to the said optical radiation.

[0003] Various QWI techniques have been reported in the literature. For example, QWI can be performed by high temperature diffusion of elements such as Zinc into a semiconductor material including a Quantum Well (QW).

[0004] QWI can also be performed by implantation of elements such as silicon into a Quantum Well (QW) semiconductor material. In such a technique the implantation element introduces point defects in the structure of the semiconductor material which are moved through the semiconductor material inducing intermixing in the Quantum Well (QW) structure by a high temperature annealing step.

[0005] Such QWI techniques have been reported in “Applications of Neutral Impurity Disordering in Fabricating Low-Loss Optical Waveguides and Integrated Waveguide Devices”, Marsh et al, Optical and Quantum Well Intermixing (QWI) Electronics, 23, 1991, s941-s957, the content of which is incorporated herein by reference.

[0006] A problem exists with such techniques in that although the QWI will alter (increase) the band-gap of the semiconductor material post-growth, residual diffusion or implantation dopants can introduce large losses due to the free carrier absorption coefficient of these dopant elements.

[0007] A further reported QWI technique providing intermixing, is Impurity Free Vacancy Diffusion (IFVD) When performing IFVD the top cap layer of the III-V semiconductor structure is typically GaAs or Indium Gallium Arsenide (GaAs) Arsenide (InGaAs). Upon the top layer is deposited a silica (S1O2) film. Subsequent rapid thermal annealing of the semiconductor material causes bonds to break within the semiconductor alloy and Gallium Arsenide (GaAs) ions or atoms—which are susceptible to silica (SiO2)—to dissolve into the silica so as to leave vacancies in the cap layer. The vacancies then diffuse through the semiconductor structure inducing layer intermixing, eg in the Quantum Well (QW) structure.

[0008] IFVD has been reported in “Quantitative Model for the Kinetics of Compositional Intermixing in GaAs—AlGaAs Quantum Well Intermixing (QWI)—Confined Heterostructures”, by Helmy et al, IEEE Journal of Selected Topics in Quantum Well Intermixing (QWI) Electronics, Vol 4, No 4, July/August 1998, pp 653-660, the content of which is incorporated herein by reference.

[0009] Reported QWI, and particularly IFVD methods, suffer from a number of disadvantages, eg the temperature at which Gallium Arsenide (GaAs) out diffuses from the semiconductor material to the silica (SiO2) film.

[0010] It is an object of at least one aspect of the present invention to obviate or at least mitigate at least one of the aforementioned disadvantages/problems in the prior art.

[0011] It is also an object of at least one aspect of the present invention to provide an improved method of manufacturing an optical device using an improved QWI process.

SUMMARY OF INVENTION

[0012] According to a first aspect of the present invention, there is provided a method of manufacturing an optical device, a device body portion from which the device is to be made including a Quantum Well Intermixing (QWI) structure, the method including the step of:

[0013] depositing a dielectric layer on at least part of a surface of the device body portion so as to introduce structural defects at least into a portion of the device body portion adjacent the dielectric layer.

[0014] The structural defects may include “point” defects.

[0015] Preferably, and advantageously, the dielectric layer is deposited by sputtering.

[0016] In a preferred embodiment the dielectric layer is deposited by sputtering using a diode sputterer.

[0017] The dielectric layer may beneficially substantially comprise silica (SiO2); or may comprise another dielectric material such as Aluminium Oxide (Al2O3).

[0018] Preferably, the sputterer includes a chamber which may be substantially filled with an inert gas such as Argon, preferably at a pressure of around 2 μm of Hg, or a mixture of Argon and Oxygen, eg in the proportion 90%/10%.

[0019] The step of depositing the dielectric layer may comprise part of a Quantum Well Intermixing (QWI) process used in manufacture of the device.

[0020] The QWI process may comprise Impurity-Free Vacancy Disordering (IFVD).

[0021] Preferably, the method of manufacture also includes the subsequent step of annealing the device body portion including the dielectric layer at an elevated temperature.

[0022] It has been surprisingly found that by depositing the dielectric layer used in QWI techniques such as IFVD by sputtering, damage induced point defects are introduced into the portion of the device body portion adjacent the dielectric cap; the portion may, for example, comprise a top or “capping” layer. It is believed that the damage arises due to breakage of bonds in the capping layer before annealing, eg the application of thermal energy by rapid thermal annealing, thereby expediting transfer of Gallium Arsenide (GaAs) from the capping layer into the dielectric layer.

[0023] Preferably the method of manufacture also includes the preceding steps of:

[0024] providing a substrate;

[0025] growing on the substrate:

[0026] a first optical cladding layer;

[0027] a core guiding layer including a Quantum Well

[0028] Intermixing (QWI) structure; and

[0029] a second optical cladding layer.

[0030] The first optical cladding layer, core guiding layer, and second optical cladding layer may be grown by Molecular Beam Epitaxy (MBE) or Metal Organic Chemical Vapour Deposition (MOCVD).

[0031] In a first embodiment the method may also include the step of defining a pattern in photoresist on a surface of the device body portion, depositing the dielectric layer and lifting off the photoresist so as to provide the dielectric layer on the said at least part of the surface of the device body portion.

[0032] In said first embodiment, the method may also include the step of depositing a further dielectric layer on the surface of the device body and on a surface of the dielectric layer prior to annealing, preferably by a technique other than sputtering, eg Plasma Enhanced Chemical Vapour Deposition (PECVD).

[0033] In a second embodiment the method may include the steps of depositing the further dielectric layer and then depositing the dielectric layer.

[0034] In said first and second embodiments, the dielectric layer may comprise an intermixing cap; the further dielectric layer may comprise an intermixing suppressing cap.

[0035] The thickness of the dielectric layer may be around 10 to a few hundred nm.

[0036] The annealing step may occur at a temperature of around 700° C. to 1000° C. for around 0.5 to 5 minutes, and in one embodiment at substantially 800° C. for around 1 minute.

[0037] According to a second aspect of the present invention there is provided a method of manufacturing an optical device, a device body portion from which the device is to be made including a Quantum Well Intermixing (QWI) structure, the method including the step of:

[0038] depositing a dielectric layer on at least part of a surface of the device body portion by sputtering.

[0039] According to a third aspect of the present invention there is provided an optical device fabricated from a method according to either of the first or second aspects of the present invention.

[0040] The optical device may be an integrated optical device or an optoelectronic device.

[0041] The device body portion may be fabricated in a III-V semiconductor materials system.

[0042] In one embodiment the III-V semiconductor materials system may be a Gallium Arsenide (GaAs) Arsenide (GaAs) based system, and may therefore operate at a wavelength(s) of substantially between 600 and 1300 nm. Alternatively, in a preferred embodiment the III-V semiconductor materials system may be an Indium Phosphide based system, and may therefore operate at a wavelength(s) of substantially between 1200 and 1700 nm. The device body portion may be made at least partly from Aluminium Gallium Arsenide (GaAs) Arsenide (AlGaAs), Indium Gallium Arsenide (GaAs) Arsenide (InGaAs), Indium Gallium Arsenide (GaAs) Arsenide Phosphide, (InGaAsP), Indium Gallium Arsenide (GaAs), Aluminium Arsenide (InGaAlAs) and/or Indium Gallium Arsenide (GaAs) Aluminium Phosphide (InGaAlP).

[0043] The device body portion may comprise a substrate upon which are provided a first optical cladding layer, a core guiding layer, and a second optical cladding layer.

[0044] Preferably the Quantum Well Intermixing (QWI) structure is provided within the core guiding layer.

[0045] The core guiding layer, as grown, may have a smaller band-gap and higher refractive index than the first and second optical cladding layers.

[0046] According to a fourth aspect of the present invention, there is provided an optical integrated circuit, optoelectronic integrated circuit (OEIC), or photonic integrated circuit (PIC) including at least one optical device according to the third aspect of the present invention.

[0047] According to a fifth aspect of the present invention, there is provided a device body portion (“sample”) when used in a method according to either the first or the second aspects of the present invention.

[0048] According to a sixth aspect of the present invention, there is provided a wafer of material including at least one device body portion when used in a method according to either of the first or second aspects of the present invention.

[0049] According to a seventh aspect of the present invention, there is provided a sputtering apparatus when used in a method according to the second aspect of the present invention.

[0050] Preferably the sputtering apparatus is a diode sputterer.

[0051] According to an eighth aspect of the present invention, there is provided use of a sputtering apparatus in a method according to either of the first or second aspects of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0052] An embodiment of the present invention will now be described, by way of example only, and with reference to the accompanying drawings, which are:

[0053]
FIG. 1 a side view of a device body portion, as grown, for use in a method of manufacture of an optical device according to an embodiment of the present invention;

[0054]
FIG. 2 a side view of an optical device according to an embodiment of the present invention manufactured from the device body portion of FIG. 1;

[0055]
FIG. 3 a schematic view of band-gap energies of a part of the device body portion of FIG. 1 the part comprising a core layer including a Quantum Well Intermixing (QWI) therein;

[0056]
FIG. 4 a schematic view similar to FIG. 3 of band-gap energies of a corresponding part of the optical device of FIG. 2 when Quantum Well Intermixing (QWI);

[0057] FIGS. 5(a) to (f) a series of schematic side views of a device body portion during various steps of a method of manufacture of the optical device of FIG. 2;

[0058]
FIG. 6 a schematic representation of a diode sputterer apparatus for use in deposition of a dielectric layer on the device body portion of FIGS. 5(a) to (f) during a dielectric layer deposition step shown in FIG. 5(c); and

[0059] FIGS. 7(a) and (b) more detailed schematic side views of the device body portion of FIGS. 5(a) to (f) before and after an annealing step shown in FIG. 5(f).

DETAILED DESCRIPTION OF DRAWINGS

[0060] Referring initially to FIG. 1, there is shown a device body portion, generally designated 5, as grown, for use in a method of manufacture of an optical device according to a first embodiment of the present invention. The optical device is an integrated optical device or an optoelectronic device.

[0061] The device body portion 5 is suitably fabricated in a III-V semiconductor material system such as Gallium Arsenide (GaAs) Arsenide (GaAs), and therefore operates at a wavelength(s) of substantially between 600 and 1300 nm, or alternatively, and beneficially, Indium Phosphide (InP), and therefore operate at a wavelength(s) of substantially between 1200 and 1700 nm. The device body portion 5 may be made at least partly from Aluminium Gallium Arsenide (GaAs) Arsenide (AlGaAs), Indium Gallium Arsenide (GaAs) Arsenide (InGaAs), Indium Gallium Arsenide (GaAs) Arsenide Phosphide (InGaAsP), Indium Aluminium Gallium Arsenide (GaAs) Arsenide (InGaAlsAs) and/or Indium Gallium Arsenide (GaAs) Aluminium Phosphide (InGaAlP) In this described first embodiment, the device body portion is made from AlGaAs.

[0062] The device body portion 5 may form part of a semiconductor wafer (see FIG. 6) together with a plurality of other possibly like optical devices which may be cleaved from the wafer after processing. The device body portion 5 comprises substrate 10 upon which is provided a first optical cladding layer 15, a core guiding layer 20, and a second optical cladding layer 25. A Quantum Well Intermixing (QWI) structure 30, including at least one Quantum Well Intermixing (QWI) is provided within the core guiding layer 20, as grown. On the second optical cladding layer 30 there is provided a capping layer 35.

[0063] As will be appreciated, the core guiding layer 20, as grown, has a smaller band-gap and higher refractive index than the first and second optical cladding layer 15,25.

[0064] Referring now to FIG. 2, there is shown an optical device, generally designated 40, manufactured from the device body portion 5 of FIG. 1, by a method which will be described in detail hereinafter. As can be seen from FIG. 2, the device 40 comprises an active region 45 and a passive region 50. In this embodiment the active region 45 comprises a Quantum Well Intermixing (QWI) Well (QUANTUM WELL (QW) amplifier. However, it should be understood that the active region 45 may in other embodiments, comprise a laser, modulator switch, detector or like active (electrically controlled) optical device. Further, the passive region 50 comprises a low-loss waveguide wherein the Quantum Well Intermixing (QWI) Well structure 30 has been at least partially removed by a Quantum Well Intermixing (QWI) Well Intermixing (QWI) technique, as will hereinafter be described in greater detail.

[0065] The device 40 has excellent alignment between the core layer 20 waveguiding regions of the active region 45 and passive region 50, and has a reflection coefficient between the active region 45 and passive region 50 which is substantially negligible (of the order of 10−6). Further, mode matching between the active region 45 and the passive region 50 is intrinsic to the device 40.

[0066] Typically, the substrate 10 is n-type doped to a first concentration, while the first cladding layer 15 is n-type doped to a second concentration. Further, the core layer 20 is typically substantially intrinsic, while the second cladding layer 25 is typically p-type doped to a third concentration. Further, the cap layer (or contact layer) 35 is p-type doped to a fourth concentration. It will be appreciated by those skilled in the art, that the cap layer 35 and second cladding layer 25 may be etched into a ridge (not shown), the ridge acting as an optical waveguide to confine optical modes within the core layer 20, both within the optically active region 45 and the optically passive region 50. Further, contact metallisations (not shown) may be formed on at least a portion of the top surface of the ridge within the optically active region 45, and also on an opposing surface of the substrate 10, as is known in the art.

[0067] It will further be appreciated that the device 40 may comprise part of an optical integrated circuit, optoelectronic integrated circuit (OEIC), or photonic integrated circuit (PIC) which may comprise one or more of such optical devices 40.

[0068] Referring now to FIG. 3, there is shown a schematic representation of the band-gap energies of a Quantum Well Intermixing (QWI) Well 31 of the Quantum Well Intermixing (QWI) Well structure 30 within the core layer 20 of the device body portion 5, as grown. As can be seen from FIG. 3, the AlGaAs core layer 20 includes at least one Quantum Well Intermixing (QWI) 31, with the Quantum Well Intermixing (QWI) structure 30 having a lower Aluminium content than the surrounding core layer 20, such that the band-gap energy of the Quantum Well Intermixing (QWI) structure 30 is less than that of the surrounding AlGaAs core layer 20. The Quantum Well Intermixing (QWI) structure 30 is typically around 3 to 20 nm thick, and more typically around 10 nm in thickness.

[0069] Referring now to FIG. 4, there is shown a corresponding portion 32 of the core layer 20 as in FIG. 3, but which has been Quantum Well Intermixing (QWI) so as to effectively increase the band-gap energy (meV) of the part 32 which corresponds to the Quantum Well Intermixing (QWI) 31 of the Quantum Well Intermixing (QWI) structure 30. Quantum Well Intermixing (QWI) Well Intermixing (QWI) therefore essentially “washes out” the Quantum Intermixing (QWI) structure 30 from the core layer 20. The portion shown in FIG. 4 relates to the passive region 50 of the device 40. As will be understood, optical radiation transmitted from or generated within the optically active region 45 of device 40 will be transmitted through the low loss waveguide provided by the Quantum Well Intermixing (QWI) region 32 of the core layer 20 of the passive region 50.

[0070] Referring now to FIGS. 5(a) to (f), there is illustrated a first embodiment of a method of manufacturing an optical device 40 from a device body portion 5, including a Quantum Well Intermixing (QWI) structure 30 according to the present invention, the method including the steps (see FIGS. 5(b) to (d)) of depositing a dielectric layer 51 on at least part of a surface 52 of the device body portion 5 so as to introduce point defects into a portion 53 of the device body portion 5 adjacent the dielectric layer 51.

[0071] The method of manufacture begins with the step of:

[0072] providing substrate 10, growing on the substrate 10 first optical cladding layer 15, core guiding layer 20 including at least one Quantum Well Intermixing (QWI) 30, second optical cladding layer 25, and cap layer 35.

[0073] The first optical cladding layer 15, core guiding layer 20, second optical cladding layer 25, and cap layer 35 may be grown by known semiconductor epitaxial growth techniques such as Molecular Beam Epitaxy (MBE) Epitaxy (MBE) or Metal Organic Chemical Vapour Deposition (MOCVD). Once the device body 5 has been grown—normally as part of a wafer (not shown) including a plurality of such device body portions 5—a pattern may be defined in Photo-Resist (PR) 55 on surface 52 of the device body portion 5. The dielectric layer 51 is deposited on the surface 52, and the Photo-Resist 55 lifted off so as to leave the dielectric layer 51 on the said at least part of the surface 52 of the device body portion 5. As can be seen from FIGS. 5(c) and 5(d), the dielectric layer 51 deposited on at least part of the surface 52 of device body portion 5 causes localised damage in region 53 of the cap layer 35, and introduces point defects into the cap layer 35.

[0074] Referring briefly to FIG. 6, the dielectric layer 51 is deposited by sputtering, and in this embodiment the dielectric layer 51 is deposited by sputtering using a diode sputterer apparatus, generally designated 65. The dielectric layer 51 substantially comprises Silica (SiO2), but may in an a modification comprise another dielectric material such as Aluminium Oxide (Al2O3). As can be seen from FIG. 6, the sputterer apparatus 65 includes a chamber 70 which in use is substantially filled with an inert gas such as Argon which is preferably provided within the chamber 70 at a pressure of around 2 μm of Hg. The sputterer 65 also comprises an RF source 75 connected to a cathode 80 of the diode sputterer 65. A Silica target 81 is provided on the cathode 80, while the device body portion 5 (on wafer 82) is provided on the anode 85 of the diode sputterer 65. In use, as can be seen from FIG. 6, an Argon plasma 86 is generated between the cathode 80 and anode 85 with first and second dark spaces 90,95 being provided between the Silica target 81 and the Argon Plasma 86 and between the Argon Plasma and the device body portion 5, respectively.

[0075] The step of depositing the dielectric layer 51 comprises part of a Quantum Well Intermixing (QWI) process used in the manufacture of the device 40, the QWI process comprising—in a preferred embodiment—an Impurity-Free Vacancy Disordering (IFVD) technique. It has been surprisingly found that by depositing the dielectric layer 51 used in QWI techniques such as IFVD by sputtering using the sputterer 65, damage induced defects are introduced into the portion 53 of the device body portion 5 adjacent dielectric cap 51; the portion 53 in this case comprising part of the cap layer 35. It is believed that the damage breaks bonds in the cap layer 35 prior to annealing (which will hereinafter be described), eg the application of thermal energy by rapid thermal annealing, thereby expediting the transfer of Gallium Arsenide (GaAs) from the cap layer 35 into the dielectric layer 51.

[0076] The dielectric layer 51 is typically between 10 to 1000 nm, and typically 300 nm in thickness. The method of manufacture includes a further step as shown in FIG. 5(e) of depositing further dielectric layer 60 on the surface 52 of device body 5 and on a surface of the dielectric layer 51 prior to annealing. The further dielectric layer 60 is deposited by a technique other than diode sputtering, and preferably by a technique other than sputtering per se, eg Plasma Enhanced Chemical Vapour Deposition (PECVD).

[0077] The dielectric layer 51 therefore comprises an intermix cap layer, while the further dielectric layer 60 comprises an intermix suppressing cap layer. The intermix suppressing cap layer is used to protect the surface 52 from Arsenic desorption. The method will work without the intermix suppressing cap layer however; the quality of the surface 52 may not be so good.

[0078] As shown in FIG. 5(f), subsequent to deposition of the further dielectric layer 60, the device body portions including the dielectric layer 51 and further dielectric layer 60 are annealed at an elevated temperature. The annealing stage comprises a rapid thermal annealing stage, the annealing temperature being around 70020 C. to 1000° C. for around 0.5 to 5 minutes, and in one implementation, at substantially 800° C. for substantially 1 minute.

[0079] The action of the annealing step of FIG. 5f) is illustrated diagrammatically in FIGS. 7(a) and (b). As can be seen from FIGS. 7(a) and (b), the annealing step causes “out diffusion” of Gallium Arsenide (GaAs) from the cap layer 35 to the intermixing cap, ie dielectric layer 51. However, portions of the cap layer 35 below the suppressing cap, ie further dielectric layer 60, are not subject to Gallium Arsenide (GaAs) “out-diffusion”. The portions of the cap layer 35 which lie within an area of the intermixing cap, ie dielectric cap 51, are subject to out-diffusion of Gallium Arsenide (GaAs) as shown in FIG. 7(b). The out-diffusion of Gallium Arsenide (GaAs) leaves vacancies behind which vacancies migrate from the cap layer 35, through the second cladding layer 25, and into the core layer 20, and hence to the Quantum Well Intermixing (QWI) structure(s) 30, thereby changing the effective band-gap of the Quantum Well Intermixing (QWI) structure 30, and effectively washing-out the Quantum Well Intermixing (QWI) of the Quantum Well Intermixing (QWI) structure 30 below the intermixing cap layer.

[0080] It will be appreciated that the intermixing cap, ie dielectric layer 51, is provided within the area of the passive region 50 to be formed in device 40, while the suppressing cap, ie further dielectric layer 60, is provided on the device body portion 5 in areas such as the optically active region 45 to be formed on the device 5, which areas are not to be Quantum Well Intermixing (QWI).

[0081] Once the device body portion 5 has been processed to the stage of FIG. 5(f), and annealed, the dielectric layer 51 and further dielectric layer 60 may be removed by conventional methods, eg wet or dry etching.

EXAMPLE

[0082] There now follows an example which illustrates a typical band-gap shift which can be obtained using IFVD in a method of manufacturing an optoelectronic device according to the present invention in a long wavelength aluminium alloy such as Indium Aluminium Gallium Arsenide (GaAs) Arsenide, (InAlGaAs), grown on an Indium Phosphide (InP) substrate.

[0083] The dielectric layer 51 deposition requires a sputter chamber 70 configured in a diode configuration with a cathode/anode (plate) separation of the order to 100 mm. The cathode 80 and anode 85 are each configured as substantially four inch circular plates. The gas used in this example for sputter deposition is typically Argon, but other suitable inert gases may be used, and also small amounts of Oxygen may be added to the Argon Plasma 86, eg approximately 10% by volume, to improve the stoichiometry of the deposited dielectric layer 51. The dielectric material used in the method is typically Silica (SiO2), but other dielectric materials such as Aluminium Oxide (Al2O3) can be used. It has been found that a preferred pressure in the chamber 70 for the method is around 2 μm of Hg. For power values shown in Table 1 below, a two minute deposition was carried out of the dielectric layer 45 on to a semiconductor wafer, including at least one device body portion 5. The resultant dielectric film thickness was from 10 to a few hundred nm. The band-gap shift figures in Table 1 illustrate the band-gap shift in the Quantum Well (QW) structure 30 for an anneal at a temperature of 800° C. for a time of 1 minute.

1TABLE 1Deposition ConditionsBand-Gap Shift (nm)PECVD (SiO2)1300 watts sputtered (SiO2)12500 watts sputtered (SiO2)21700 watts sputtered (SiO2)38

[0084] as a better intermix cap than non-sputtered silica (SiO2), and also illustrates that the effectiveness of the sputtered silica (SiO2) cap increases with increasing sputtering power.

[0085] In a second embodiment of a method of manufacturing an optical device 40 according to the present invention, to process a wafer to produce more than one band-gap a film of PECVD SiO2 is deposited on to the wafer to provide further dielectric layer 60. Photolithography techniques are then used to delineate a pattern on top of the PECVD SiO2. Either wet or dry etching can then be used to transfer the pattern into the PECVD (SiO2).

[0086] Patterned photoresist (PR) is then left on top of the patterned PECVD (SiO2), and the sample/wafer is then placed into the sputtering apparatus 65 for deposition of the dielectric layer 51. After deposition the sample is immersed in acetone and the sputtered SiO2 on the photoresist is removed in a “lift-off” process.

[0087] A rapid thermal anneal is now performed at a suitable temperature (700-1000° C.) for the required period of time (0.5-5 min). This enables the point defects generated at the surface 52 to propagate through the device body portion 5 and cause interdiffusion of the elements.

[0088] It will be appreciated that the embodiment of the invention hereinbefore described are given by way of example only, and are not meant to limit the scope thereof in any way.

[0089] It should be particularly understood that the damage induced in the semiconductor device body portion 5 adjacent to the sputtered dielectric layer 57 is believed to arise from radiation in the form of secondary electrons, soft x-rays and/or also from bombardment of ions. The damage to the surface 50 of the semiconductor device body portion 5 or wafer 82, can be introduced by various means in the sputtering apparatus 65, an effective method being to use a diode configuration in the deposition chamber 70. Using the diode configuration has been unexpectedly found to permit more radiation damage to the device body portion 5 (or “sample”) than in the more usual magnetron machine arrangement wherein magnets create a high local field which it is believed stop particles travelling from the dielectric target 81 to the device body portion 5 provided on the wafer 82 of semiconductor material.

[0090] It will further be appreciated that an optical device according to the present invention may include a waveguide such as a ridge or buried heterostructure or indeed any other suitable waveguide.

[0091] It will also be appreciated that the Quantum Well Intermixing (QWI) regions may comprise optically active device(s).

[0092] Further, it will be appreciated that sequential processing including using several RF powers may be used to provide a device with several different QWI band-gaps.

Claims

1. A method of manufacturing an optical device, a device body portion from which the device is to be made including a Quantum Well Intermixing (QWI) structure, the method including the step of: depositing a dielectric layer on at least part of a surface of the device body portion so as to introduce structural defects at least into a portion of the device body portion adjacent the dielectric layer.
2. A method of manufacturing an optical device as claimed in claim 1, wherein the structural defects substantially comprise point defects.
3. A method of manufacturing an optical device as claimed in claim 1, wherein the dielectric layer is deposited by sputtering.
4. A method of manufacturing an optical device as claimed in claim 1, wherein the dielectric layer is deposited by sputtering using a diode sputterer.
5. A method of manufacturing an optical device as claimed in claim 1, wherein the dielectric layer is selected from Silica (SiO2) and Aluminium Oxide (Al2O3).
6. A method of manufacturing an optical device as claimed in claim 4, wherein the sputterer includes a chamber which is substantially filled with an inert gas.
7. A method of manufacturing an optical device as claimed in claim 6, wherein the inert gas is selected from Argon and a mixture of Argon and Oxygen.
8. A method of manufacturing an optical device as claimed in claim 1, wherein the step of depositing the dielectric layer comprises part of a Quantum Well Intermixing (QWI) Well Intermixing (QWI) process used in manufacture of the device.
9. A method of manufacturing an optical device as claimed in claim 8, wherein the QWI process comprises Impurity-Free Vacancy Disordering (IFVD).
10. A method of manufacturing an optical device as claimed in claim 8, wherein the method of manufacture also includes the subsequent step of annealing the device body portion including the dielectric layer at an elevated temperature.
11. A method of manufacturing an optical device as claimed in claim 1, wherein the method of manufacture also includes th e preceding steps of: providing a substrate; growing on the substrate: a first optical cladding layer; a core guiding layer including a Quantum Well Intermixing (QWI) Well structure; and a second optical cladding layer.
12. A method of manufacturing an optical device as claimed in claim 11, wherein the first optical cladding layer, core guiding layer, and second optical cladding layer are grown by a growth technique selected from: Molecular Beam Epitaxy (MBE) Epitaxy (MBE) and Metal Organic Chemical Vapour Deposition (MOCVD).
13. A method of manufacturing an optical device as claimed in claim 1, wherein the method also includes the step of defining a pattern in photoresist on a surface of the device body portion, depositing the dielectric layer and lifting off the photoresist so as to provide the dielectric layer on the said at least part of the surface of the device body portion.
14. A method of manufacturing an optical device as claimed in claim 13, wherein the method also includes the step of depositing a further dielectric layer on the surface of the device body and on a surface of the dielectric layer prior to annealing, the further dielectric layer being deposited by a technique other than sputtering.
15. A method of manufacturing an optical device as claimed in claim 14, wherein the other technique comprises Plasma Enhanced Chemical Vapour Deposition (PECVD).
16. A method of manufacturing an optical device as claimed in claim 1, wherein the method includes the steps of depositing a further dielectric layer and then depositing the dielectric layer.
17. A method of manufacturing an optical device as claimed in claim 13, wherein the dielectric layer comprises an intermixing cap and further dielectric layer comprises an intermixing suppressing cap.
18. A method of manufacturing an optical device as claimed in claim 1, wherein the thickness of the dielectric layer is around 10 to a few hundred nm.
19. A method of manufacturing an optical device as claimed in claim 10, wherein the annealing step occurs at a temperature of around 700° C. to 1000° C. for around 0.5 to 5 minutes.
20. A method of manufacturing an optical device, a device body portion from which the device is to be made including a Quantum Well Intermixing (QWI) Well (QUANTUM WELL (QW) structure, the method including the step of: depositing a dielectric layer on at least part of a surface of the device body portion by sputtering.
21. An optical device fabricated from a method according to either of claim 1 or 20.
22. An optical device as claimed in claim 21, wherein the optical device is selected from an integrated optical device and an optoelectronic device.
23. An optical device as claimed in claim 21, wherein the device body portion is fabricated in a III-V semiconductor materials system.
24. An optical device as claimed in claim 21, wherein the III-V semiconductor materials system is a Gallium Arsenide (GaAs) Arsenide (GaAs) based system and the device operates at a wavelength(s) of substantially between 600 and 1300 nm.
25. An optical device as claimed in claim 21, wherein the III-V semiconductor materials system is an Indium Phosphide based system and the device operates at a wavelength(s) of substantially between 1200 and 1700 nm.
26. An optical device as is claimed in claim 23, wherein the device body portion is made at least partly from Aluminium Gallium Arsenide (GaAs) Arsenide (AlGaAs), Indium Gallium Arsenide (GaAs) Arsenide (InGaAs), Indium Gallium Arsenide (GaAs) Arsenide Phosphide, (InGaAsP), Indium Gallium Arsenide (GaAs) Aluminium Arsenide (InGaAlAs) and/or Indium Gallium Arsenide (GaAs) Aluminium Phosphide (InGaAlP).
27. An optical device as claimed in claim 21, wherein the device body portion comprises a substrate upon which are provided a first optical cladding layer, a core guiding layer, and a second optical cladding layer.
28. An optical device as claimed in claim 27, wherein the Quantum Well Intermixing (QWI) Well (QUANTUM WELL (QW) structure is provided within the core guiding layer.
29. An optical device as claimed in claim 27, wherein the core guiding layer, as grown, has a smaller band-gap and higher refractive index than the first and second optical cladding layers.
30. An optical integrated circuit, optoelectronic integrated circuit (OEIC), or photonic integrated circuit (PIC) including at least one optical device according to claim 21.
31. A device body portion when used in a method according to either of claim 1 or 20.
32. A wafer of material including at least one device body portion when used in a method according to either of claim 1 or 20.
33. A sputtering apparatus when used in a method according to claim 20.
34. A sputtering apparatus as claimed 33, wherein the sputtering apparatus is a diode sputterer.
35. Use of a sputtering apparatus in a method according to either of claim 4 or 20.

Priority Claims (2)

Number	Date	Country	Kind
GB 01 01 635.1	Jan 2001	GB
01 02 536.0	Feb 2001	GB

Method of manufacturing optical devices and related improvements

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Abstract

Description

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Priority Claims (2)