Patent Grant
9443888
1. Field of the Invention
The present invention relates to a driver circuit including an element that is formed using a metal oxide exhibiting semiconductor characteristics, and to a semiconductor device using the driver circuit. Note that the semiconductor device indicates all the devices that can operate by using semiconductor characteristics, and display devices, semiconductor circuits, and electronic appliances are all included in the category of the semiconductor devices.
2. Description of the Related Art
A wide variety of metal oxides exist and are used for various applications. Indium oxide is a well-known material and is used as a transparent electrode material needed for a liquid crystal display and the like.
Some metal oxides exhibit semiconductor characteristics. Metal oxides exhibiting semiconductor characteristics are a kind of compound semiconductor. The compound semiconductor is a semiconductor obtained by bonding two or more kinds of atoms. In general, metal oxides are insulators; however, it is known that metal oxides become semiconductors depending on the combination of elements included in the metal oxides.
For example, it is known that some metal oxides such as tungsten oxide, tin oxide, indium oxide, and zinc oxide exhibit semiconductor characteristics. References disclose a thin film transistor in which a transparent semiconductor layer including such a metal oxide is used as a channel formation region (Patent Documents 1 to 4, and Non-Patent Document 1).
As metal oxides, multi-component oxides as well as single-component oxides are known. For example, InGaO3(ZnO)m (m is a natural number) belonging to homologous series is a known material (Non-Patent Documents 2 to 4).
In addition, it has been confirmed that such an In—Ga—Zn-based oxide can be used for a channel formation region of a thin film transistor (Patent Document 5, and Non-Patent Documents 5 and 6).
Application of a thin film transistor using a metal oxide exhibiting semiconductor characteristics (hereinafter, also referred to as an oxide semiconductor) to an active matrix display device (such as a liquid crystal display, an electroluminescence display, or electronic paper) has been taken into consideration. An active matrix display device includes several hundreds of thousands to several millions of pixels arranged in a matrix and a driver circuit for inputting pulse signals to the pixels.
In an active matrix display device, a thin film transistor is provided in each pixel and serves as a switching element for switching on or off when a pulse signal is input from a driver circuit, so that images can be displayed. The thin film transistor is also used as an element forming a driver circuit.
A driver circuit for driving a pixel portion includes elements such as a thin film transistor, a capacitor, and a resistor.
An object of one embodiment of the present invention is to provide a driver circuit including an active element and a passive element that are manufactured using an oxide semiconductor, and a semiconductor device including the driver circuit.
One embodiment of the present invention includes an enhancement-mode thin film transistor and a resistor. The thin film transistor and the resistor are formed using an oxide semiconductor layer. In addition, the concentration of hydrogen in the oxide semiconductor layer used for the thin film transistor is made lower than that in the oxide semiconductor layer used for the resistor. Accordingly, the oxide semiconductor layer used for the resistor has a lower resistance than the oxide semiconductor layer used for the thin film transistor.
One embodiment of the present invention includes a thin film transistor and a resistor that are formed using an oxide semiconductor layer. A silicon nitride layer formed by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3) is formed on and in direct contact with the oxide semiconductor layer used for the resistor, and the silicon nitride layer is formed over the oxide semiconductor layer used for the thin film transistor with a silicon oxide layer serving as a barrier layer interposed therebetween. Therefore, a higher concentration of hydrogen is introduced into the oxide semiconductor layer used for the resistor than into the oxide semiconductor layer used for the thin film transistor. As a result, the oxide semiconductor layer used for the resistor has a lower resistance than the oxide semiconductor layer used for the thin film transistor.
That is, one embodiment of the present invention is a driver circuit including a resistor in which a first oxide semiconductor layer is used for a resistor element, a thin film transistor in which a second oxide semiconductor layer having a lower concentration of hydrogen than the first oxide semiconductor layer is used for a channel formation region, a silicon oxide layer provided over the second oxide semiconductor layer, and a silicon nitride layer provided over the first oxide semiconductor layer and the silicon oxide layer.
According to one embodiment of the present invention, an oxide semiconductor layer having a low resistance may be provided between the oxide semiconductor layers that are used for the resistor element of the resistor and the channel formation region of the thin film transistor, and a wiring that is a conductor.
That is, according to one embodiment of the present invention, the driver circuit having the aforementioned structure includes a third oxide semiconductor layer in contact with one terminal or the other terminal of the resistor and the first oxide semiconductor layer; a fourth oxide semiconductor layer in contact with a first terminal of the thin film transistor and the second oxide semiconductor layer; and a fifth oxide semiconductor layer in contact with a second terminal of the thin film transistor and the second oxide semiconductor layer. The resistance of each of the third oxide semiconductor layer to the fifth oxide semiconductor layer is lower than that of the second oxide semiconductor layer.
In addition, a driver circuit of one embodiment of the present invention includes a resistor and a thin film transistor that are formed using an oxide semiconductor layer containing a high concentration of nitrogen. Furthermore, a silicon oxide layer serving as a barrier layer is provided over the thin film transistor. At this time, heat treatment is performed at 200° C. to 600° C., typically 250° C. to 500° C. in an atmosphere containing a substance which is a supply source of a hydrogen atom. Nitrogen in the oxide semiconductor layer has the effect of preventing atoms forming the oxide semiconductor layer from tightly filling the film, and of promoting diffusion and solid dissolution of hydrogen in the film. Accordingly, the heat treatment allows a higher concentration of hydrogen to be introduced into the oxide semiconductor layer used for the resistor and containing a high concentration of nitrogen than into the oxide semiconductor layer used for the thin film transistor. As a result, the resistance of the oxide semiconductor layer used for the resistor and containing a high concentration of nitrogen is lower than that of the oxide semiconductor layer used for the thin film transistor and containing a high concentration of nitrogen.
That is, the driver circuit of one embodiment of the present invention includes a resistor in which a first oxide semiconductor layer containing a high concentration of nitrogen is used for a resistor element, and a thin film transistor in which a second oxide semiconductor layer containing a high concentration of nitrogen and a lower concentration of hydrogen than the first oxide semiconductor layer is used for a channel formation region.
Note that the oxide semiconductor layer containing a high concentration of nitrogen refers to an oxide semiconductor layer with a ratio of nitrogen (N) to oxygen (O) (N/O) of 0.05 to 0.8, preferably 0.1 to 0.5.
Furthermore, according to one embodiment of the present invention, a silicon nitride layer formed by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3) is provided on and in direct contact with the oxide semiconductor layer used for the resistor and containing a high concentration of nitrogen.
That is, according to one embodiment of the present invention, the driver circuit having the aforementioned structure includes a silicon oxide layer provided over the second oxide semiconductor layer, and a silicon nitride layer provided over the first oxide semiconductor layer and the silicon oxide layer.
In this document (specification, claims, drawings, and the like), the word “film” means something formed on the entire surface of a substrate to be processed into a desired shape in a subsequent photolithography step or the like, and something before the processing. The word “layer” means something obtained by processing and shaping a “film” into a desired shape by a photolithography step or the like, or something that is to be formed on the entire surface of a substrate.
Also in this document (specification, claims, drawings, and the like), the phrase “A and B are connected” means that A and B are electrically connected, as well as that A and B are directly connected. Here, the phrase “A and B are electrically connected” shows that, when an electrically acting object exists between A and B, A and B are at substantially the same potential through the object.
Specifically, the phrase “A and B are connected” means the case where A and B can be regarded to be at the same node in consideration of the circuit operation, such as the case where A and B are connected through a switching element such as a transistor and have substantially the same potential through the conduction of the switching element, and the case where A and B are connected through a resistor and a potential difference between the two ends of the resistor does not affect the operation of a circuit including A and B.
Note that it is difficult to determine which one of the terminals of a thin film transistor is a source terminal or a drain terminal because it changes depending on the structure, operating conditions, and the like of the thin film transistor. Therefore, in this document (specification, claims, drawings, and the like), one of a source terminal and a drain terminal is referred to as a first terminal and the other thereof is referred to as a second terminal for distinction.
According to one embodiment of the present invention, the concentration of hydrogen in an oxide semiconductor layer used for a resistor element of a resistor can be made higher than that in an oxide semiconductor layer used for a channel formation region of a thin film transistor. Therefore, the resistance of an oxide semiconductor layer can be selectively lowered. Accordingly, a thin film transistor and a resistor do not need to be manufactured in different steps, which makes it possible to provide a driver circuit manufactured in a smaller number of steps and a semiconductor device including the driver circuit.
In the accompanying drawings:
Embodiments of the disclosed invention will be described below with reference to drawings. Note that the disclosed invention is not limited to the following embodiments, and it is apparent to those skilled in the art that modes and details can be modified in a wide variety of ways without departing from the spirit and scope of the disclosed invention. Accordingly, the disclosed invention should not be construed as being limited to the description of the embodiments given below. Note that in the embodiments shown below, like portions are denoted by like reference numerals in different drawings in some cases.
In this embodiment, an example of a display device including a driver circuit manufactured using an oxide semiconductor will be described with reference to
Note that a display device refers to a device including a display element such as a light-emitting element or a liquid crystal element. The display device may include a peripheral driver circuit for driving a plurality of pixels. The peripheral driver circuit for driving a plurality of pixels is formed over the same substrate as the plurality of pixels. The display device may include a flexible printed circuit (FPC). Furthermore, the display device may include a printed wiring board (PWB) which is connected to the display device through a flexible printed circuit (FPC) or the like and to which an IC chip, a resistor, a capacitor, an inductor, a transistor, and the like are attached. The display device may further include an optical sheet such as a polarizing plate or a retardation plate, a lighting device, a housing, an audio input/output device, an optical sensor, and the like.
The source line driver circuit and the gate line driver circuit for driving the pixel portion have a logic circuit such as an inverter circuit formed with a thin film transistor, a capacitor, a resistor, and the like. As an inverter circuit formed with a unipolar thin film transistor, there are a circuit formed by a combination of an enhancement-mode thin film transistor and a depletion-mode thin film transistor (hereinafter, referred to as an EDMOS circuit), a circuit formed by a combination of enhancement-mode thin film transistors (hereinafter, referred to as an EEMOS circuit), and an ERMOS circuit. Note that an n-channel thin film transistor with a positive threshold voltage is defined as an enhancement-mode transistor while an n-channel thin film transistor with a negative threshold voltage is defined as a depletion-mode transistor, and these definitions apply to this specification.
When an enhancement-mode transistor with a positive threshold voltage is used as a thin film transistor provided in the pixel portion, a current flowing due to a voltage applied between a gate terminal and a source terminal can be made lower than that in the case of using a depletion-mode transistor, resulting in lower power consumption. It is preferable that an enhancement-mode thin film transistor be also used as a thin film transistor in the driver circuit for driving the pixel portion as well as in the pixel portion. By using an enhancement-mode thin film transistor as a thin film transistor of an inverter circuit, the pixel portion and the driver circuit can be manufactured with one kind of transistor, which makes it possible to reduce the number of manufacturing steps. Note that an enhancement-mode transistor uses an oxide semiconductor and has such electric characteristics as an on/off ratio of 109 or more at a gate voltage of −20 V to 20 V. Accordingly, a small leakage current flows between a source terminal and a drain terminal, which allows low power consumption driving.
Note that in this document (specification, claims, drawings, and the like), a thin film containing a compound represented by InMO3 (ZnO)m (m>0) is formed as an oxide semiconductor and the thin film is used for manufacturing a semiconductor element. Note that M denotes one or more of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co). For example, M is gallium (Ga) in some cases, and in other cases, M contains other metal elements in addition to gallium (Ga), such as gallium (Ga) and nickel (Ni) or gallium (Ga) and iron (Fe). Furthermore, the above oxide semiconductor may contain a transition metal element such as iron (Fe) or nickel (Ni) or an oxide of the transition metal as an impurity element in addition to a metal element contained as M. In addition, the concentration of sodium (Na) contained in the above oxide semiconductor is 5×1018 atoms/cm3 or less, preferably 1×1018 atoms/cm3 or less. In this document (specification, claims, drawings, and the like), this thin film is also referred to as an In—Ga—Zn—O-based non-single-crystal film.
Table 1 shows a typical example of measurement by inductively coupled plasma mass spectrometry (ICP-MS). An oxide semiconductor film of InGa0.94Zn0.40O3.31 is obtained under Condition 1: a target including In2O3, Ga2O3, and ZnO at a molar ratio of 1:1:1 (In:Ga:Zn=1:1:0.5) is used, pressure is 0.4 Pa, direct current (DC) power source is 500 W, the flow rate of argon gas is 10 sccm, and the flow rate of oxygen gas is 5 sccm. Further, an oxide semiconductor film of InGa0.95Zn0.41O3.33 is obtained under Condition 2 that is different from Condition 1 only in the deposition atmosphere in which the flow rate of argon gas is changed to 40 sccm and the flow rate of oxygen gas is changed to 0 sccm.
In addition, the measurement is performed by Rutherford backscattering spectrometry (RBS) instead of ICP-MS, and the quantified results are shown in Table 2.
As the result of measurement of the sample in Condition 1 by RBS, an oxide semiconductor film of InGa0.92Zn0.45O3.86 is obtained. Further, as the result of measurement of the sample in Condition 2 by RBS, an oxide semiconductor film of InGa0.93Zn0.44O3.49 is obtained.
Even when an In—Ga—Zn—O-based non-single-crystal film is deposited by sputtering and then subjected to heat treatment at a temperature of 200° C. to 500° C., typically 300° C. to 400° C. for 10 minutes to 100 minutes, an amorphous structure is observed when its crystal structure is analyzed by X-ray diffraction (XRD). In addition, it is possible to manufacture a thin film transistor having such electric characteristics as an on/off ratio of 109 or more and a mobility of 10 or more at a gate voltage of −20 V to 20 V. A thin film transistor manufactured using an oxide semiconductor layer having such electric characteristics has a higher mobility than a thin film transistor manufactured using amorphous silicon, which allows a driver circuit including a shift register to be driven at high speed.
Next, an example of a circuit diagram of a gate line driver circuit and a source line driver circuit using an ERMOS circuit will be illustrated and described.
First, a structure of a source line driver circuit which uses an ERMOS circuit as an inverter circuit will be described.
Further, in the source line driver circuit in the display device of this embodiment, a sampling pulse which is output from a pulse output circuit of one stage in the shift register drives the sampling switch 206 to sample analog video signals of 12 source signal lines at the same time. Note that another signal for switching a scanning direction, or the like may be additionally input. Although this embodiment shows an example in which clock signals having two phases, such as a first clock signal (CLK1) and a second clock signal (CLK2), are used for driving the driver circuit, another structure may be employed in which signals other than the clock signals having two phases are input to drive the driver circuit.
In the circuit diagram illustrated in
A first terminal of the thin film transistor 351 is connected to a terminal to which a start pulse SP is input, and a gate terminal of the thin film transistor 351 is connected to the wiring 359.
One terminal of the resistor 352 is connected to a wiring to which a high power supply potential VDD is supplied (also referred to as a high potential line).
A first terminal of the thin film transistor 353 is connected to the other terminal of the resistor 352, a gate terminal of the thin film transistor 353 is connected to a second terminal of the thin film transistor 351, and a second terminal of the thin film transistor 353 is connected to a wiring to which a low power supply potential VSS is supplied (also referred to as a low potential line).
One terminal of the resistor 354 is connected to the high potential line.
A first terminal of the thin film transistor 355 is connected to the other terminal of the resistor 354, a gate terminal of the thin film transistor 355 is connected to the other terminal of the resistor 352 and the first terminal of the thin film transistor 353, and a second terminal of the thin film transistor 355 is connected to the low potential line.
A first terminal of the thin film transistor 356 is connected to the other terminal of the resistor 354 and the first terminal of the thin film transistor 355, a gate terminal of the thin film transistor 356 is connected to the wiring 360, and a second terminal of the thin film transistor 356 is connected to the second terminal of the thin film transistor 351 and the gate terminal of the thin film transistor 353.
One terminal of the resistor 357 is connected to the high potential line, and the other terminal thereof is connected to a first terminal of a thin film transistor 351 in the pulse output circuit 332 of the second stage.
A first terminal of the thin film transistor 358 is connected to the other terminal of the resistor 357 and the first terminal of the thin film transistor 351 in the pulse output circuit 332 of the second stage, a gate terminal of the thin film transistor 358 is connected to the other terminal of the resistor 352, the first terminal of the thin film transistor 353, and the gate terminal of the thin film transistor 355, and a second terminal of the thin film transistor 358 is connected to the low potential line.
The pulse output circuit of the second stage has the same structure as that of the first stage except that the connection of the wiring 359 and the connection of the wiring 360 are switched to each other. In the third stage and thereafter, the pulse output circuit 331 of the odd-numbered stage and the pulse output circuit 332 of the even-numbered stage are connected in a manner similar to the pulse output circuit 331 of the first stage and the pulse output circuit 332 of the second stage, respectively.
In
It is preferable that the thin film transistors 351 and 356 be enhancement-mode transistors like the thin film transistors 353, 355, and 358. By using an enhancement-mode transistor as a switch, the off-current of the transistor can be reduced, resulting in lower power consumption and reduction in the number of manufacturing steps.
Here, operation of the circuits illustrated in
In addition, as the nodes in the pulse output circuit of the second stage illustrated in
Operation in a period T1 in
When the first clock signal (CLK1) becomes H level, the thin film transistor 351 in the pulse output circuit of the first stage is turned on.
Then, the voltage at the node A rises to H level due to the start pulse at H level.
When the voltage at the node A rises to H level, the thin film transistor 353 in the pulse output circuit of the first stage is turned on.
Then, the voltage at the node B drops to L level due to the low power supply potential at L level.
When the voltage at the node B drops to L level, the thin film transistor 355 and the thin film transistor 358 in the pulse output circuit of the first stage are turned off.
When the thin film transistor 355 in the pulse output circuit of the first stage is turned off, the voltage at the node C rises to H level due to the high power supply potential at H level. Moreover, when the thin film transistor 358 in the pulse output circuit of the first stage is turned off, the voltage at the node out1 rises to H level due to the high power supply potential at H level.
Note that since the second clock signal (CLK2) is at L level, the thin film transistor 356 in the pulse output circuit of the first stage and the thin film transistor 351 in the pulse output circuit of the second stage are turned off.
Next, operation in a period T2 in
When the first clock signal becomes L level, the thin film transistor 351 in the pulse output circuit of the first stage is turned off. On the other hand, the thin film transistor 356 in the pulse output circuit of the first stage is turned on because the second clock signal (CLK2) is at H level. Accordingly, the voltage at the node A is kept at H level due to the voltage at the node C which is at H level in the period T1.
Thus, each of the nodes in the pulse output circuit of the first stage is kept at the same level as in the period T1.
On the other hand, since the second clock signal (CLK2) retains H level, the thin film transistor 351 in the pulse output circuit of the second stage is turned on.
Then, the voltage at the node D rises to H level due to the voltage at the node out1 which is at H level.
When the voltage at the node D rises to H level, the thin film transistor 353 in the pulse output circuit of the second stage is turned on.
Then, the voltage at the node E drops to L level due to the low power supply potential at L level.
When the voltage at the node E drops to L level, the thin film transistor 355 and the thin film transistor 358 in the pulse output circuit of the second stage are turned off.
When the thin film transistor 355 in the pulse output circuit of the second stage is turned off, the voltage at the node F rises to H level due to the high power supply potential at H level. Moreover, when the thin film transistor 358 in the pulse output circuit of the second stage is turned off, the voltage at the node out2 rises to H level due to the high power supply potential at H level.
Note that since the first clock signal (CLK1) is at L level, the thin film transistor 356 in the pulse output circuit of the second stage and the thin film transistor 351 in the pulse output circuit of the third stage are turned off.
Next, operation in a period T3 in
When the first clock signal retains H level, the thin film transistor 351 in the pulse output circuit of the first stage is turned on. On the other hand, the thin film transistor 356 in the pulse output circuit of the first stage is turned off due to the second clock signal (CLK2) at L level. Accordingly, the voltage at the node A drops to L level.
When the voltage at the node A drops to L level, the thin film transistor 353 in the pulse output circuit of the first stage is turned off.
Then, the voltage at the node B rises to H level due to the high power supply potential at H level.
When the voltage at the node B rises to H level, the thin film transistor 355 and the thin film transistor 358 in the pulse output circuit of the first stage are turned off.
When the thin film transistor 355 in the pulse output circuit of the first stage is turned on, the voltage at the node C drops to L level due to the low power supply potential at L level. Moreover, when the thin film transistor 358 in the pulse output circuit of the first stage is turned on, the voltage at the node out1 drops to L level due to the low power supply potential at L level.
Note that since the second clock signal (CLK2) is at L level, the thin film transistor 356 in the pulse output circuit of the first stage is turned off.
Furthermore, as in the pulse output circuit of the first stage in the period T2, the thin film transistor 351 in the pulse output circuit of the second stage is turned off due to the second clock signal at L level. On the other hand, the first clock signal (CLK1) is at H level; thus, the thin film transistor 356 in the pulse output circuit of the second stage is turned on. Accordingly, the voltage at the node D is kept at H level due to the voltage at the node F which is at H level in the period T2.
Thus, each of the nodes in the pulse output circuit of the second stage is kept at the same level as in the period T2.
On the other hand, when the first clock signal (CLK1) retains H level, the thin film transistor 351 in the pulse output circuit of the third stage is turned on.
Then, the voltage at the node G rises to H level due to the voltage at the node out2 which is at H level.
When the voltage at the node G rises to H level, the thin film transistor 353 in the pulse output circuit of the third stage is turned on.
Subsequently, the transistors are controlled to be on or off in sequence, whereby the circuit illustrated in
Note that in the pulse output circuit illustrated in
In addition, in the source line driver circuit, a NAND of a signal output from each pulse output circuit is calculated to generate a signal for driving each source line. Accordingly, in the source line driver circuit, a larger number of pulse output circuits than source lines are preferably provided to generate a signal output to a source line.
Operation of the circuit illustrated in
A first input clock signal (CLK1) having an amplitude of L level/H level=VSS/VDD0 is input to a signal input portion (CLK in1).
When the first input clock signal is at H level, a thin film transistor 602 is turned on. Here, the on-resistance of the thin film transistor 602 is set much lower than the resistance of a resistor 601. Thus, a node α becomes L level.
When the node α is at L level, a thin film transistor 604 is turned off. Here, the off-resistance of the thin film transistor 604 is set much higher than the resistance of a resistor 603. Thus, a node β becomes H level, and the H level becomes substantially equal to VDD. As a result, amplitude conversion is completed.
In the level shifter illustrated in
When an H-level signal is input to a signal input portion (In1) and a signal input portion (In2), the thin film transistors 702 and 703 are turned on, whereby an L-level signal is output to a signal output portion (Out).
On the other hand, when an L-level signal is input to one or both of the signal input portion (In1) and the signal input portion (In2), an H-level signal having a potential of VDD is output to the signal output portion (Out).
A first clock signal (CLK1), a second clock signal (CLK2), and a start pulse (SP) are input to the gate line driver circuit. The amplitude of these input signals is converted by the clock signal level shifter 751 or the start pulse level shifter 752 immediately after they have been input from the outside as signals with low voltage amplitude, and then the signals are input to the driver circuit as signals with high voltage amplitude.
Note that the structure and operation of the clock signal level shifter 751, the start pulse level shifter 752, the pulse output circuit 753, the NAND circuit 754, and the buffer 755 are similar to those used in the source line driver circuit, and thus the above description applies here.
Next,
The pulse output circuit illustrated in
The connection relationship of each circuit element in
An oxide semiconductor layer with a rectangular shape is used for the resistors 352, 354, and 357 in the ERMOS circuit illustrated in
Note that in each layout of the pulse output circuits illustrated in
Next, a structure of an inverter circuit including the resistor 354 and the thin film transistor 355 illustrated in the layouts of
In
Note that the first wiring 901 serves as one terminal of the resistor 354. The second wiring 907 serves as the other terminal of the resistor 354 and one terminal of the thin film transistor 355, as well as a wiring for connecting the resistor 354 and the thin film transistor 355. Similarly, the third wiring 908 serves as the second terminal of the thin film transistor 355 as well as a wiring to which a low power supply potential VSS is supplied (also referred to as a low potential line). In other words, the connecting wiring and the low (high) power supply potential line are partly used as the first terminal or the second terminal of each thin film transistor.
In
Next, materials of the ERMOS circuit illustrated in
In
The insulating layer 903 can be made of an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a tantalum oxide film. The insulating layer 903 may have a multi-layer structure of these insulating films. Note that the silicon oxynitride film refers to a film which contains more oxygen than nitrogen and contains oxygen, nitrogen, silicon, and hydrogen at given concentrations ranging from 55 to 65 atomic %, 1 to 20 atomic %, 25 to 35 atomic %, and 0.1 to 10 atomic %, respectively, where the total percentage of atoms is 100 atomic %. Further, the silicon nitride oxide film refers to a film which contains more nitrogen than oxygen and contains oxygen, nitrogen, silicon, and hydrogen at given concentrations ranging from 15 to 30 atomic %, 20 to 35 atomic %, 25 to 35 atomic %, and 15 to 25 atomic %, respectively, where the total percentage of atoms is 100 atomic %.
The first oxide semiconductor layer 905 and the second oxide semiconductor layer 906 are made of a thin film containing a compound represented by InMO3(ZnO)m (m>0). Note that M denotes one or more of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co). For example, M is gallium (Ga) in some cases, and in other cases, M contains other metal elements in addition to gallium (Ga), such as gallium (Ga) and nickel (Ni) or gallium (Ga) and iron (Fe). Furthermore, the above oxide semiconductor layer may contain a transition metal element such as iron (Fe) or nickel (Ni) or an oxide of the transition metal as an impurity element in addition to a metal element contained as M. In addition, the concentration of sodium (Na) contained in the above oxide semiconductor layer is 5×1018 atoms/cm3 or less, preferably 1×1018 atoms/cm3 or less.
As the material of the second wiring 907 and the third wiring 908, it is possible to use an element selected from aluminum (Al), chromium (Cr), tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing any of the elements, an alloy film combining the elements, or the like. The second wiring 907 and the third wiring 908 may have a multi-layer structure of these elements.
A silicon oxide layer 909 is made of a silicon oxide film deposited by sputtering. A silicon nitride layer 910 deposited over the entire surface of the substrate is formed by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3). Accordingly, the silicon nitride layer 910 contains a high concentration of hydrogen.
In addition, as illustrated in
Note that the buffer layers 911a to 911c are oxide semiconductor layers having a low resistance, which are formed using an In—Ga—Zn—O-based non-single-crystal film deposited under conditions different from those under which the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906 are formed. In the description below, for convenience, an oxide semiconductor film for forming the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906 is referred to as a first oxide semiconductor film, and an oxide semiconductor film for forming the buffer layers 911a to 911c is referred to as a second oxide semiconductor film.
For example, in the case where an oxide semiconductor film is deposited by sputtering, the resistance of the oxide semiconductor film can be changed by changing the oxygen concentration in a sputtering gas used for the deposition. In specific, the resistance of the oxide semiconductor film can be increased by increasing the oxygen concentration in a sputtering gas. One of the conditions for depositing the first oxide semiconductor film and the second oxide semiconductor film by sputtering is as follows: a sputtering gas containing an argon gas at a flow rate of 10 sccm and an oxygen gas at a flow rate of 5 sccm is used for depositing the first oxide semiconductor film; and a sputtering gas containing an argon gas at a flow rate of 40 sccm is used for depositing the second oxide semiconductor film. Note that the buffer layers 911a to 911c have n-type conductivity and an activation energy (ΔE) of 0.1 eV or less. The buffer layers 911a to 911c formed using an In—Ga—Zn—O-based non-single-crystal film include at least an amorphous component. The buffer layers 911a to 911c include a crystal grain (nanocrystal) in the amorphous structure in some cases. The crystal grain (nanocrystal) in the buffer layers 911a to 911c has a diameter of 1 nm to 10 nm, and typically about 2 nm to 4 nm.
By providing the buffer layers 911a to 911c having a lower resistance than the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906, a better contact than a Schottky junction can be made between the second wiring 907 that is a conductor and the first oxide semiconductor layer 905, and between the second wiring 907 and the third wiring 908 that are conductors, and the second oxide semiconductor layer 906. As a result, thermally stable operation can be achieved. Furthermore, by providing the buffer layers 911b and 911c in the thin film transistor 355, good mobility can be maintained even at a high drain voltage.
In addition, as illustrated in
By providing the buffer layer 911d, a better contact than a Schottky junction can be made between the first wiring 901 that is a conductor and the first oxide semiconductor layer 905, and thermally stable operation can be achieved.
Next, thin film transistors having a structure different from those illustrated in
In
Although an inverted staggered thin film transistor is shown in
In
In
An ERMOS circuit having the aforementioned structure includes a resistor in which the first oxide semiconductor layer 905 on which the silicon nitride layer 910 is provided in direct contact therewith is used for a resistor element, and a thin film transistor in which the second oxide semiconductor layer 906 over which the silicon nitride layer 910 is provided with the silicon oxide layer 909 (the channel protective layer 1001) interposed therebetween is used for a channel formation region. Accordingly, a higher concentration of hydrogen can be introduced into the first oxide semiconductor layer 905 than into the second oxide semiconductor layer 906. As a result, the resistance of the first oxide semiconductor layer 905 can be made lower than that of the second oxide semiconductor layer 906.
Next, a manufacturing process of the ERMOS circuit will be described with reference to cross-sectional views of
A first conductive film is deposited over the substrate 900. The first conductive film is deposited by a thin film deposition method typified by sputtering, vacuum evaporation, pulse laser deposition, ion plating, and the like. As the material of the first conductive film, a low-resistance conductive material such as aluminum (Al) or copper (Cu) can be used. Alternatively, the first conductive film may be formed of aluminum (Al) in combination with a heat-resistant conductive material. As the heat-resistant conductive material, it is possible to use an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy containing any of the elements, an alloy film combining the elements, or a nitride containing any of the elements. Then, a resist is formed over the first conductive film by a first photolithography step. Furthermore, the first conductive film is selectively etched using the resist as a mask, thereby forming the first wiring 901 and the gate terminal 902.
Then, an insulating film is formed to cover the first wiring 901 and the gate terminal 902. The insulating film is deposited by a thin film deposition method typified by sputtering, vacuum evaporation, pulse laser deposition, ion plating, plasma CVD, and the like. The insulating film can be made of an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a tantalum oxide film. The insulating film may have a multi-layer structure of these insulating films. Then, a resist is formed over the insulating film by a second photolithography step. Furthermore, the insulating film is selectively etched using the resist as a mask, thereby forming the insulating layer 903 having the contact hole 904 that reaches the first wiring.
Then, a second oxide semiconductor film is deposited. The second oxide semiconductor film is deposited by a thin film deposition method typified by sputtering, vacuum evaporation, pulse laser deposition, ion plating, plasma CVD, and the like. In the case where the second oxide semiconductor film is deposited by sputtering, it is preferable to use a target made by sintering In2O3, Ga2O3, and ZnO. As a sputtering gas, a rare gas typified by an argon gas is used. One of the deposition conditions by sputtering is as follows: a target made by mixing and sintering In2O3, Ga2O3, and ZnO (1:1:1) is used; pressure is 0.4 Pa; direct current (DC) power source is 500 W; and the flow rate of argon gas is 40 sccm.
Then, a second conductive film is deposited. The second conductive film is deposited by a thin film deposition method typified by sputtering, vacuum evaporation, pulse laser deposition, ion plating, and the like. As the material of the second conductive film, it is possible to use an element selected from aluminum (Al), chromium (Cr), tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing any of the elements, an alloy film combining the elements, or the like. The second conductive film may have a multi-layer structure of these elements.
Then, a resist is formed over the second conductive film by a third photolithography step. Furthermore, the second oxide semiconductor film and the second conductive film are selectively etched using the resist as a mask, thereby forming the second wiring 907, the third wiring 908, and the buffer layers 1010a and 1010b. This etching step is performed by wet etching or dry etching. For example, in the case where an aluminum (Al) film or an aluminum alloy film is used as the second conductive film, wet etching can be performed using a mixed solution of phosphoric acid, acetic acid, and nitric acid. Similarly, in the case where a titanium (Ti) film or a titanium alloy film is used as the second conductive film, wet etching can be performed using an ammonia hydrogen peroxide mixture (hydrogen peroxide:ammonia:water=5:2:2).
Then, a first oxide semiconductor film is deposited. The first oxide semiconductor film is deposited by a thin film deposition method typified by sputtering, vacuum evaporation, pulse laser deposition, ion plating, and the like. The first oxide semiconductor film is deposited under the conditions in which a sputtering gas contains a higher oxygen concentration than under the conditions for forming the second oxide semiconductor film. One of the deposition conditions by sputtering is as follows: a target made by mixing and sintering In2O3, Ga2O3, and ZnO (1:1:1) is used; pressure is 0.4 Pa; direct current (DC) power source is 500 W; the flow rate of argon gas is 10 sccm; and the flow rate of oxygen gas is 5 sccm.
Before depositing the first oxide semiconductor film, reverse sputtering where an argon gas is introduced to generate plasma is preferably performed, so that dust attached to the insulating layer 903, the first wiring 901, the second wiring 907, and the third wiring 908 can be removed. In addition, the reverse sputtering is preferably conducted in an atmosphere in which oxygen is added to argon, whereby the first wiring 901, the second wiring 907, and the third wiring 908 that are conductors are oxidized, resulting in an increase in the resistance in the vicinity of the interface with the second oxide semiconductor film. Thus, the off-current of a thin film transistor formed later can be reduced. Note that the reverse sputtering is a method in which voltage is applied to a substrate side in an argon atmosphere with the use of an RF power source without applying voltage to a target side, so that plasma is generated to modify the surface of the substrate.
Then, a resist is formed over the first oxide semiconductor film by a fourth photolithography step. Furthermore, the first oxide semiconductor film is selectively etched using the resist as a mask, thereby forming the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906.
Then, a silicon oxide film is deposited by sputtering. For example, the silicon oxide film can be deposited using silicon as a target and using a sputtering gas containing argon and oxygen. Alternatively, the silicon oxide film can be deposited using silicon oxide as a target and using argon as a sputtering gas. Subsequently, a resist is formed over the silicon oxide film by a fifth photolithography step. Furthermore, the silicon oxide film is selectively etched using the resist as a mask, thereby forming the silicon oxide layer 909 over the second oxide semiconductor layer 906.
Then, the silicon nitride layer 910 serving as a passivation film is deposited over the entire surface of the substrate. The silicon nitride layer 910 is formed by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3), and is a silicon nitride layer containing a high concentration of hydrogen.
Then, heat treatment is performed at 200° C. to 600° C., typically 250° C. to 500° C. For example, heat treatment is performed in a furnace in a nitrogen atmosphere at 350° C. for one hour.
Through the above steps, the resistor 354 and the thin film transistor 355 can be manufactured using the oxide semiconductor layers.
Note that the order of the steps described above is an example and there is no particular limitation on the order. Manufacturing steps different from those in
A first conductive film is deposited over the substrate 900. Then, a resist is formed over the first conductive film by a first photolithography step. Furthermore, the first conductive film is selectively etched using the resist as a mask, thereby forming the first wiring 901 and the gate terminal 902.
Then, an insulating film is formed to cover the first wiring 901 and the gate terminal 902. After that, a second oxide semiconductor film is deposited. Then, a second conductive film is deposited. Subsequently, a resist is formed over the second conductive film by a second photolithography step. Furthermore, the second conductive film and the second oxide semiconductor film are selectively etched using the resist as a mask, thereby forming the second wiring 907, the third wiring 908, and the buffer layers 1010a and 1010b.
Then, a resist is formed over the insulating film by a third photolithography step. Furthermore, the insulating film is selectively etched using the resist as a mask, thereby forming the insulating layer 903 having the contact hole 904 that reaches the first wiring 901.
Then, a first oxide semiconductor film is deposited. After that, a resist is formed over the first oxide semiconductor film by a fourth photolithography step. Furthermore, the first oxide semiconductor film is selectively etched using the resist as a mask, thereby forming the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906.
Then, a silicon oxide film is deposited by sputtering. Subsequently, a resist is formed over the silicon oxide film by a fifth photolithography step. Furthermore, the silicon oxide film is selectively etched using the resist as a mask, thereby forming the silicon oxide layer 909 to cover the second oxide semiconductor layer 906.
Then, the silicon nitride layer 910 serving as a passivation film is deposited over the entire surface of the substrate by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3).
Then, heat treatment is performed at 200° C. to 600° C. in a nitrogen atmosphere.
Through the above steps, the resistor 354 and the thin film transistor 355 can be manufactured using the oxide semiconductor layers. In addition, in the steps illustrated in
The resistor and the thin film transistor described in this embodiment are formed using the oxide semiconductor layers. Accordingly, a driver circuit including the resistor and the thin film transistor has good dynamic characteristics. Moreover, the silicon nitride layer formed by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3) is provided on and in direct contact with the first oxide semiconductor layer used for the resistor, and the silicon nitride layer is provided over the second oxide semiconductor layer used for the thin film transistor with the silicon oxide layer serving as a barrier layer interposed therebetween. Therefore, a higher concentration of hydrogen is introduced into the first oxide semiconductor layer in direct contact with the silicon nitride layer containing a high concentration of hydrogen than into the second oxide semiconductor layer. As a result, the resistance of the first oxide semiconductor layer can be made lower than that of the second oxide semiconductor layer. Thus, the thin film transistor and the resistor do not need to be manufactured in different steps, which makes it possible to provide a driver circuit manufactured in a smaller number of steps.
In this embodiment, another example of the resistor and the thin film transistor, which is different from that of Embodiment 1, will be described with reference to
The first wiring 901 and the gate terminal 902 are provided over the substrate 900. Then, the insulating layer 903 is provided over the first wiring 901 and the gate terminal 902. Note that the substrate 900, the first wiring 901, the gate terminal 902, and the insulating layer 903 can be made of the materials described in Embodiment 1; thus, the description of Embodiment 1 applies in this embodiment.
A first oxide semiconductor layer 2001 containing a high concentration of nitrogen and a second oxide semiconductor layer 2002 containing a high concentration of nitrogen are provided over the insulating layer 903 so as to overlap the first wiring 901 and the gate terminal 902, respectively. Note that the first wiring 901 is in contact with the first oxide semiconductor layer 2001 containing a high concentration of nitrogen through the contact hole 904 formed in the insulating layer 903.
Note that the first oxide semiconductor layer 2001 containing a high concentration of nitrogen and the second oxide semiconductor layer 2002 containing a high concentration of nitrogen are oxide semiconductor layers with a high concentration of nitrogen, which are formed of an oxide semiconductor film formed under conditions different from those under which the first oxide semiconductor film and the second oxide semiconductor film shown in Embodiment 1 are formed. In specific, the first oxide semiconductor layer 2001 and the second oxide semiconductor layer 2002 each have a ratio of nitrogen (N) to oxygen (O) (N/O) of 0.05 to 0.8, preferably 0.1 to 0.5.
For example, in the case where the oxide semiconductor film containing a high concentration of nitrogen is deposited by sputtering, deposition may be performed using a sputtering gas containing a nitrogen gas. One of the deposition conditions by sputtering is as follows: a target including In2O3, Ga2O3, and ZnO (1:1:1) (In:Ga:Zn=1:1:0.5) is used; pressure is 0.4 Pa; direct current (DC) power source is 500 W; the flow rate of argon gas is 35 sccm and the flow rate of nitrogen gas is 5 sccm. Note that it is preferable to use a pulsed direct current (DC) power source so that dust can be reduced and thickness distribution can be evened. Subsequently, the oxide semiconductor film containing a high concentration of nitrogen is subjected to photolithography, thereby forming the first oxide semiconductor layer 2001 containing a high concentration of nitrogen and the second oxide semiconductor layer 2002 containing a high concentration of nitrogen.
Then, the second wiring 907 and the third wiring 908 are provided. The second wiring 907 covers one end of the first oxide semiconductor layer 2001 containing a high concentration of nitrogen and one end of the second oxide semiconductor layer 2002 containing a high concentration of nitrogen, and the third wiring 908 covers the other end of the second oxide semiconductor layer 2002 containing a high concentration of nitrogen. Note that the second wiring 907 and the third wiring 908 can be made of the materials described in Embodiment 1; thus, the description of Embodiment 1 applies in this embodiment.
Then, the silicon oxide layer 909 is provided over the second oxide semiconductor layer 2002 containing a high concentration of nitrogen. The silicon oxide layer is formed by selectively etching a silicon oxide film which is deposited by sputtering. The silicon oxide film can be deposited using silicon as a target and using a sputtering gas containing argon and oxygen, or deposited using silicon oxide as a target and using a sputtering gas containing argon.
At this time, heat treatment is performed at 200° C. to 600° C., typically 250° C. to 500° C. in an atmosphere containing a substance which is a supply source of a hydrogen atom. For example, the heat treatment is performed at 350° C. for one hour. As the atmosphere containing a substance which is a supply source of a hydrogen atom, a mixed atmosphere of hydrogen and a rare gas such as argon can be used.
Nitrogen in the oxide semiconductor layer has the effect of preventing atoms forming the oxide semiconductor layer from tightly filling the film, and of promoting diffusion and solid dissolution of hydrogen in the film. Accordingly, the heat treatment allows hydrogen to be introduced into the first oxide semiconductor layer 2001 containing a high concentration of nitrogen. As a result, the concentration of hydrogen in the first oxide semiconductor layer 2001 containing a high concentration of nitrogen becomes higher than that in the second oxide semiconductor layer 2002 containing a high concentration of nitrogen. In other words, the resistance of the first oxide semiconductor layer 2001 containing a high concentration of nitrogen can be made lower than that of the second oxide semiconductor layer 2002 containing a high concentration of nitrogen.
Furthermore, the silicon nitride layer 910 is formed over the entire surface of the substrate by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3). The silicon nitride layer 910 is a silicon nitride layer containing a high concentration of hydrogen. Accordingly, the concentration of hydrogen in the first oxide semiconductor layer 2001 containing a high concentration of nitrogen that is in direct contact with the silicon nitride layer 910 can be further increased to reduce resistance.
Through the above steps, it is possible to form the resistor 354 using the first oxide semiconductor layer 2001 containing a high concentration of nitrogen and having a low resistance and the thin film transistor 355 using the second oxide semiconductor layer 2002 containing a high concentration of nitrogen and having a high resistance.
Although the cross-sectional structure of the resistor corresponding to the line A-B in
In this embodiment, the cross-sectional structure of the channel-etched thin film transistor is shown; however, a channel-stop thin film transistor can also be used. Furthermore, although the inverted staggered thin film transistor is shown in this embodiment, a coplanar thin film transistor can also be used.
The resistor and the thin film transistor shown in this embodiment are formed using the oxide semiconductor layer containing a high concentration of nitrogen. Thus, a driver circuit including the resistor and the thin film transistor has good dynamic characteristics. In addition, since the heat treatment is performed at 200° C. to 600° C., typically 250° C. to 500° C. in an atmosphere containing a substance which is a supply source of a hydrogen atom, hydrogen is introduced into the first oxide semiconductor layer containing a high concentration of nitrogen that is used for the resistor. Accordingly, a higher concentration of hydrogen is introduced into the first oxide semiconductor layer containing a high concentration of nitrogen than into the second oxide semiconductor layer containing a high concentration of nitrogen. As a result, the resistance of the first oxide semiconductor layer containing a high concentration of nitrogen can be made lower than that of the second oxide semiconductor layer containing a high concentration of nitrogen. Thus, the thin film transistor and the resistor do not need to be manufactured in different steps, which makes it possible to provide a driver circuit manufactured in a smaller number of steps.
In this embodiment, a resistor and a thin film transistor that are manufactured using the oxide semiconductor layer described in Embodiment 1 and the oxide semiconductor layer containing a high concentration of nitrogen described in Embodiment 2 will be described with reference to
In this embodiment, specifically, a structure in which the oxide semiconductor layer containing a high concentration of nitrogen described in Embodiment 2 is used instead of the buffer layers described in Embodiment 1 will be described with reference to
First, a first conductive film is deposited over the substrate 900. The first conductive film is deposited by a thin film deposition method typified by sputtering, vacuum evaporation, pulse laser deposition, ion plating, and the like. Then, a resist is formed over the first conductive film by a first photolithography step. Furthermore, the first conductive film is selectively etched using the resist as a mask, thereby forming the first wiring 901 and the gate terminal 902. Then, an insulating film is formed to cover the first wiring 901 and the gate terminal 902. The insulating film is deposited by a thin film deposition method typified by sputtering, vacuum evaporation, pulse laser deposition, ion plating, plasma CVD, and the like. Subsequently, a resist is formed over the insulating film by a second photolithography step. Furthermore, the insulating film is selectively etched using the resist as a mask, thereby forming the insulating layer 903 having the contact hole 904. Note that the first wiring 901, the gate terminal 902, and the insulating layer 903 can be made of the materials described in Embodiment 1; thus, the description of Embodiment 1 applies in this embodiment.
Then, an oxide semiconductor film 950 is deposited. The oxide semiconductor film 950 is deposited by a thin film deposition method typified by sputtering, vacuum evaporation, pulse laser deposition, ion plating, plasma CVD, and the like. In the case where the oxide semiconductor film 950 is deposited by sputtering, it is preferable to use a target made by sintering In2O3, Ga2O3, and ZnO. One of the deposition conditions by sputtering is as follows: a target made by mixing and sintering In2O3, Ga2O3, and ZnO (1:1:1) is used; pressure is 0.4 Pa; direct current (DC) power source is 500 W; the flow rate of argon gas is 10 sccm; and the flow rate of oxygen gas is 5 sccm.
Then, an oxide semiconductor film 951 containing a high concentration of nitrogen is deposited. The oxide semiconductor film 951 containing a high concentration of nitrogen is deposited by a thin film deposition method typified by sputtering, vacuum evaporation, pulse laser deposition, ion plating, and the like. In the case where the oxide semiconductor film 951 is deposited by sputtering, it is preferable to use a target made by sintering In2O3, Ga2O3, and ZnO. The oxide semiconductor film 951 containing a high concentration of nitrogen is deposited by sputtering, for example, under the following conditions: a target made by mixing and sintering In2O3, Ga2O3, and ZnO (1:1:1) is used; pressure is 0.4 Pa; direct current (DC) power source is 500 W; the flow rate of argon gas is 35 sccm; and the flow rate of nitrogen gas is 5 sccm.
Then, a resist is formed over the oxide semiconductor film 951 containing a high concentration of nitrogen by a third photolithography step. Furthermore, the oxide semiconductor film 950 and the oxide semiconductor film 951 containing a high concentration of nitrogen are selectively etched using the resist as a mask, thereby forming a stack of a first oxide semiconductor layer 960 and a first oxide semiconductor layer 961 containing a high concentration of nitrogen, and a stack of a second oxide semiconductor layer 962 and a second oxide semiconductor layer 963 containing a high concentration of nitrogen.
At this time, heat treatment is performed at 200° C. to 600° C., typically 250° C. to 500° C. in an atmosphere containing a substance which is a supply source of a hydrogen atom. For example, the heat treatment is performed at 350° C. for one hour. As the atmosphere containing a substance which is a supply source of a hydrogen atom, a mixed atmosphere of hydrogen and a rare gas such as argon can be used.
Nitrogen in the oxide semiconductor layer has the effect of preventing atoms forming the oxide semiconductor layer from tightly filling the film, and of promoting diffusion and solid dissolution of hydrogen in the film. Accordingly, the heat treatment allows hydrogen to be introduced into the first oxide semiconductor layer 961 containing a high concentration of nitrogen and the second oxide semiconductor layer 963 containing a high concentration of nitrogen. As a result, the resistance of the first oxide semiconductor layer 961 containing a high concentration of nitrogen and the second oxide semiconductor layer 963 containing a high concentration of nitrogen can be reduced.
Then, a second conductive film is deposited. The second conductive film is deposited by a thin film deposition method typified by sputtering, vacuum evaporation, pulse laser deposition, ion plating, and the like. Then, a resist is formed over the second conductive film by a fourth photolithography step. Furthermore, the second conductive film is selectively etched using the resist as a mask, thereby forming the second wiring 907 and the third wiring 908. Note that the second wiring 907 and the third wiring 908 can be made of the materials described in Embodiment 1; thus, the description of Embodiment 1 applies in this embodiment. In this etching step, the oxide semiconductor layer containing a high concentration of nitrogen in a region that does not overlap the second wiring 907 and the third wiring 908 is etched to be removed. In addition, part of the oxide semiconductor layer in that region is also etched to form oxide semiconductor layers 964 and 966 and oxide semiconductor layers 965, 967, and 968 containing a high concentration of nitrogen.
Then, a silicon oxide film is deposited by sputtering. For example, the silicon oxide film can be deposited using silicon as a target and using a sputtering gas containing argon and oxygen. Alternatively, the silicon oxide film can be deposited using silicon oxide as a target and using argon as a sputtering gas. Subsequently, a resist is formed over the silicon oxide film by a fifth photolithography step. Furthermore, the silicon oxide film is selectively etched using the resist as a mask, thereby forming the silicon oxide layer 909.
Then, the silicon nitride layer 910 serving as a passivation film is deposited. The silicon nitride layer 910 is formed by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3). Through the above steps, the resistor 354 and the thin film transistor 355 are formed.
In the resistor 354 and the thin film transistor 355 shown in this embodiment, the oxide semiconductor layers 965, 967, and 968 containing a high concentration of nitrogen, into which hydrogen is introduced and which have a low resistance, are formed between the oxide semiconductor layers and the wiring layers that are conductors. Accordingly, a better contact than a Schottky junction can be made between the oxide semiconductor layers and the wiring layers, and thermally stable operation can be achieved. In addition, by providing the oxide semiconductor layers 967 and 968 containing a high concentration of nitrogen in the thin film transistor 355, good mobility can be maintained even at a high drain voltage.
Note that the aforementioned manufacturing process shows an example in which heat treatment for introducing hydrogen into the oxide semiconductor layer containing a high concentration of nitrogen is conducted after the etching step of the oxide semiconductor layer. However, the heat treatment may be conducted at any time after deposition of the oxide semiconductor film containing a high concentration of nitrogen and before deposition of the second conductive film. For example, the heat treatment can be conducted in the subsequent step of deposition of the oxide semiconductor film containing a high concentration of nitrogen.
Although the cross-sectional structure of the resistor corresponding to the line A-B in
In this embodiment, the cross-sectional structure of the channel-etched thin film transistor is shown; however, a channel-stop thin film transistor can also be used. Furthermore, although the inverted staggered thin film transistor is shown in this embodiment, a coplanar thin film transistor can also be used.
The resistor and the thin film transistor described in this embodiment are formed using the oxide semiconductor layer and the oxide semiconductor layer containing a high concentration of nitrogen. Accordingly, a driver circuit including the resistor and the thin film transistor has good dynamic characteristics. Moreover, the silicon nitride layer formed by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3) is provided on and in direct contact with the first oxide semiconductor layer used for the resistor, and the silicon nitride layer is provided over the second oxide semiconductor layer used for the thin film transistor with the silicon oxide layer serving as a barrier layer interposed therebetween. Therefore, a higher concentration of hydrogen is introduced into the first oxide semiconductor layer in direct contact with the silicon nitride layer containing a high concentration of hydrogen than into the second oxide semiconductor layer. As a result, the resistance of the first oxide semiconductor layer can be made lower than that of the second oxide semiconductor layer. Thus, the thin film transistor and the resistor do not need to be manufactured in different steps, which makes it possible to provide a driver circuit manufactured in a smaller number of steps.
In this embodiment, an example of a structure of a driver circuit including a shift register formed by a dynamic circuit will be described with reference to
A pulse output circuit 1400 illustrated in
First, operation will be described in which the first clock signal (CLK1) is at H level and the second clock signal (CLK2) is at L level.
An inverted signal of the start pulse (SP) appears at the node A. The signal at the node B is equal to that at the node A because the first clock signal (CLK1) is at H level. The signal at the node B is inverted by the inverter circuit in the subsequent stage, whereby an inverted signal of the signal at the node B appears at the node C. The signal at the node C does not appear at the node D because the second clock signal (CLK2) is at L level and the switch is closed.
Next, operation will be described in which the first clock signal (CLK1) is at L level and the second clock signal (CLK2) is at H level.
The signal at the node C transfers to the node D, and the signal at the node C is reflected in and appears at the node D. Then, the signal at the node D is inverted by the inverter circuit, whereby the inverted signal of the signal at the node D appears at the node E. After that, the first clock signal (CLK1) and the second clock signal (CLK2) are alternately at H level, so that the circuit illustrated in
A shift register including the pulse output circuits shown in this embodiment can be used for a source line driver circuit and a gate line driver circuit. Note that a signal may be output from the shift register via a logic circuit or the like so that a desired signal can be obtained.
The dynamic circuit described in this embodiment includes an ERMOS circuit. The ERMOS circuit includes the resistor and the thin film transistor shown in Embodiments 1 to 3. Accordingly, the dynamic circuit has good dynamic characteristics.
In this embodiment, an example of a display device including a protective circuit will be described with reference to
Furthermore, a protective circuit 550 is provided between the first gate line driver circuit 502A and the pixel portion, and a protective circuit 551 is provided between the source line driver circuit 501 and the pixel portion. The protective circuits 550 and 551 are connected to wirings extending from the first gate line driver circuit 502A and the source line driver circuit 501 to the pixel portion 503. By providing the protective circuits 550 and 551, even when noise is input together with signals or power supply voltages, it is possible to prevent malfunction of the circuit in the subsequent stage or degradation or destruction of a semiconductor element due to the noise. Thus, reliability and yield can be increased.
Next, a circuit structure of the protective circuits 550 and 551 illustrated in
A protective circuit illustrated in
The anode of the diode-connected n-channel thin film transistor 560 is connected to a wiring to which a low power supply potential VSS is supplied. The anode of the diode-connected n-channel thin film transistor 561 is connected to the cathode of the diode-connected n-channel thin film transistor 560, and the cathode of the diode-connected n-channel thin film transistor 561 is connected to a wiring 569. The anode of the diode-connected n-channel thin film transistor 562 is connected to the wiring 569. The anode of the diode-connected n-channel thin film transistor 563 is connected to the cathode of the diode-connected n-channel thin film transistor 562, and the cathode of the diode-connected n-channel thin film transistor 563 is connected to a high power supply potential VDD. The diode-connected n-channel thin film transistors 564 to 567 are connected in a manner similar to that of the diode-connected n-channel thin film transistors 560 to 563. The resistor 568 is connected in series to a terminal to which an input potential Vin is input and a terminal from which an output potential Vout is output.
Operation of the protective circuit illustrated in
When the input potential Vin from the driver circuit is extremely high, specifically, when the input potential Vin is higher than the sum of the high power supply potential VDD and the forward voltage drop of the diode-connected n-channel thin film transistors 562 and 563, the diode-connected n-channel thin film transistors 562 and 563 are turned on and the wiring 569 has a potential corresponding to the sum of the high power supply potential VDD and the forward voltage drop of the diode-connected n-channel thin film transistors 562 and 563.
On the other hand, when the input potential Vin from the driver circuit is extremely low, specifically, when the input potential Vin is lower than the difference between the low power supply potential VSS and the forward voltage drop of the diode-connected n-channel thin film transistors 560 and 561, the diode-connected n-channel thin film transistors 560 and 561 are turned on and the wiring 569 has a potential corresponding to the difference between the low power supply potential VSS and the forward voltage drop of the diode-connected n-channel thin film transistors 560 and 561.
Thus, the output potential Vout of the protective circuit can be kept within a given range.
Note that this embodiment shows the structure including the diode-connected n-channel thin film transistors 564 to 567 that are connected in a manner similar to that of the diode-connected n-channel thin film transistors 560 to 563. The diode-connected n-channel thin film transistors 564 to 567 can increase the number of current paths in the case where the input potential Vin from the driver circuit is extremely high or low. Accordingly, the reliability of the display device can be further increased.
In addition, the resistor 568 suppresses a rapid change in the potential of the wiring 569, thereby preventing degradation or destruction of a semiconductor element in the pixel portion.
A protective circuit illustrated in
The resistor 570 and the resistor 571 can suppress a rapid change in the potential of the wiring 573, thereby preventing degradation or destruction of a semiconductor element in the pixel portion. Furthermore, the diode-connected n-channel thin film transistor 572 can prevent the flow of a reverse bias current through the wiring 573 due to a change in potential.
Note that when only the resistors are connected in series to the wiring, a rapid change in the potential of the wiring can be suppressed and degradation or destruction of a semiconductor element in the pixel portion can be prevented. Further, when only the diode-connected n-channel thin film transistor is connected in series to the wiring, a reverse bias current due to a change in potential can be prevented from flowing through the wiring.
Note that the structure of the protective circuit of this embodiment is not limited to those illustrated in
The protective circuit described in this embodiment includes the resistor and the thin film transistor shown in Embodiments 1 to 3. Accordingly, the protective circuit has good dynamic characteristics.
In this embodiment, an example of a light-emitting display device will be described as a semiconductor device including the resistor and the thin film transistor described in Embodiments 1 to 3. Here, a light-emitting display device including a light-emitting element utilizing electroluminescence is described. Light-emitting elements utilizing electroluminescence are classified according to whether a light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.
In an organic EL element, by application of voltage to a light-emitting element, electrons and holes are separately injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. Then, the carriers (electrons and holes) are recombined, so that the light-emitting organic compound is excited. The light-emitting organic compound returns to a ground state from the excited state, thereby emitting light. Owing to such a mechanism, this light-emitting element is referred to as a current-excitation light-emitting element.
The inorganic EL elements are classified according to their element structures into a dispersion-type inorganic EL element and a thin-film inorganic EL element. A dispersion-type inorganic EL element has a light-emitting layer where particles of a light-emitting material are dispersed in a binder, and its light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. A thin-film inorganic EL element has a structure where a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and its light emission mechanism is localized type light emission that utilizes inner-shell electron transition of metal ions. Description is made here using an organic EL element as a light-emitting element.
The structure and operation of a pixel that can be used will be described. A pixel shown here includes an n-channel thin film transistor using an oxide semiconductor layer for a channel formation region.
A second electrode of the light-emitting element 6403 corresponds to a common electrode 6408. The common electrode 6408 is electrically connected to a common potential line provided over the same substrate. Note that the second electrode of the light-emitting element 6403 (the common electrode 6408) is set to a low power supply potential VSS. For example, GND or 0 V may be set as the low power supply potential VSS. The difference between the high power supply potential VDD applied to the power supply line 6407 and the low power supply potential VSS applied to the second electrode is applied to the light-emitting element 6403, whereby flow currents through the light-emitting element 6403 and the light-emitting element 6403 emits light. Thus, each potential is set so that the difference between the high power supply potential VDD and the low power supply potential VSS is equal to or higher than a forward threshold voltage of the light-emitting element 6403.
Next, a structure of the light-emitting element will be described with reference to
In order to extract light emitted from the light-emitting element, at least one of the anode and the cathode is required to transmit light. A thin film transistor and a light-emitting element are formed over a substrate. A light-emitting element can have a top emission structure in which light is extracted through the surface opposite to the substrate; a bottom emission structure in which light is extracted through the surface on the substrate side; or a dual emission structure in which light is extracted through the surface opposite to the substrate and the surface on the substrate side. The pixel structure illustrated in
A light-emitting element having a top emission structure will be described with reference to
A region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel illustrated in
Next, a light-emitting element having a bottom emission structure will be described with reference to
A region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 corresponds to the light-emitting element 7012. In the case of the pixel illustrated in
Next, a light-emitting element having a dual emission structure will be described with reference to
A region where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap each other corresponds to the light-emitting element 7022. In the case of the pixel illustrated in
Although an organic EL element is described here as a light-emitting element, an inorganic EL element can also be provided as a light-emitting element.
Next, the appearance and a cross section of a light-emitting display panel (also referred to as a light-emitting panel), which is one embodiment of the display device, will be described with reference to
A sealant 4505 is provided to surround a pixel portion 4502, source line driver circuits 4503a and 4503b, and gate line driver circuits 4504a and 4504b, which are provided over a first substrate 4501. In addition, a second substrate 4506 is provided over the pixel portion 4502, the source line driver circuits 4503a and 4503b, and the gate line driver circuits 4504a and 4504b. Accordingly, the pixel portion 4502, the source line driver circuits 4503a and 4503b, and the gate line driver circuits 4504a and 4504b are sealed together with a filler 4507, by the first substrate 4501, the sealant 4505, and the second substrate 4506. It is preferable that a display device be thus packaged (sealed) with a protective film (such as a bonding film or an ultraviolet curable resin film) or a cover material with high air-tightness and little degasification so that the display device is not exposed to the outside air.
Like the source line driver circuits 4503a and 4503b, and the gate line driver circuits 4504a and 4504b, the pixel portion 4502 formed over the first substrate 4501 includes a thin film transistor manufactured using an oxide semiconductor. In
In this embodiment, the thin film transistor illustrated in
Reference numeral 4511 denotes a light-emitting element. A first electrode layer 4517 that is a pixel electrode included in the light-emitting element 4511 is electrically connected to a source electrode layer or a drain electrode layer of the thin film transistor 4510. Note that a structure of the light-emitting element 4511 is not limited to the stacked structure shown in this embodiment, which includes the first electrode layer 4517, an electroluminescent layer 4512, and a second electrode layer 4513. The structure of the light-emitting element 4511 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 4511, or the like.
A partition wall 4520 is made of an organic resin film, an inorganic insulating film, or organic polysiloxane. It is particularly preferable that the partition wall 4520 be made of a photosensitive material and include an opening over the first electrode layer 4517 so that a sidewall of the opening is formed as an inclined surface with continuous curvature.
The electroluminescent layer 4512 may be formed using a single layer or a plurality of layers stacked.
A protective film may be formed over the second electrode layer 4513 and the partition wall 4520 in order to prevent oxygen, hydrogen, moisture, carbon dioxide, or the like from entering into the light-emitting element 4511. As the protective film, a silicon nitride layer, a silicon nitride oxide layer, a DLC layer, or the like can be formed.
A variety of signals and potentials are supplied to the source line driver circuits 4503a and 4503b, the gate line driver circuits 4504a and 4504b, or the pixel portion 4502 from FPCs 4518a and 4518b.
In this embodiment, a connection terminal electrode 4515 is formed using the same conductive film as the first electrode layer 4517 included in the light-emitting element 4511, and a terminal electrode 4516 is formed using the same conductive film as the source and drain electrode layers included in the thin film transistors 4509 and 4510.
The connection terminal electrode 4515 is electrically connected to a terminal of the FPC 4518a through an anisotropic conductive film 4519.
The second substrate 4506 located in the direction in which light is extracted from the light-emitting element 4511 needs to have a light-transmitting property. In that case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.
As the filler 4507, an ultraviolet curable resin or a thermosetting resin can be used, in addition to an inert gas such as nitrogen or argon. For example, PVC (polyvinyl chloride), acrylic, polyimide, an epoxy resin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used for the filler 4507.
If needed, an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (a quarter-wave plate or a half-wave plate), or a color filter may be provided as appropriate on a light-emitting surface of the light-emitting element. Furthermore, the polarizing plate or the circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment by which reflected light can be diffused by projections and depressions on the surface so as to reduce the glare can be performed.
The source line driver circuits 4503a and 4503b and the gate line driver circuits 4504a and 4504b may be mounted as driver circuits formed over a substrate separately prepared. Alternatively, only the source line driver circuits or part thereof, or only the gate line driver circuits or part thereof may be separately formed and mounted. This embodiment is not limited to the structure illustrated in
The light-emitting display device described in this embodiment includes the resistor and the thin film transistor shown in Embodiments 1 to 3. Accordingly, the light-emitting display device has good dynamic characteristics.
In this embodiment, an example of electronic paper will be described as a semiconductor device including the resistor and the thin film transistor shown in Embodiments 1 to 3.
The thin film transistor 581 provided over a first substrate 580 is a bottom-gate thin film transistor. A first terminal or a second terminal of the thin film transistor 581 is in contact with a first electrode layer 587 through an opening formed in an insulating layer 585, whereby the thin film transistor 581 is electrically connected to the first electrode layer 587. Spherical particles 589 each having a black region 590a, a white region 590b, and a cavity 594 around the regions which is filled with liquid are provided between the first electrode layer 587 and a second electrode layer 588, and further sandwiched between the first substrate 580 and the second substrate 596. A space around the spherical particles 589 is filled with a filler 595 such as a resin (see
Instead of the twisting ball, an electrophoretic element can also be used. A microcapsule having a diameter of about 10 μm to 200 μm, in which transparent liquid, positively charged white microparticles, and negatively charged black microparticles are encapsulated, is used. In the microcapsule that is provided between the first electrode layer and the second electrode layer, when an electric field is applied between the first electrode layer and the second electrode layer, the white microparticles and the black microparticles move to opposite sides from each other, so that white or black can be displayed. A display element using this principle is an electrophoretic display element and is generally called electronic paper. The electrophoretic display element has higher reflectance than a liquid crystal display element, and thus, an auxiliary light is unnecessary, power consumption is low, and a display portion can be recognized in a dim place. In addition, even when power is not supplied to the display portion, an image which has been displayed once can be maintained. Accordingly, a displayed image can be stored even if a semiconductor device having a display function (which may be referred to simply as a display device or a semiconductor device provided with a display device) is distanced from an electric wave source.
The electronic paper described in this embodiment includes the resistor and the thin film transistor shown in Embodiments 1 to 3. Accordingly, the electronic paper has good dynamic characteristics.
In this embodiment, examples of an electronic appliance will be described as a semiconductor device including the resistor and the thin film transistor shown in Embodiments 1 to 3.
The electronic appliances described in this embodiment each include the resistor and the thin film transistor shown in Embodiments 1 to 3. Accordingly, the electronic appliances have good dynamic characteristics.
This application is based on Japanese Patent Application serial No. 2008-327998 filed with Japan Patent Office on Dec. 24, 2008, the entire contents of which are hereby incorporated by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2008-327998 | Dec 2008 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 5403762 | Takemura | Apr 1995 | A |
| 5403772 | Zhang et al. | Apr 1995 | A |
| 5563426 | Zhang et al. | Oct 1996 | A |
| 5572046 | Takemura | Nov 1996 | A |
| 5604360 | Zhang et al. | Feb 1997 | A |
| 5731856 | Kim et al. | Mar 1998 | A |
| 5744864 | Cillessen et al. | Apr 1998 | A |
| 5847410 | Nakajima | Dec 1998 | A |
| 5888857 | Zhang et al. | Mar 1999 | A |
| 6140165 | Zhang et al. | Oct 2000 | A |
| 6140198 | Liou | Oct 2000 | A |
| 6191452 | Oda et al. | Feb 2001 | B1 |
| 6294274 | Kawazoe et al. | Sep 2001 | B1 |
| 6323071 | Zhang et al. | Nov 2001 | B1 |
| 6338991 | Zhang et al. | Jan 2002 | B1 |
| 6413805 | Zhang et al. | Jul 2002 | B1 |
| 6479331 | Takemura | Nov 2002 | B1 |
| 6555419 | Oda et al. | Apr 2003 | B2 |
| 6563174 | Kawasaki et al. | May 2003 | B2 |
| 6586346 | Yamazaki et al. | Jul 2003 | B1 |
| 6727522 | Kawasaki et al. | Apr 2004 | B1 |
| 6806125 | Zhang et al. | Oct 2004 | B2 |
| 6867075 | Oda et al. | Mar 2005 | B2 |
| 6872605 | Takemura | Mar 2005 | B2 |
| 6875628 | Zhang et al. | Apr 2005 | B1 |
| 6960812 | Yamazaki et al. | Nov 2005 | B2 |
| 6987283 | Zhang et al. | Jan 2006 | B2 |
| 7049190 | Takeda et al. | May 2006 | B2 |
| 7061014 | Hosono et al. | Jun 2006 | B2 |
| 7064346 | Kawasaki et al. | Jun 2006 | B2 |
| 7105868 | Nause et al. | Sep 2006 | B2 |
| 7211825 | Shih et al | May 2007 | B2 |
| 7230316 | Yamazaki et al. | Jun 2007 | B2 |
| 7238558 | Takemura | Jul 2007 | B2 |
| 7282782 | Hoffman et al. | Oct 2007 | B2 |
| 7297977 | Hoffman et al. | Nov 2007 | B2 |
| 7301211 | Yamazaki et al. | Nov 2007 | B2 |
| 7323356 | Hosono et al. | Jan 2008 | B2 |
| 7385224 | Ishii et al. | Jun 2008 | B2 |
| 7391051 | Zhang et al. | Jun 2008 | B2 |
| 7402506 | Levy et al. | Jul 2008 | B2 |
| 7411209 | Endo et al. | Aug 2008 | B2 |
| 7453065 | Saito et al. | Nov 2008 | B2 |
| 7453087 | Iwasaki | Nov 2008 | B2 |
| 7462862 | Hoffman et al. | Dec 2008 | B2 |
| 7468304 | Kaji et al. | Dec 2008 | B2 |
| 7501293 | Ito et al. | Mar 2009 | B2 |
| 7550328 | Kunii | Jun 2009 | B2 |
| 7601984 | Sano et al. | Oct 2009 | B2 |
| 7602456 | Tanaka | Oct 2009 | B2 |
| 7622335 | Zhang et al. | Nov 2009 | B2 |
| 7674650 | Akimoto et al. | Mar 2010 | B2 |
| 7700418 | Kunii | Apr 2010 | B2 |
| 7732819 | Akimoto et al. | Jun 2010 | B2 |
| 7804091 | Takechi et al. | Sep 2010 | B2 |
| 7855379 | Hayashi et al. | Dec 2010 | B2 |
| 7858451 | Maekawa et al. | Dec 2010 | B2 |
| 7863607 | Lee et al. | Jan 2011 | B2 |
| 7939822 | Maekawa et al. | May 2011 | B2 |
| 7943930 | Zhang et al. | May 2011 | B2 |
| 7998372 | Yano et al. | Aug 2011 | B2 |
| 8026152 | Yamazaki et al. | Sep 2011 | B2 |
| 8062935 | Zhang et al. | Nov 2011 | B2 |
| 8088652 | Hayashi et al. | Jan 2012 | B2 |
| 8102476 | Son et al. | Jan 2012 | B2 |
| 8143115 | Omura et al. | Mar 2012 | B2 |
| 8148721 | Hayashi et al. | Apr 2012 | B2 |
| 8158974 | Yano et al. | Apr 2012 | B2 |
| 8164256 | Sano et al. | Apr 2012 | B2 |
| 8207533 | Maekawa et al. | Jun 2012 | B2 |
| 8232124 | Takechi et al. | Jul 2012 | B2 |
| 8247814 | Maekawa et al. | Aug 2012 | B2 |
| 8278660 | Zhang et al. | Oct 2012 | B2 |
| 8415198 | Itagaki et al. | Apr 2013 | B2 |
| 8436349 | Sano et al. | May 2013 | B2 |
| 8441102 | Yamazaki et al. | May 2013 | B2 |
| 8476625 | Kimura | Jul 2013 | B2 |
| 8541944 | Sano et al. | Sep 2013 | B2 |
| 8575618 | Maekawa et al. | Nov 2013 | B2 |
| 8742421 | Yamazaki et al. | Jun 2014 | B2 |
| 8803768 | Kimura et al. | Aug 2014 | B2 |
| 9130049 | Sano et al. | Sep 2015 | B2 |
| 20010046027 | Tai et al. | Nov 2001 | A1 |
| 20020056838 | Ogawa | May 2002 | A1 |
| 20020132454 | Ohtsu et al. | Sep 2002 | A1 |
| 20030189401 | Kido et al. | Oct 2003 | A1 |
| 20030218221 | Wager, III et al. | Nov 2003 | A1 |
| 20030218222 | Wager, III et al. | Nov 2003 | A1 |
| 20040038446 | Takeda et al. | Feb 2004 | A1 |
| 20040127038 | Carcia et al. | Jul 2004 | A1 |
| 20050017302 | Hoffman | Jan 2005 | A1 |
| 20050199959 | Chiang et al. | Sep 2005 | A1 |
| 20060035452 | Carcia et al. | Feb 2006 | A1 |
| 20060043377 | Hoffman et al. | Mar 2006 | A1 |
| 20060091793 | Baude et al. | May 2006 | A1 |
| 20060108529 | Saito et al. | May 2006 | A1 |
| 20060108636 | Sano et al. | May 2006 | A1 |
| 20060110867 | Yabuta et al. | May 2006 | A1 |
| 20060113536 | Kumomi et al. | Jun 2006 | A1 |
| 20060113539 | Sano et al. | Jun 2006 | A1 |
| 20060113549 | Den et al. | Jun 2006 | A1 |
| 20060113565 | Abe et al. | Jun 2006 | A1 |
| 20060169973 | Isa et al. | Aug 2006 | A1 |
| 20060170067 | Maekawa et al. | Aug 2006 | A1 |
| 20060170111 | Isa et al. | Aug 2006 | A1 |
| 20060197092 | Hoffman et al. | Sep 2006 | A1 |
| 20060208977 | Kimura | Sep 2006 | A1 |
| 20060228974 | Thelss et al. | Oct 2006 | A1 |
| 20060231882 | Kim et al. | Oct 2006 | A1 |
| 20060238135 | Kimura | Oct 2006 | A1 |
| 20060244107 | Sugihara et al. | Nov 2006 | A1 |
| 20060284171 | Levy et al. | Dec 2006 | A1 |
| 20060284172 | Ishii | Dec 2006 | A1 |
| 20060292777 | Dunbar | Dec 2006 | A1 |
| 20070024187 | Shin et al. | Feb 2007 | A1 |
| 20070046191 | Saito | Mar 2007 | A1 |
| 20070052025 | Yabuta | Mar 2007 | A1 |
| 20070054507 | Kaji et al. | Mar 2007 | A1 |
| 20070072439 | Akimoto | Mar 2007 | A1 |
| 20070090365 | Hayashi et al. | Apr 2007 | A1 |
| 20070108446 | Akimoto | May 2007 | A1 |
| 20070115219 | Inoue | May 2007 | A1 |
| 20070141784 | Wager, III et al. | Jun 2007 | A1 |
| 20070152217 | Lai et al. | Jul 2007 | A1 |
| 20070172591 | Seo et al. | Jul 2007 | A1 |
| 20070187678 | Hirao et al. | Aug 2007 | A1 |
| 20070187760 | Furuta et al. | Aug 2007 | A1 |
| 20070194379 | Hosono et al. | Aug 2007 | A1 |
| 20070252928 | Ito et al. | Nov 2007 | A1 |
| 20070272922 | Kim et al. | Nov 2007 | A1 |
| 20070287296 | Chang | Dec 2007 | A1 |
| 20080006877 | Mardilovich et al. | Jan 2008 | A1 |
| 20080038882 | Takechi et al. | Feb 2008 | A1 |
| 20080038929 | Chang | Feb 2008 | A1 |
| 20080050595 | Nakagawara et al. | Feb 2008 | A1 |
| 20080067508 | Endo | Mar 2008 | A1 |
| 20080073653 | Iwasaki | Mar 2008 | A1 |
| 20080083950 | Pan et al. | Apr 2008 | A1 |
| 20080106191 | Kawase | May 2008 | A1 |
| 20080128689 | Lee et al. | Jun 2008 | A1 |
| 20080129195 | Ishizaki et al. | Jun 2008 | A1 |
| 20080158217 | Hata et al. | Jul 2008 | A1 |
| 20080166475 | Jeong | Jul 2008 | A1 |
| 20080166834 | Kim et al. | Jul 2008 | A1 |
| 20080176364 | Yang et al. | Jul 2008 | A1 |
| 20080182358 | Cowdery-Corvan et al. | Jul 2008 | A1 |
| 20080191332 | Koyama et al. | Aug 2008 | A1 |
| 20080203387 | Kang et al. | Aug 2008 | A1 |
| 20080213927 | Wang et al. | Sep 2008 | A1 |
| 20080224133 | Park et al. | Sep 2008 | A1 |
| 20080254569 | Hoffman et al. | Oct 2008 | A1 |
| 20080258139 | Ito et al. | Oct 2008 | A1 |
| 20080258140 | Lee et al. | Oct 2008 | A1 |
| 20080258141 | Park et al. | Oct 2008 | A1 |
| 20080258143 | Kim et al. | Oct 2008 | A1 |
| 20080291350 | Hayashi et al. | Nov 2008 | A1 |
| 20080296568 | Ryu et al. | Dec 2008 | A1 |
| 20080303020 | Shin et al. | Dec 2008 | A1 |
| 20080308796 | Akimoto et al. | Dec 2008 | A1 |
| 20080308797 | Akimoto et al. | Dec 2008 | A1 |
| 20080308804 | Akimoto et al. | Dec 2008 | A1 |
| 20080308805 | Akimoto et al. | Dec 2008 | A1 |
| 20080308806 | Akimoto et al. | Dec 2008 | A1 |
| 20090008639 | Akimoto et al. | Jan 2009 | A1 |
| 20090045397 | Iwasaki | Feb 2009 | A1 |
| 20090065771 | Iwasaki | Mar 2009 | A1 |
| 20090068773 | Lai et al. | Mar 2009 | A1 |
| 20090073325 | Kuwabara et al. | Mar 2009 | A1 |
| 20090101895 | Kawamura et al. | Apr 2009 | A1 |
| 20090114910 | Chang | May 2009 | A1 |
| 20090114911 | Maekawa et al. | May 2009 | A1 |
| 20090134399 | Sakakura et al. | May 2009 | A1 |
| 20090141203 | Son | Jun 2009 | A1 |
| 20090152506 | Umeda et al. | Jun 2009 | A1 |
| 20090152541 | Maekawa et al. | Jun 2009 | A1 |
| 20090179199 | Sano et al. | Jul 2009 | A1 |
| 20090237000 | Inoue | Sep 2009 | A1 |
| 20090278122 | Hosono et al. | Nov 2009 | A1 |
| 20090280600 | Hosono et al. | Nov 2009 | A1 |
| 20100025678 | Yamazaki et al. | Feb 2010 | A1 |
| 20100051937 | Kaji et al. | Mar 2010 | A1 |
| 20100065837 | Omura | Mar 2010 | A1 |
| 20100065844 | Tokunaga | Mar 2010 | A1 |
| 20100092800 | Itagaki et al. | Apr 2010 | A1 |
| 20100109002 | Itagaki et al. | May 2010 | A1 |
| 20100117073 | Yamazaki | May 2010 | A1 |
| 20110032435 | Kimura | Feb 2011 | A1 |
| 20120168748 | Yano et al. | Jul 2012 | A1 |
| 20120168750 | Hayashi et al. | Jul 2012 | A1 |
| 20140346506 | Kimura et al. | Nov 2014 | A1 |
| 20150325707 | Sano et al. | Nov 2015 | A1 |
| Number | Date | Country |
|---|---|---|
| 101325202 | Dec 2008 | CN |
| 1737044 | Dec 2006 | EP |
| 1918904 | May 2008 | EP |
| 1939842 | Jul 2008 | EP |
| 2226847 | Sep 2010 | EP |
| 2579237 | Apr 2013 | EP |
| 2425401 | Oct 2006 | GB |
| 59-009959 | Jan 1984 | JP |
| 60-198861 | Oct 1985 | JP |
| 63-210022 | Aug 1988 | JP |
| 63-210023 | Aug 1988 | JP |
| 63-210024 | Aug 1988 | JP |
| 63-215519 | Sep 1988 | JP |
| 63-239117 | Oct 1988 | JP |
| 63-265818 | Nov 1988 | JP |
| 03-231472 | Oct 1991 | JP |
| 04-100270 | Apr 1992 | JP |
| 05-198806 | Aug 1993 | JP |
| 05-251705 | Sep 1993 | JP |
| 07-104312 | Apr 1995 | JP |
| 07-226373 | Aug 1995 | JP |
| 08-264794 | Oct 1996 | JP |
| 09-186332 | Jul 1997 | JP |
| 10-242474 | Sep 1998 | JP |
| 11-111994 | Apr 1999 | JP |
| 11-505377 | May 1999 | JP |
| 2000-044236 | Feb 2000 | JP |
| 2000-150900 | May 2000 | JP |
| 2002-076356 | Mar 2002 | JP |
| 2002-158304 | May 2002 | JP |
| 2002-289859 | Oct 2002 | JP |
| 2003-086000 | Mar 2003 | JP |
| 2003-086808 | Mar 2003 | JP |
| 2004-103957 | Apr 2004 | JP |
| 2004-221570 | Aug 2004 | JP |
| 2004-273614 | Sep 2004 | JP |
| 2004-273732 | Sep 2004 | JP |
| 2005-077822 | Mar 2005 | JP |
| 2005-167212 | Jun 2005 | JP |
| 2006-128666 | May 2006 | JP |
| 2006-163507 | Jun 2006 | JP |
| 2006-165532 | Jun 2006 | JP |
| 2007-096055 | Apr 2007 | JP |
| 2007-115808 | May 2007 | JP |
| 2007-123861 | May 2007 | JP |
| 2007-142195 | Jun 2007 | JP |
| 2007-194594 | Aug 2007 | JP |
| 2007-194628 | Aug 2007 | JP |
| 2007-220817 | Aug 2007 | JP |
| 2007-250983 | Sep 2007 | JP |
| 2008-040343 | Feb 2008 | JP |
| 2008-053356 | Mar 2008 | JP |
| 2008-060419 | Mar 2008 | JP |
| 2008-134625 | Jun 2008 | JP |
| 2008-141119 | Jun 2008 | JP |
| 2008-217778 | Sep 2008 | JP |
| 2008-218495 | Sep 2008 | JP |
| 2008-294136 | Dec 2008 | JP |
| 2006-0089144 | Aug 2006 | KR |
| 2006-0113745 | Nov 2006 | KR |
| 2007-0111975 | Nov 2007 | KR |
| 2008-0047179 | May 2008 | KR |
| 200730985 | Aug 2007 | TW |
| 200838302 | Sep 2008 | TW |
| 200847297 | Dec 2008 | TW |
| 200847421 | Dec 2008 | TW |
| 200847441 | Dec 2008 | TW |
| WO-2004114391 | Dec 2004 | WO |
| WO-2005055178 | Jun 2005 | WO |
| WO-2006051993 | May 2006 | WO |
| WO-2007119386 | Oct 2007 | WO |
| WO-2008023553 | Feb 2008 | WO |
| WO-2008069056 | Jun 2008 | WO |
| WO-2008069255 | Jun 2008 | WO |
| WO-2008069286 | Jun 2008 | WO |
| WO-2008105250 | Sep 2008 | WO |
| WO-2008105347 | Sep 2008 | WO |
| WO-2008117739 | Oct 2008 | WO |
| WO-2008133345 | Nov 2008 | WO |
| WO-2011148537 | Dec 2011 | WO |
| Entry |
|---|
| Taiwanese Office Action (Application No. 102115027) Dated Jan. 27, 2015. |
| Prins.M et al., “A Ferroelectric Transparent Thin-Film Transistor”, Appl. Phys. Lett. (Applied Physics Letters) , Jun. 17, 1996, vol. 68, No. 25, pp. 3650-3652. |
| Nakamura.M et al., “The phase relations in the In2O3—Ga2ZnO4—ZnO system at 1350° C.”, Journal of Solid State Chemistry, Aug. 1, 1991, vol. 93, No. 2, pp. 298-315. |
| Kimizuka.N et al., “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m (m = 3, 4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m (m = 7, 8, 9, and 16) in the In2O3—ZnGa2O4—ZnO System”, Journal of Solid State Chemistry, Apr. 1, 1995, vol. 116, No. 1, pp. 170-178. |
| Nomura.K et al., “Thin-Film Transistor Fabricated in Single-Crystalline Transparent Oxide Semiconductor”, Science, May 23, 2003, vol. 300, No. 5623, pp. 1269-1272. |
| Nomura.K et al., “Room-Temperature Fabrication of Transparent Flexible Thin-Film Transistors Using Amorphous Oxide Semiconductors”, Nature, Nov. 25, 2004, vol. 432, pp. 488-492. |
| Hayashi.R et al., “42.1: Invited Paper: Improved Amorphous In—Ga—Zn—O TFTs”, SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 621-624. |
| Search Report (Application No. 09178444.7) Dated Feb. 15, 2010. |
| Nakamura.M et al., “Syntheses and crystal structures of new homologous compounds, indium iron zinc oxides (InFeO3(ZnO)m) (m natural number) and related compounds”, Kotai Butsuri (Solid State Physics), 1993, vol. 28, No. 5, pp. 317-327. |
| Dembo.H et al., “RFCPUS on Glass and Plastic Substrates Fabricated by TFT Transfer Technology”, IEDM 05: Technical Digest of International Electron Devices Meeting, Dec. 5, 2005, pp. 1067-1069. |
| Ikeda.T et al., “Full-Functional System Liquid Crystal Display Using CG-Silicon Technology”, SID Digest '04 : SID International Symposium Digest of Technical Papers, 2004, vol. 35, pp. 860-863. |
| Takahashi.M et al., “Theoretical Analysis of IGZO Transparent Amorphous Oxide Semiconductor”, IDW '08 : Proceedings of the 15th International Display Workshops, Dec. 3, 2008, pp. 1637-1640. |
| Osada.T et al., “15.2: Development of Driver-Integrated Panel using Amorphous In—Ga—Zn—Oxide TFT”, SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 184-187. |
| Li.C et al., “Modulated Structures of Homologous Compounds InMO3(ZnO)m (M=In,Ga; m=Integer) Described by Four-Dimensional Superspace Group”, Journal of Solid State Chemistry, 1998, vol. 139, pp. 347-355. |
| Lee.J et al., “World's Largest (15-Inch) XGA AMLCD Panel Using IGZO Oxide TFT”, SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 625-628. |
| Nowatari.H et al., “60.2: Intermediate Connector With Suppressed Voltage Loss for White Tandem OLEDs”, SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, vol. 40, pp. 899-902. |
| Kanno.H et al., “White Stacked Electrophosphorecent Organic Light-Emitting Devices Employing MOO3 as a Charge-Generation Layer”, Adv. Mater. (Advanced Materials), 2006, vol. 18, No. 3, pp. 339-342. |
| Tsuda.K et al., “Ultra Low Power Consumption Technologies for Mobile TFT-LCDs ”, IDW '02 : Proceedings of the 9th International Display Workshops, Dec. 4, 2002, pp. 295-298. |
| Jeong.J et al., “3.1: Distinguished Paper: 12.1-Inch WXGA AMOLED Display Driven by Indium—Gallium—Zinc Oxide TFTs Array”, SID Digets '08 : SID International Symposium Digets of Technical Papers, May 20, 2008, vol. 39, No. 1, pp. 1-4. |
| Park.J et al., “High performance amorphous oxide thin film transistors with self-aligned top-gate structure”, IEDM 09: Technical Digest of International Electron Devices Meeting, Dec. 7, 2009, pp. 191-194. |
| Kurokawa.Y et al., “UHF RFCPUS on Flexible and Glass Substrates for Secure RFID Systems”, Journal of Solid-State Circuits , 2008, vol. 43, No. 1, pp. 292-299. |
| Ohara.H et al., “Amorphous In—Ga—Zn—Oxide TFTs with Suppressed Variation for 4.0 inch QVGA AMOLED Display”, AM-FPD '09 Digest of Technical Papers, Jul. 1, 2009, pp. 227-230, The Japan Society of Applied Physics. |
| Coates.D et al., “Optical Studies of the Amorphous Liquid-Cholesteric Liquid Crystal Transition:The “Blue Phase””, Physics Letters, Sep. 10, 1973, vol. 45A, No. 2, pp. 115-116. |
| Cho.D et al., “21.2:AL and SN-Doped Zinc Indium Oxide Thin Film Transistors for AMOLED Back-Plane”, SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 280-283. |
| Lee.M et al., “15.4:Excellent Performance of Indium—Oxide-Based Thin-Film Transistors by DC Sputtering”, SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 191-193. |
| Jin.D et al., “65.2:Distinguished Paper:World-Largest (6.5″) Flexible Full Color Top Emission AMOLED Display on Plastic Film and its Bending Properties”, SID Digest '09 : SID International Symposium Digets of Technical Papers, May 31, 2009, pp. 983-985. |
| Sakata.J et al., “Development of 4.0-In. AMOLED Display With Driver Circuit Using Amorphous In—Ga—Zn—Oxide TFTs”, IDW '09 : Proceedings of the 16th International Display Workshops, 2009, pp. 689-692. |
| Park.J et al., “Amorphous Indium—Gallium—Zinc Oxide TFTs and Their Application for Large Size AMOLED”, AM-FPD '08 Digest of Technical Papers, Jul. 2, 2008, pp. 275-278. |
| Parks et al., “Challenge to Future Displays: Transparent AM-OLED Driven by Peald Grown ZnO TFT”, IMID '07 Digest, 2007, pp. 1249-1252. |
| Godo.H et al., “Temperature Dependence of Characteristics and Electronic Structure for Amorphous In—Ga—Zn—Oxide TFT”, AM-FPD '09 Digest of Technical Papers, Jul. 1, 2009, pp. 41-44. |
| Osada.T et al., “Development of Driver-Integrated Panel Using Amorphous In—Ga—Zn—Oxide TFT”, AM-FPD '09 Digest of Technical Papers, Jul. 1, 2009, pp. 33-36. |
| Hirao.T et al., “Novel Top-Gate Zinc Oxide Thin-Film Transistors (ZnO TFTs) for AMLCDS”, J. Soc. Inf. Display (Journal of the Society for Information Display), 2007, vol. 15, No. 1, pp. 17-22. |
| Hosono.H, “68.3:Invited Paper:Transparent Amorphous Oxide Semiconductors for High Performance TFT”, SID Digest '07 : SID International Symposium Digest of Technical Papers, 2007, vol. 38, pp. 1830-1833. |
| Godo.H et al., “P-9:Numerical Analysis on Temperature Dependence of Characteristics of Amorphous In—Ga—Zn—Oxide TFT”, SID Digest '09 : SID International Symposium of Technical Papers, May 31, 2009, pp. 1110-1112. |
| Ohara.H et al., “21.3:4.0 In. QVGA AMOLED Display Using In—Ga—Zn—Oxide TFTs With a Novel Passivation Layer”, SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 284-287. |
| Miyasaka.M, “Suftla Flexible Microelectronics on Their Way to Business”, SID Digest '07 : SID International Symposium Digest of Technical Papers, 2007, vol. 38, pp. 1673-1676. |
| Chern.H et al., “An Analytical Model for the Above-Threshold Characteristics of Polysilicon Thin-Film Transistors”, IEEE Transactions on Electron Devices, Jul. 1, 1995, vol. 42, No, 7, pp. 1240-1246. |
| Kikuchi.H et al., “39.1:Invited Paper:Optically Isotropic Nano-Structured Liquid Crystal Composites for Display Applications”, SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 578-581. |
| Asaoka.Y et al., “29.1:Polarizer-Free Reflective LCD Combined With Ultra Low-Power Driving Technology”, SID Digest '09 : SID International Symposium Digest of Technical Papers, May 31, 2009, pp. 395-398. |
| Lee.H et al., “Current Status of, Challenges to, and Perspective View of AM-OLED”, IDW '06 : Proceedings of the 13th International Display Workshops, Dec. 7, 2006, pp. 663-666. |
| Kikuchi.H et al., “62.2:Invited Paper:Fast Electro-Optical Switching in Polymer-Stabilized Liquid Crystalline Blue Phases for Display Application”, SID Digest '07 : SID International Symposium Digest of Technical Papers, 2007, vol. 38, pp. 1737-1740. |
| Kikuchi.H et al., “Polymer-Stabilized Liquid Crystal Blue Phases”, Nature Materials, Sep. 2, 2002, vol. 1, pp. 64-68. |
| Kimizuka.N et al., “Spinel,YBFE2O4, and YB2FE3O7 Types of Structures for Compounds in the IN2O3 and SC2O3—A2O3—BO Systems [A; Fe, Ga, or Al; B: Mg, Mn, Fe, Ni, Cu, or Zn] At Temperatures over 1000° C.”, Journal of Solid State Chemistry, 1985, vol. 60, pp. 382-384. |
| Kitzerow.H et al., “Observation of Blue Phases in Chiral Networks”, Liquid Crystals, 1993, vol. 14, No. 3, pp. 911-916. |
| Costello.M et al., “Electron Microscopy of a Cholesteric Liquid Crystal and Its Blue Phase”, Phys. Rev. A (Physical Review. A), May 1, 1984, vol. 29, No. 5, pp. 2957-2959. |
| Meiboom.S et al., “Theory of the Blue Phase of Cholesteric Liquid Crystals”, Phys. Rev. Lett. (Physical Review Letters), May 4, 1981, vol. 46, No. 18, pp. 1216-1219. |
| Nakamura.M, “Synthesis of Homologous Compound with New Long-Period Structure”, Nirim Newsletter, Mar. 1, 1995, vol. 150, pp. 1-4. |
| Hosono.H et al., “Working hypothesis to explore novel wide band gap electrically conducting amorphous oxides and examples”, J. Non-Cryst. Solids (Journal of Non-Crystalline Solids), 1996, vol. 198-200, pp. 165-169. |
| Orita.M et al., “Mechanism of Electrical Conductivity of Transparent InGaZnO4”, Phys. Rev, B (Physical Review. B), Jan. 15, 2000, vol. 61, No. 3, pp. 1811-1816. |
| Van de Walle.C, “Hydrogen as a Cause of Doping in Zinc Oxide”, Phys. Rev. Lett. (Physical Review Letters), Jul. 31, 2000, vol. 85, No. 5, pp. 1012-1015. |
| Orita.M et al., “Amorphous transparent conductive oxide InGaO3(ZnO)m (m <4):a Zn4s conductor”, Philosophical Magazine, 2001, vol. 81, No. 5, pp. 501-515. |
| Janotti.A et al., “Oxygen Vacancies in ZnO”, Appl. Phys. Lett. (Applied Physics Letters) , 2005, vol. 87, pp. 122102-1-122102-3. |
| Clark.S et al., “First Principles Methods Using Castep”, Zeitschrift fur Kristallographie, 2005, vol. 220, pp. 567-570. |
| Nomura.K et al., “Amorphous Oxide Semiconductors for High-Performance Flexible Thin-Film Transistors”, Jpn. J. Appl. Phys. (Japanese Journal of Applied Physics ) , 2006, vol. 45, No. 5B, pp. 4303-4308. |
| Janotti.A et al., “Native Point Defects in ZnO”, Phys. Rev. B (Physical Review. B), Oct. 4, 2007, vol. 76, No. 16, pp. 165202-1-165202-22. |
| Lany.S at al., “Dopability, Intrinsic Conductivity, and Nonstoichiometry of Transparent Conducting Oxides”, Phys. Rev. Lett. (Physical Review Letters), Jan. 26, 2007, vol. 98, pp. 045501-1-045501-4. |
| Park.J et al., “Improvements in the Device Characteristics of Amorphous Indium Gallium Zinc Oxide Thin-Film Transistors by Ar Plasma Treatment”, Appl. Phys. Lett. (Applied Physics Letters) , Jun. 26, 2007, vol. 90, No. 26, pp. 262106-1-262106-3. |
| Park.J et al., “Electronic Transport Properties of Amorphous Indium—Gallium—Zinc Oxide Semiconductor Upon Exposure to Water”, Appl. Phys. Lett. (Applied Physics Letters) , 2008, vol. 92, pp. 072104-1-072104-3. |
| Hsieh.H et al., “P-29:Modeling of Amorphous Oxide Semiconductor Thin Film Transistors and Subgap Density of States”, SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 1277-1280. |
| Oba.F et al., “Defect energetics in ZnO: A hybrid Hartree-Fock density functional study”, Phys. Rev. B (Physical Review. B), 2008, vol. 77, pp. 245202-1-245202-6. |
| Kim.S et al., “High-Performance oxide thin film transistors passivated by various gas plasmas”, 214th ECS Meeting, 2008, No. 2317, ECS. |
| Son.K et al., “42.4L: Late-News Paper: 4 Inch QVGA AMOLED Driven by the Threshold Voltage Controlled Amorphous GIZO (Ga2O3—In2O3—ZnO) TFT”, SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 633-636. |
| Park.Sang-Hee et al., “42.3: Transparent ZnO Thin Film Transistor for the Application of High Aperture Ratio Bottom Emission AM-OLED Display”, SID Digest '08 : SID International Symposium Digest of Technical Papers, May 20, 2008, vol. 39, pp. 629-632. |
| Fung.T et al., “2-D Numerical Simulation of High Performance Amorphous In—Ga—Zn—O TFTs for Flat Panel Displays”, AM-FPD '08 Digest of Technical Papers, Jul. 2, 2008, pp. 251-252, The Japan Society of Applied Physics. |
| Mo.Y et al., “Amorphous Oxide TFT Backplanes for Large Size AMOLED Displays”, IDW '08 : Proceedings of the 6th International Display Workshops, Dec. 3, 2008, pp. 581-584. |
| Asakuma.N et al., “Crystallization and Reduction of Sol-Gel-Derived Zinc Oxide Films by Irradiation With Ultraviolet Lamp”, Journal of Sol-Gel Science and Technology, 2003, vol. 26, pp. 181-184. |
| Fortunato.E et al., “Wide-Bandgap High-Mobility ZnO Thin-Film Transistors Produced At Room Temperature”, Appl. Phys. Lett. (Applied Physics Letters) , Sep. 27, 2004, vol. 85, No. 13, pp. 2541-2543. |
| Masuda.S et al., “Transparent thin film transistors using ZnO as an active channel layer and their electrical properties”, J. Appl. Phys. (Journal of Applied Physics) , Feb. 1, 2003, vol. 93, No. 3, pp. 1624-1630. |
| Oh.M et al., “Improving the Gate Stability of ZnO Thin-Film Transistors With Aluminum Oxide Dielectric Layers”, J. Electrochem. Soc. (Journal of the Electrochemical Society), 2008, vol. 155, No. 12, pp. H1009-H1014. |
| Park.J et al., “Dry etching of ZnO films and plasma-induced damage to optical properties”, J. Vac. Sci. Technol. B (Journal of Vacuum Science & Technology B), Mar. 1, 2003, vol. 21, No. 2, pp. 800-803. |
| Ueno.K et al., “Field-Effect Transistor on SrTiO3 With Sputtered Al2O3 Gate Insulator”, Appl. Phys. Lett. (Applied Physics Letters) , Sep. 1, 2003, vol. 83, No. 9, pp. 1755-1757. |
| Nomura.K et al., “Carrier transport in transparent oxide semiconductor with intrinsic structural randomness probed using single-crystalline InGaO3(ZnO)5 films”, Appl. Phys. Lett. (Applied Physics Letters ) , Sep. 13, 2004, vol. 85, No. 11, pp. 1993-1995. |
| Chinese Office Action (Application No. 200910262579.8) Dated Jun. 4, 2013. |
| Taiwanese Office Action (Application No. 98143361) Dated Jul. 24, 2014. |
| Chinese Office Action (Application No. 201410329038.3) Dated Jun. 12, 2016. |
| Chinese Office Action (Application No. 201410329040.0) Dated May 23, 2016. |
| Number | Date | Country | |
|---|---|---|---|
| 20140357019 A1 | Dec 2014 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12641446 | Dec 2009 | US |
| Child | 14461938 | US |
