The various embodiments according to the present patent will be described with reference to the accompanying drawings.
Referring to
Referring to
A second insulating layer 114 is formed on the entire surface so that it fully gap-fills the trench 110. The second insulating layer 114 may be formed using Spin On Glass (SOG), Boron Phosphorus Silicate Glass (BPSG) or O3-TEOS (Tetra Ethyl Ortho Silicate). The first and second insulating layers 112 and 114 are polished until the top surface of the hard mask layer 108 is exposed.
Referring to
A third insulating layer 116 is formed on the entire surface so that the trench 110 is fully gap-filled. The third insulating layer 116 is polished until a top surface of the hard mask layer 108 is exposed, thereby forming an isolation structure 118. The third insulating layer 116 may be composed of a HDP oxide layer. Accordingly, the trench 110 is completely gap-filled without void.
As described above, in accordance with the method of manufacturing the semiconductor devices according to the present invention, manufacturing cost can be reduced by applying inexpensive SOG to the process.
Furthermore, a trench can be gap-filled without voids by applying a low selectivity wet etch process.
Although the foregoing description has been made with reference to the various embodiments, it is to be understood that changes and modifications of the present patent may be made by those skilled in the art without departing from the spirit and scope of the present patent and appended claims.
Number | Date | Country | Kind |
---|---|---|---|
2006-42992 | May 2006 | KR | national |