Patent Application
20150188009
This application claims priority of Taiwan Patent Application No. 102148949, filed on Dec. 30, 2013, the entirety of which is incorporated by reference herein.
1. Field of the Invention
The present disclosure relates to semiconductor technology, and in particular relates to a method of manufacturing a semiconductor device that can increase carrier concentration and improve brightness.
2. Description of the Related Art
Light-emitting diode (LED) is a semiconductor device that can convert electrical energy into light energy, which includes at least a p-n junction constituted of, for example, a p-type semiconductor layer and an n-type semiconductor layer. When an appropriate bias is applied to the p-n junction, the electrons combine with the holes at the p-n junction and release energy. If the energy is released as light, a luminescence phenomenon happens.
To reduce the driving voltage of the light-emitting diodes and to improve the luminous efficiency of light-emitting diodes, various manufacturing technologies for the light-emitting diodes have been developed in recent years. In conventional light-emitting diode manufacturing processes, it is difficult to form a good Ohmic contact by a current-spreading layer composed of pure metals with a p-type semiconductor layer since the p-type semiconductor layer has a high work function. In order to reduce the contact resistance between the current-spreading layer and the p-type semiconductor layer, more than one type of metal is used to form the current-spreading layer. However, the design of the light-emitting diodes would be limited in currently known light-emitting diode manufacturing processes. Moreover, the luminous efficiency obtained by such manufacturing processes needs to be improved.
Therefore, though the existing manufacturing technologies of the light-emitting diodes have been used in various applications, a manufacturing method that can further reduce the driving voltage of the light-emitting diodes and improve the luminous efficiency of the light-emitting diodes is still under requirement.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
An embodiment of the present disclosure involves a method of manufacturing a semiconductor device. The method comprises providing a semiconductor structure, including a sequential stack of an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. A first metal layer and a second metal layer are formed on the semiconductor structure, wherein the second metal layer is disposed on the first metal layer. A heat treatment process is performed such that the first metal layer is oxidized to form a first metal oxide layer and the second metal layer is reversed to form a second metallic compound layer between the first metal oxide layer and the p-type semiconductor layer. The first metal oxide layer and the second metallic compound layer are then removed, and a mesa etching process is performed after performing the heat treatment process to remove a part of the p-type semiconductor layer, a part of the active layer, and a part of the n-type semiconductor layer, to form a mesa region exposing another part of the n-type semiconductor layer.
The present disclosure can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is set forth in order to provide a thorough understanding of the disclosed embodiments. The following description and the drawings are made for the purpose of illustrating the general principles of the disclosure and should not be taken in a limiting sense. The present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or drawings discussed. The scope of the invention is best determined by reference to the appended claims.
Refer to
The n-type semiconductor layer 104, the active layer 106 and the p-type semiconductor layer 108 may each be a single-layer structure or a multilayer structure. In the present embodiment, the n-type semiconductor layer 104, the active layer 106 and the p-type semiconductor layer 108 constitute a light-emitting diode structure. The active layer 106 may have a single heterostructure (SH), a double heterostructure (DH) or a multi-quantum well (MQW) structure, and the emission wavelength of the light-emitting diode structure can be adjusted by modifying the composition of the material constituting the active layer 106. The n-type semiconductor layer 104, the active layer 106 and the p-type semiconductor layer 108 may include gallium (Ga), aluminum (Al), indium (In), nitrogen (N), arsenic (As), phosphorus (P), silicon (Si), a compound thereof, or a combination thereof. Moreover, the n-type semiconductor layer 104 may further include an n-type dopant (for example, silicon) and the p-type semiconductor layer 108 may further include a p-type dopant (for example, magnesium). In the present embodiment, the n-type semiconductor layer 104 is n-type doped gallium nitride (n-GaN), the active layer 106 has a multi-quantum well structure, and the p-type semiconductor layer 108 is p-type doped gallium nitride (p-GaN). The n-type semiconductor layer 104, the active layer 106 and the p-type semiconductor layer 108 may be formed using any suitable epitaxial growth process. In the present embodiment, the n-type semiconductor layer 104, the active layer 106 and the p-type semiconductor layer 108 are epitaxially grown on the substrate 102 in sequence by a metal-organic chemical vapor deposition (MOCVD) process.
Continue to refer to
Then, refer to
In the present embodiment, a p-type doped GaN is used as the p-type semiconductor layer 108, and a nickel layer and a gold layer are used as the first metal layer 202 and the second metal layer 204, respectively. During performing the heat treatment process T, the gold atoms of the second metal layer 204 may pass through the first metal layer 202 and diffuse toward the p-type semiconductor layer 108, thereby forming a gold-rich second metallic compound layer 212 in the first metal layer 202. The gold atoms of the second metal layer 204 may also diffuse into the p-type semiconductor layer 108 and occupy the lattice sites of the gallium atoms that constitute the p-type semiconductor layer 108, such that a large number of vacancies are formed in the p-type semiconductor layer 108. As a result, a carrier concentrated region P is formed in the p-type semiconductor layer 108, as shown in
After the heat treatment process T is completed, an etching solution having a pH value less than 10 may be used to remove the first metal oxide layer 214 and the second metallic compound layer 212, thereby obtaining a semiconductor structure 100 with a carrier concentrated region P formed at the surface of the p-type semiconductor layer 108, as shown in
It is noted that the heat treatment process T must be performed before the mesa etching process. If the heat treatment process T is performed after the mesa etching process, the atomic bonds in the part of the n-type semiconductor layer 104 that are exposed from the mesa region 110 may be broken due to the heating temperature of the heat treatment process T, therefore resulting in the formation of defects. In consequence, the electrons may be captured by the defects more easily in the semiconductor device, and the electrical properties of the semiconductor device may be deteriorated. Accordingly, it is not desired.
Thereafter, other desired features may be formed on the semiconductor device 10 using any suitable semiconductor manufacturing technology to obtain a complete electronic device structure. For example, a p-type electrode and an n-type electrode (not shown) may be formed on the p-type semiconductor layer 108 and on the mesa region 110 that exposes another part of the n-type semiconductor layer 104, respectively, to electrically connect the p-type semiconductor layer 108 and the n-type semiconductor layer 104 to an external circuit.
In another embodiment, after removing the first metal oxide layer 214 and the second metallic compound layer 212, as shown in
Table 1 shows the driving voltage (VFD), the brightness (POD) and the simulated value of the brightness after packaging of Sample 1 (which is the semiconductor structure 100 subjected to the heat treatment process T after the first metal layer 202 and the second metal layer 204 formed thereon) and Sample 2 (which is the semiconductor structure 100 not subjected to the heat treatment process T and without the first metal layer 202 and the second metal layer 204 formed thereon).
As shown in Table 1, the driving voltage (VFD) of Sample 1 is similar to that of Sample 2. However, the brightness (POD) of Sample 1 is about 2.5% greater than that of Sample 2. Moreover, the simulated value of the brightness after packaging of Sample 1 is about 1.5% greater than that of Sample 2. Accordingly, the method of manufacturing a semiconductor device provided by the present embodiment can effectively improve the brightness compared to the method of manufacturing a semiconductor device without the first metal layer 202 and the second metal layer 204 formed on the semiconductor structure 100 and without performing the heat treatment process.
Table 2 shows the driving voltage (VFD) and the brightness (POD) of Sample 3 (in which the heat treatment process T is performed before the mesa etching process) and Sample 4 (in which the heat treatment process T is performed after the mesa etching process). As shown in Table 2, the brightness of Sample 3 is slightly greater than that of Sample 4 by about 0.15%. Moreover, the driving voltage (VFD) of Sample 3 is significantly lower than that of Sample 4 by 0.08V. Accordingly, the method of manufacturing a semiconductor device in which the heat treatment process T is performed before the mesa etching process can provide lower driving voltage compared to the method of manufacturing a semiconductor device in which the heat treatment process T is performed after the mesa etching process.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102148949 | Dec 2013 | TW | national |
