BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a first cross-sectional view of a semiconductor device according to a related art;
FIG. 2 is a second cross-sectional view of a semiconductor device according to a related art;
FIGS. 3A to 3C are first cross-sectional views showing a semiconductor device in a diffusion process according to the present invention;
FIGS. 4A to 4C are second cross-sectional views showing the semiconductor device in the diffusion process according to the present invention;
FIGS. 5A to 5C are third cross-sectional views showing the semiconductor device in the diffusion process according to the present invention;
FIGS. 6A to 6C are fourth cross-sectional views showing the semiconductor device in the diffusion process according to the present invention; and
FIGS. 7A to 7C are fifth cross-sectional views showing the semiconductor device in the diffusion process according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
A method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 3 to 7. FIGS. 3 to 7 are cross-sectional views showing principal steps of the method of manufacturing a semiconductor device. The left side diagram with the alphabetic suffix “A” of each figure is a cross-sectional view showing a grooved memory cell portion formed by a grooved NMOS transistor, the central diagram with the alphabetic suffix “B” is a cross-sectional view showing an ordinary NMOS transistor portion, and the right side diagram with alphabetic suffix “C” is a cross-sectional view showing an antifuse element portion. Description herein will be made principally of formation of a transistor relating to the nature of the present invention.
At first, an element isolation trench with a depth of 250 nm for example is formed in the surface of a P-type semiconductor substrate 101 by a commonly used method. The trench is then filled with an element isolation insulating film 102. As shown in FIG. 3A, a groove 103 for grooved NMOS transistor is then formed to a depth of 200 nm for example.
Subsequently, as shown in FIGS. 4A and 4C, the grooved memory cell portion and the antifuse element portion are covered with a resist 104. Further, the substrate surface of the NMOS transistor portion is selectively channel-doped for adjustment of threshold voltage (Vt) of the NMOS transistor. Boron is implanted at a dose of 2e12 cm−2 at 20 keV, for example, to form a P-type channel doped region 105, as shown in FIG. 4B.
Then, as shown in FIGS. 5A through 5C, a gate oxide film 106 having a thickness of 7 nm for example is formed. When two types of gate oxide films, namely thin-film and thick-film gate oxide films are used, it is desirable to use a thin-film gate oxide film for the antifuse element portion, and a thick-film gate oxide film for the grooved NMOS transistor. Further, a phosphorus doped polysilicon film having a thickness of 100 nm and an impurity concentration of 2e20 cm−3 for example is formed as a gate electrode 107.
Next, as shown in FIGS. 6A through 6C, ion implantation is conducted through a phosphorus doped polysilicon film to provide a channel-doped region and a source/drain diffusion region in the grooved memory cell portion and antifuse element portion. For this purpose, a resist pattern 108 is formed to cover the NMOS transistor portion while leaving the grooved memory cell portion and antifuse element portion open. Thereafter, boron is implanted at a dose of 5e12 cm−2 at 70 keV, for example. This boron implantation forms a second P-type channel doped region 109 in the grooved memory cell portion for control of threshold voltage (Vt) of the grooved NMOS transistor, and also forms a second P-type channel doped region 109 in the antifuse element portion. The second P-type channel doped region 109 in the antifuse element portion is formed by only increasing the concentration of the P-type semiconductor substrate.
Further, phosphorus is implanted at a dose of 1e13 cm−2 at 80 keV, for example. This phosphorus implantation forms an N− diffusion layer 110 in the source/drain diffusion region of the grooved NMOS transistor and in the surface region of the P-type semiconductor substrate 101 of the antifuse element portion, as shown in FIGS. 6A and 6C. The surface region of the P-type semiconductor substrate 101 in the antifuse element portion is inverted to N type by this N− diffusion layer region 110, and is connected to a source/drain diffusion region to be described later with a low resistance. The boron implantation and the phosphorus implantation are conducted using the same resist pattern. The implantation energy and the dose amount are set such that the boron ions are implanted to a deep region from the surface of the P-type semiconductor substrate while the phosphorus ions are implanted to a shallow region from the surface of the P-type semiconductor substrate.
Subsequently, as shown in FIGS. 7A through 7C, the gate electrode 107 is patterned to a desired pattern. An N+ source/drain diffusion region 111 is formed in the transistor of each of the NMOS transistor portion and the antifuse element portion by a commonly used technique, as shown in FIGS. 7B and 7C. It should be noted that, in FIGS. 3 to 7, only the main points of the invention are illustrated for the purpose of simplification. For example, a tungsten film may be formed prior to the gate patterning to reduce the layer resistance of the gate electrode. Further, a side-wall structure may be employed, or an LDD structure may be employed as a source/drain structure.
The method of manufacturing a semiconductor device according to the present invention forms the N− diffusion layer to be the source/drain diffusion region of the grooved NMOS transistor simultaneously with the N− diffusion layer of the channel region directly below the gate of the antifuse element. The formation of the N− diffusion layer directly below the gate of the antifuse element ensures stable electrical connection between the gate electrode and the source/drain diffusion region even if the breakdown of the antifuse element caused by writing is small. Therefore, the writing to the antifuse element can be performed stably at a relatively low voltage. In addition, the simultaneous formation of the N− diffusion layers eliminates the need of increasing the number of process steps or the cost especially for formation of the antifuse element, and enables low-cost manufacture of the semiconductor device. Thus, according to the manufacture method of a semiconductor device of the present invention, an antifuse element having a stable writing characteristic and a semiconductor device having such an antifuse element can be obtained without involving increase in the number of process steps or in the cost.
Although the present invention has been described in its preferred embodiments with a certain degree of particularity, the present invention is not limited to these embodiments but may be otherwise variously modified without departing from the true scope and spirit of the invention. It should be understood that all such modifications fall within the scope of the invention. For example, a capacitative element may be used in place of the antifuse element used in the present invention. Since the channel region is of N-type, the capacitative element will function stably without gate electrode dependence.
Patent Application
20080090363
