BACKGROUND
Field of Invention
The present disclosure relates to a method of manufacturing a structure having anodized parts.
Description of Related Art
The statements in this section merely provide background information related to the present disclosure and do not necessarily constitute prior art.
Traditional display manufacturing is a standardized process set. In recent years, there are more and more new types of displays such as a micro light-emitting diode display, a mini light-emitting diode display, and a quantum dot light-emitting diode display . . . etc., which are promising to dominate the future display market, and thus new display manufacturing processes are waiting to be set up. There are many steps contained in a manufacturing process set in order to produce one display, and reducing one of the steps thereof can reduce the cost and enhance the efficiency.
SUMMARY
According to some embodiments of the present disclosure, a method of manufacturing a structure having anodized parts includes: forming a bottom metal pattern with a dielectric layer thereon on a substrate, in which the dielectric layer has at least one opening exposing the bottom metal pattern; forming a semiconductor layer to cover the dielectric layer; forming a first metal layer on the semiconductor layer; forming a second metal layer on the first metal layer; forming a mask layer on the second metal layer to expose a portion of a top surface of the second metal layer; etching the second metal layer through the mask layer until a top surface of the first metal layer is exposed, wherein an etch selectivity of the second metal layer and the first metal layer is greater than 2.0; anodizing the first metal layer through the mask layer to form an anodized segment; and removing the mask layer after the anodizing.
It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the disclosure as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
The disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
FIG. 1 is a flowchart of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure;
FIGS. 2A to 2L are schematic cross-sectional views of intermediate stages of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure;
FIG. 3 is a schematic cross-sectional view of a gate electrode before and after being anodized according to some embodiments of the present disclosure;
FIG. 4 is a partial top view of the structure shown in FIG. 2L according to some embodiments of the present disclosure;
FIG. 5A is another partial top view of the structure shown in FIG. 2L according to some embodiments of the present disclosure;
FIG. 5B is another partial top view of the structure shown in FIG. 2L according to some embodiments of the present disclosure;
FIG. 5C is another partial top view of the structure shown in FIG. 2L according to some embodiments of the present disclosure;
FIG. 6 is another partial top view of the structure shown in FIG. 2L according to some embodiments of the present disclosure;
FIG. 7 is a schematic diagram of a circuit according to some embodiments of the present disclosure;
FIGS. 8A to 8F are schematic cross-sectional views of intermediate stages of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure;
FIGS. 9A to 9C are schematic cross-sectional views of intermediate stages of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure.
FIGS. 10A to 10F are schematic cross-sectional views of intermediate stages of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure; and
FIGS. 11A to 11F are schematic cross-sectional views of intermediate stages of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure.
DETAILED DESCRIPTION
Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions, and processes, etc., in order to provide a thorough understanding of the present disclosure. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present disclosure. Reference throughout this specification to “one embodiment,” “an embodiment”, “some embodiments” or the like means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrase “in one embodiment,” “in an embodiment”, “according to some embodiments” or the like in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.
Reference is made to FIG. 1. FIG. 1 is a flowchart of a method of manufacturing a structure having multi metal layers according to some embodiments of the present disclosure. The method begins with step S101 in which a bottom metal pattern with a dielectric layer thereon is formed on a substrate, in which the dielectric layer has at least one opening exposing the bottom metal pattern. The method continues with step S102 in which a semiconductor layer is formed to cover the dielectric layer. The method continues with step S103 in which a first metal layer is formed on the semiconductor layer. The method continues with step S104 in which a second metal layer is formed on the first metal layer. The method continues with step S105 in which a mask layer is formed on the second metal layer to expose a portion of a top surface of the second metal layer. The method continues with step S106 in which the second metal layer is etched through the mask layer until a top surface of the first metal layer is exposed, in which an etch selectivity of the second metal layer and the first metal layer is greater than 2.0. The method continues with step S107 in which the first metal layer is anodized through the mask layer to form an anodized segment. The method continues with step S108 in which the mask layer is removed. While the method is illustrated and described below as a series of steps or events, it will be appreciated that the illustrated ordering of such steps or events are not to be interpreted in a limiting sense. For example, some steps may occur in different orders and/or concurrently with other steps or events apart from those illustrated and/or described herein. In addition, not all illustrated steps may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the steps depicted herein may be carried out in one or more separate steps and/or phases.
Reference is made to FIG. 2A. FIG. 2A is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. As shown in FIG. 2A, a bottom metal layer BM is formed on a substrate SUB, and a photoresist PR is formed on the bottom metal layer BM. An atomic ratio of aluminum in the bottom metal layer BM is greater than 50 wt %. A material of the photoresist PR is positive tone photoresist. First regions of the photoresist PR are exposed with a first exposure dose E1 of light. Second regions of the photoresist PR are exposed with a second exposure dose E2 of light which is smaller than the first exposure dose E1. Third regions of the photoresist PR are not exposed. In some embodiments, the photoresist PR may be exposed by UV light, but the present disclosure is not limited in this regard. In some embodiments, the photoresist PR may be exposed by using a gray-tone mask (or a half-tone mask). For example, the half-tone mask may include full exposed portions where the full intensity of light (i.e., the first exposure dose E1) would be transmitted, half tone portions where parts of the light (e.g., the second exposure dose E2, which may be 20% to 60% of the first exposure dose E1) would be transmitted, and full tone portions where the light would be perfectly blocked.
In some embodiments, an atomic ratio of aluminum in the bottom metal layer BM is greater than 50%, but the present disclosure is not limited in this regard.
Reference is made to FIG. 2B. FIG. 2B is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 2A may be sequentially followed by the intermediate stage shown in FIG. 2B. As shown in FIG. 2B, the exposed photoresist PR is then developed to form a first patterned photoresist PR1 (i.e., a mask layer). The first patterned photoresist PR1 has a first mask portion PR11, a second mask portion PR12, and a third mask portion PR13. The mask portions may be called photoresist zones. The third mask portion PR13 is thicker than the first mask portion PR11 and the second mask portion PR12. It can be seen that the regions of the photoresist PR exposed with the first exposure dose E1 will be entirely removed, the regions of the photoresist PR exposed with the second exposure dose E2 will be partially removed to form the first mask portion PR11 and the second mask portion PR12, and the regions of the photoresist PR not exposed will be originally remained to form the third mask portion PR13.
Reference is made to FIG. 2C. FIG. 2C is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 2B may be sequentially followed by the intermediate stage shown in FIG. 2C. As shown in FIG. 2C, the bottom metal layer BM is etched through the first patterned photoresist PR1 to form a bottom metal pattern BP. The bottom metal pattern BP includes a gate electrode GE, a lower metal pattern LP, and a lower metal electrode LE that are respectively covered by the first mask portion PR11, the second mask portion PR12, and the third mask portion PR13.
In some embodiments, a wet etching process may be performed to etch the bottom metal layer BM. In some embodiments, a PAN etchant (a mixture of phosphoric acid, acetic acid, nitric acid, and water) may be used in the wet etching process. For example, a mixing ratio of phosphoric acid, acetic acid, nitric acid, and water may be 16:1:1:2, but the present disclosure is not limited in this regard. In some other embodiments, hydrogen peroxide and sulfuric acid may be used in the wet etching process.
In some embodiments, a dry etching process may be performed to etch the bottom metal layer BM. For example, the dry etching process may be an ECCP (Enhanced Capacitance Coupled Plasma) process using, for example, Cl2 and BCl3, but the present disclosure is not limited in this regard.
Reference is made to FIG. 2D. FIG. 2D is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 2C may be sequentially followed by the intermediate stage shown in FIG. 2D. As shown in FIG. 2D, the first mask portion PR11 and the second mask portion PR12 are removed to expose the top surfaces of the gate electrode GE and the lower metal pattern LP. In some embodiments, an ashing process is performed to the first mask portion PR11, the second mask portion PR12, and the third mask portion PR13 until the first mask portion PR11 and the second mask portion PR12 are entirely removed and the third mask portion PR13 still covers the top surface of the lower metal electrode LE. In some embodiments, oxygen plasma is used in the ashing process to perform the erosion of the first mask portion PR11, the second mask portion PR12, and the third mask portion PR13.
Reference is made to FIG. 2E. FIG. 2E is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 2D may be sequentially followed by the intermediate stage shown in FIG. 2E. As shown in FIG. 2E, the bottom metal pattern BP is anodized. The gate electrode GE, the lower metal pattern LP, and the lower metal electrode LE are partially anodized after the anodizing and thus have anodized parts GI (i.e., anodic oxide). The anodized part GI of the anodized gate electrode GE serves as a gate insulator. The anodized lower metal electrode LE has a surface portion S1 that is unanodized and in contact with the third mask portion PR13.
In some embodiments, the etched bottom metal layer BM is anodized to reach a termination voltage. The gate electrode GE has a thickness T1 (e.g., a vertical length of the gate electrode GE in FIG. 2D) and a width W1 (e.g., a lateral length of the gate electrode GE in FIG. 2D) before being anodized, and the termination voltage is less than a smallest one of the thickness T1 and the width W1 in nm divided by 0.9 nm-V−1. In this way, the etched bottom metal layer BM will not be fully anodized and leave conductive parts.
In some embodiments, the width W1 of the gate electrode GE is greater than the thickness T1 of the gate electrode GE, but the disclosure is not limited in this regard.
In some embodiments, the termination voltage that the etched bottom metal layer BM is anodized to reach is greater than 10 Volt and smaller than 500 Volt. It should be pointed out that if the etched bottom metal layer BM is anodized to reach a termination voltage greater than 500 Volt, the thickness of the anodized parts GI of the etched bottom metal layer BM (e.g., the anodized part GI of the gate electrode GE) may be too thick and result in high operation voltage of thin-film transistors.
In some embodiments, the etched bottom metal layer BM is anodized by applying a constant current greater than 0.5 mA/cm2.
In some embodiments, the etched bottom metal layer BM is anodized until the termination voltage is reached and kept for at least 300 seconds. It makes more uniform thickness of the anodized parts GI of the etched bottom metal layer BM.
In some embodiments, an annealing process may be performed to the anodized bottom metal layer BM. In this way, the resistance of the anodized bottom metal layer BM (e.g., the anodized part GI of the anodized gate electrode GE) to a second wet etching process (if any) can be increased. In some embodiments, an annealing temperature used in the annealing process is greater than 150° C., but the disclosure is not limited in this regard.
In some embodiments, the etched bottom metal layer BM is anodized by using an electrolyte with a pH value between pH5 and pH8. It should be pointed out that if the pH value is smaller than pH5 or greater than pH8, there will be more pores in the anodized parts GI of the etched bottom metal layer BM.
In some embodiments, the etched bottom metal layer BM is anodized by using an electrolyte containing a content of water less than 45 wt %. In this way, the Hydrogen content in the anodized parts GI of the etched bottom metal layer BM can be small. The Hydrogen content may reduce the breakdown voltage of the gate insulator. Hydrogen sometimes affects the semiconductor layer A (introduced below) and reduces its stability.
In some embodiments, the etched bottom metal layer BM is anodized by using an electrolyte containing water, ethylene glycol, and ammonium tartrate. For example, the electrolyte may contain ethylene glycol of about 68.5 wt %, water of about 30 wt %, and ammonium tartrate of about 1.5 wt %, but the disclosure is not limited in this regard.
In some embodiments, the etched bottom metal layer BM is anodized at a temperature under 20° C. In this way, the anodized parts GI of the etched bottom metal layer BM will be denser and thus the quality can be improved.
Reference is made to FIG. 3. FIG. 3 is a schematic cross-sectional view of the gate electrode GE before and after being anodized according to some embodiments of the present disclosure. As shown in FIG. 3, in some embodiments, a thickness of the unanodized part of the anodized gate electrode GE is equal to or greater than 1/10 of a thickness of the gate electrode GE before the etched bottom metal layer BM is anodized. In this way, the resistance of the etched bottom metal layer BM will not be too large.
Reference is made to FIG. 2F. FIG. 2F is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 2E may be sequentially followed by the intermediate stage shown in FIG. 2F. As shown in FIG. 2F, the third mask portion PR13 is removed to expose the surface portion S1 of the lower metal electrode LE that is unanodized.
Reference is made to FIG. 2G. FIG. 2G is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 2F may be sequentially followed by the intermediate stage shown in FIG. 2G. As shown in FIG. 2G, a semiconductor layer A is deposited on the anodized bottom metal layer BM to cover the gate electrode GE, the lower metal pattern LP, and the lower metal electrode LE, such that the gate electrode GE, the lower metal pattern LP, and the lower metal electrode LE are in contact with the semiconductor layer A.
In some embodiments, the semiconductor layer A is an oxide semiconductor layer. In addition, the semiconductor layer A includes at least one element of aluminum, gallium, indium, zinc, tin, and zirconium, but the disclosure is not limited in this regard. In some other embodiments, the semiconductor layer A includes MoS2.
In some embodiments, a thickness of the semiconductor layer A is smaller than 100 nm. In this regard, the back channel leakage may be reduced in certain circumstances.
In some embodiments, the semiconductor layer A may be deposited by a PVD (Physical Vapor Deposition) process or a CVD (Chemical Vapor Deposition) process.
In some embodiments, the semiconductor layer A may be a multi-layer structure containing different compositions. For example, the semiconductor layer A may be a double-layer structure including IZO (indium gallium zinc oxide) and IGZTO (indium gallium zinc tin oxide), but the disclosure is not limited in this regard. In this way, the channel mobility can be improved.
As shown in FIG. 2G, a first metal layer M1 is deposited on the semiconductor layer A, and a second metal layer M2 is deposited on the first metal layer M1. It should be pointed out that a surface of the first metal layer M1 in contact with the semiconductor layer A contains metal that can be anodized (e.g., aluminum). A second patterned photoresist PR2 (i.e., a mask layer) is formed on the first metal layer M1. The formation method of the second patterned photoresist PR2 may be the same as or similar to that of the first patterned photoresist PR1, so the formation of the second patterned photoresist PR2 can be referred to the description about FIGS. 2A and 2B and will not be repeated here. The second patterned photoresist PR2 has a first hollow portion H1 exposing a portion of a top surface of the second metal layer M2.
In some embodiments, an atomic ratio of aluminum in the first metal layer M1 is greater than 50%, but the present disclosure is not limited in this regard.
In some embodiments, first metal layer M1 further contains at least one rare earth element, but the present disclosure is not limited in this regard. In some embodiments, first metal layer M1 further contains zirconium, silicon, or tungsten, but the present disclosure is not limited in this regard. In some embodiments, first metal layer M1 further contains valve metals, but the present disclosure is not limited in this regard.
In some embodiments, an atomic ratio of copper in the second metal layer M2 is greater than 40%, but the present disclosure is not limited in this regard.
In some embodiments, the step of depositing the semiconductor layer A, the step of depositing the first metal layer M1, and the step of depositing the second metal layer M2 are performed continuously in vacuum. That is, the semiconductor layer A does not come into contact with the atmosphere before the first metal layer M1 and the second metal layer M2 are deposited. In some other embodiments, the step of depositing the semiconductor layer A, the step of depositing the first metal layer M1, and the step of depositing the second metal layer M2 are performed in chambers with transferring in vacuum. In this way, the oxide semiconductor layer A can be prevented from contacting with air.
Reference is made to FIG. 2H. FIG. 2H is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 2G may be sequentially followed by the intermediate stage shown in FIG. 2H. As shown in FIG. 2H, the second metal layer M2 is etched through the second patterned photoresist PR2 until a surface portion S2 of a top surface of the first metal layer M1 is exposed, in which an etch selectivity of the second metal layer M2 and the first metal layer M1 is greater than 2.0. Reference is made to FIG. 2I. FIG. 2I is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 2H may be sequentially followed by the intermediate stage shown in FIG. 2I. As shown in FIG. 2I with reference to FIG. 2G, the surface portion S2 of the first metal layer M1 is anodized through the second patterned photoresist PR2 until the first metal layer M1 has an anodized segment C (i.e., anodic oxide) extended from the surface portion S2 of the first metal layer M1 to a side of the first metal layer M1 facing the semiconductor layer A. As mentioned above, the surface of the first metal layer M1 in contact with the semiconductor layer A contains metal that can be anodized (e.g., aluminum), so that the first metal layer M1 can be anodized to extend the anodized segment C to the side of the first metal layer M1 facing the semiconductor layer A.
In some embodiments, the surface portion S2 of the first metal layer M1 is anodized to reach a termination voltage. The first metal layer M1 has a thickness T2 before being anodized, as shown in FIG. 2G. The termination voltage is greater than the thickness T2 in nm divided by 1.5 nm-V−1. In this way, it can be ensured that the anodized segment C can reach the side of the first metal layer M1 facing the semiconductor layer A.
In some embodiments, as shown in FIG. 2I, the semiconductor layer A has an active area A1 and an inactive area A2. The active area A1 is covered by and in contact with the anodized segment C. The active area A1 may be defined by a vertical projection of the anodized segment C projected on the semiconductor layer A. The inactive area A2 is covered by and in contact with the other conductive segment of the first metal layer M1. In order to reduce the contact resistance of the inactive area A2 relative to the first metal layer M1, an annealing process may be performed to make the inactive area A2 react with aluminum in the first metal layer M1. Aluminum increases the oxygen vacancies of the inactive area A2 of the semiconductor layer A. The annealing process also improves the stability of the active area A1 of the semiconductor layer A.
Reference is made to FIG. 2J. FIG. 2J is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 2I may be sequentially followed by the intermediate stage shown in FIG. 2J. As shown in FIG. 2J, second hollow portions H2 are formed in the second patterned photoresist PR2. In some embodiments, an ashing process is performed to the second patterned photoresist PR2 until the second hollow portions H2 are formed to expose portions of the second metal layer M2. In some embodiments, oxygen plasma is used in the ashing process to perform the erosion of the second patterned photoresist PR2.
Reference is made to FIG. 2K. FIG. 2K is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 2J may be sequentially followed by the intermediate stage shown in FIG. 2K. As shown in FIG. 2K, the second metal layer M2 and the first metal layer M1 are sequentially etched through the second hollow portions H2, such that a first upper metal pattern UP1 and a second upper metal pattern UP2 are formed from the first metal layer M1 and the second metal layer M2. The semiconductor layer A is then etched. The first upper metal pattern UP1 is above the anodized gate electrode GE and has a drain electrode DE and a source electrode SE. The drain electrode DE and the source electrode SE are connected to the anodized segment C and electrically isolated from each other by the anodized segment C. The anodized segment C serves as a channel protect structure. The second upper metal pattern UP2 is above the lower metal pattern LP and the lower metal electrode LE. The second upper metal pattern UP2 forms a metal cross over structure with the lower metal pattern LP. In addition, the second upper metal pattern UP2 forms a contact structure with the lower metal electrode LE.
In some embodiments, an etch selectivity of the first metal layer M1 and the anodized segment C in the step of etching the first metal layer M1 (as shown in FIG. 2K) is higher than 2.0. In some embodiments, an etch selectivity of the second metal layer M2 and the anodized segment C in the step of etching the second metal layer M2 (as shown in FIG. 2K) is higher than 2.0.
In some embodiments, a wet etching process may be performed to etch the first metal layer M1. In some embodiments, a PAN etchant (a mixture of phosphoric acid, acetic acid, nitric acid, and water) may be used in the wet etching process. For example, a mixing ratio of phosphoric acid, acetic acid, nitric acid, and water may be 16:1:1:2, but the present disclosure is not limited in this regard.
In some embodiments, the first metal layer M1 and the semiconductor layer A may be etched by using different etchants, respectively. For example, in an embodiment where the semiconductor layer A is an oxide semiconductor layer and includes tin, the PAN etchant may be not easy to etch the semiconductor layer A. To etch this kind of semiconductor layer A, oxalic acid or formic acid may be used, but the present disclosure is not limited in this regard.
Reference is made to FIG. 2L. FIG. 2L is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 2K may be sequentially followed by the intermediate stage shown in FIG. 2L. As shown in FIG. 2L, the second patterned photoresist PR2 is removed to expose the first upper metal pattern UP1 and the second upper metal pattern UP2.
Reference is made to FIGS. 4, 5A, and 6. FIGS. 4, 5A, and 6 are partial top views of the structure shown in FIG. 2L according to some embodiments of the present disclosure. In detail, FIG. 4 is a partial schematic diagram showing the anodized gate electrode GE (covered by the anodized part GI) and the first upper metal pattern UP1. FIG. 5A is a partial schematic diagram showing the anodized lower metal electrode LE (covered by the anodized part GI and exposing the surface portion S1) and the second upper metal pattern UP2 that form the aforementioned contact structure. FIG. 6 is a partial schematic diagram showing the anodized lower metal pattern LP (covered by the anodized part GI) and the second upper metal pattern UP2 that form the aforementioned metal cross over structure.
Reference is made to FIG. 5B. FIG. 5B is another partial top view of the structure shown in FIG. 2L according to some embodiments of the present disclosure. As shown in FIG. 5B, the surface portion S1 of the lower metal electrode LE exposed by the anodized part GI has a smaller area than that shown in FIG. 5A.
Reference is made to FIG. 5C. FIG. 5C is another partial top view of the structure shown in FIG. 2L according to some embodiments of the present disclosure. As shown in FIG. 5C, both the surface portion S1 of the lower metal electrode LE exposed by the anodized part GI and the second upper metal pattern UP2 covering the lower metal electrode LE are extended along the lower metal electrode LE.
Reference is made to FIGS. 6 and 7. FIG. 7 is a schematic diagram of a circuit according to some embodiments of the present disclosure. It should be pointed out that the metal cross over structure (formed by the second upper metal pattern UP2 and the lower metal pattern LP) in FIG. 6 may correspond to the structure indicated by the dotted circle in FIG. 7 (i.e., the metal cross over structure formed by a first metal line ML1 and a second metal line ML2).
Accordingly, it can be seen that the method of manufacturing a structure having anodized parts of the embodiments as shown in FIGS. 2A to 2L only uses two sets of PEP (Photo Engraving Process). Therefore, the manufacturing cost can be significantly reduced and the manufacturing efficiency can be effectively enhanced.
Reference is made to FIG. 8A. FIG. 8A is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. In some embodiments, the intermediate stage shown in FIG. 2F may be directly followed by the intermediate stage shown in FIG. 8A. As shown in FIG. 8A, a semiconductor layer A is deposited on the anodized bottom metal layer BM, a first metal layer M1 is deposited on the semiconductor layer A, and a second metal layer M2 is deposited on the first metal layer M1. The deposition methods of the semiconductor layer A, the first metal layer M1, and the second metal layer M2 may be the same as or similar to those of the embodiments as shown in FIG. 2G, so they can be referred to the description about FIG. 2G and will not be repeated here.
As shown in FIG. 8A, a second patterned photoresist PR2 is formed on the second metal layer M2. The formation method of the second patterned photoresist PR2 may be the same as or similar to that of the first patterned photoresist PR1, so the formation of the second patterned photoresist PR2 can be referred to the description about FIGS. 2A and 2B and will not be repeated here. The second patterned photoresist PR2 has first hollow portions H1 exposing portions of the first metal layer M1.
Reference is made to FIG. 8B. FIG. 8B is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 8A may be sequentially followed by the intermediate stage shown in FIG. 8B. As shown in FIG. 8B, the second metal layer M2 and the first metal layer M1 are sequentially etched through the second patterned photoresist PR2 to form a first upper metal pattern UP1 and a second upper metal pattern UP2. The first upper metal pattern UP1 is above the anodized gate electrode GE and covered by a first mask portion PR21 of the second patterned photoresist PR2. The second upper metal pattern UP2 is above the anodized lower metal pattern LP and the anodized lower metal electrode LE and covered by a second mask portion PR22 of the second patterned photoresist PR2.
Reference is made to FIG. 8C. FIG. 8C is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 8B may be sequentially followed by the intermediate stage shown in FIG. 8C. As shown in FIG. 8C, a part of the first mask portion PR21 of the second patterned photoresist PR2 is removed to form a second hollow portion H2. The second hollow portion H2 exposes a portion of the first upper metal pattern UP1. In some embodiments, an ashing process is performed to the second patterned photoresist PR2 until the second hollow portion H2 is formed to expose the portion of the first upper metal pattern UP1. In some embodiments, oxygen plasma is used in the ashing process to perform the erosion of the second patterned photoresist PR2.
Reference is made to FIG. 8D. FIG. 8D is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 8C may be sequentially followed by the intermediate stage shown in FIG. 8D. As shown in FIG. 8D, the second metal layer M2 is etched through the second patterned photoresist PR2 until a surface portion S2 of a top surface of the first metal layer M1 is exposed, in which an etch selectivity of the second metal layer M2 and the first metal layer M1 is greater than 2.0.
Reference is made to FIG. 8E. FIG. 8E is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 8D may be sequentially followed by the intermediate stage shown in FIG. 8E. As shown in FIG. 8E, the surface portion S2 of the first metal layer M1 is anodized until the first metal layer M1 has a drain electrode DE, a source electrode SE, and an anodized segment C connected between and electrically isolating the drain electrode DE and the source electrode SE. The anodized segment C serves as a channel protect structure.
In some embodiments, the bottom metal pattern BP is anodized to reach a termination voltage. The gate electrode GE has a thickness T1 (e.g., a vertical length of the gate electrode GE in FIG. 2D) before being anodized, and the termination voltage is less than the thickness T1 in nm divided by 0.9 nm-V−1. In this way, the etched bottom metal layer BM will not be fully anodized and leave conductive parts.
In some embodiments, the surface portion S2 of the first metal layer M1 is anodized to reach a termination voltage. The first upper metal pattern UP1 has a width W2 and a thickness T3 before being anodized, as shown in FIG. 8C. The termination voltage is greater than a smallest one of the width W2 and the thickness T2 in nm divided by 1.5 nm-V−1. In this way, it can be ensured that the anodized segment C can reach the side of the first upper metal pattern UP1 facing the semiconductor layer A, as shown in FIG. 8E.
Reference is made to FIG. 8F. FIG. 8F is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 8E may be sequentially followed by the intermediate stage shown in FIG. 8F. As shown in FIG. 8F, the second patterned photoresist PR2 is removed to expose the first upper metal pattern UP1 and the second upper metal pattern UP2.
Reference is made to FIG. 9A. FIG. 9A is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. In some embodiments, the intermediate stage shown in FIG. 2F may be directly followed by the intermediate stage shown in FIG. 9A. As shown in FIG. 9A, a semiconductor layer A is deposited on the bottom metal pattern BP. A first metal layer M1 is deposited on the semiconductor layer A. A second metal layer M2 is deposited on the first metal layer M1. A second patterned photoresist PR2 is formed on the second metal layer M2. In other words, the second metal layer M2 in FIG. 2G is replaced by the second metal layer M2 in FIG. 9A. As shown in FIG. 9A, the second metal layer M2 is a multi-layer structure. Specifically, the second metal layer M2 includes a first sub-layer SL1 and a second sub-layer SL2. The first sub-layer SL1 may contain molybdenum. The second sub-layer SL2 is stacked on the first sub-layer SL1. In addition, the second patterned photoresist PR2 has a first hollow portion H1 exposing a surface portion S3 of the second metal layer M2. The surface portion S3 is a portion of the top surface of the second sub-layer SL2 right above the gate electrode GE.
In some embodiments, the first sub-layer SL1 contains molybdenum, titanium, or an alloy thereof, but the disclosure is not limited in this regard. The first sub-layer SL1 which contains molybdenum can prevent the first metal layer M1 which contains aluminum from occurring hillock in the subsequent high temperature process.
In some embodiments, the second sub-layer SL2 contains copper, but the disclosure is not limited in this regard. In some embodiments, an atomic ratio of copper in the second sub-layer SL2 is greater than 40%, but the disclosure is not limited in this regard.
In some embodiments, one of the first sub-layer SL1 and the second sub-layer SL2 may be omitted.
In some embodiments, the step of depositing the semiconductor layer A as shown in FIG. 9A is the same as or similar to that as shown in FIG. 2G, so it can be referred to the description about FIG. 2G and will not be repeated here. In some embodiments, the step of forming the second patterned photoresist PR2 as shown in FIG. 9A is the same as or similar to that as shown in FIG. 2G, so it can be referred to the description about FIG. 2G and will not be repeated here.
Reference is made to FIG. 9B. FIG. 9B is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 9A may be sequentially followed by the intermediate stage shown in FIG. 9B. As shown in FIG. 9B, the second sub-layer SL2 and the first sub-layer SL1 in the first hollow portion H1 are selectively etched relative to the first metal layer M1 to expose a surface portion S2 of the first metal layer M1 in the first hollow portion H1.
In some embodiments, the first sub-layer SL1 which contains molybdenum may be etched by using hydrogen peroxide and citric acid solution.
In some embodiments, an etch selectivity of the first sub-layer SL1 and the first metal layer M1 in the selectively etching is higher than 2.0.
In some embodiments, the first sub-layer SL1 may be omitted. That is, the second metal layer M2 may only include the second sub-layer SL2 which contains copper.
Reference is made to FIG. 9C. FIG. 9C is a schematic cross-sectional view of an intermediate stage of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. The intermediate stage shown in FIG. 9B may be sequentially followed by the intermediate stage shown in FIG. 9C. As shown in FIG. 9C with reference to FIG. 9B, the surface portion S2 of the first metal layer M1 exposed by the first hollow portion H1 is anodized through the second patterned photoresist PR2 until the first metal layer M1 has an anodized segment C extended from the surface portion of the first metal layer M1 exposed by the first hollow portion H1 to a side of the first metal layer M1 facing the semiconductor layer A. In some embodiments, the step of anodizing the first metal layer M1 as shown in FIG. 9C is the same as or similar to that as shown in FIG. 2I, so it can be referred to the description about FIG. 2I and will not be repeated here.
In some embodiments, the first metal layer M1 as shown in FIG. 8A may be replaced by the first metal layer M1 as shown in FIG. 9A, and after the first metal layer M1 is exposed by the second hollow portion H2 of the second patterned photoresist PR2 as shown in FIG. 8C, the second sub-layer SL2 and the first sub-layer SL1 in the second hollow portion H2 can be selectively etched relative to the first metal layer M1 to expose the first metal layer M1. Afterwards, the step of anodizing the first metal layer M1 (as the intermediate stage shown in FIG. 8E) and the step of removing the second patterned photoresist PR2 can be sequentially performed.
Reference is made to FIGS. 10A to 10F. FIGS. 10A to 10F are schematic cross-sectional views of intermediate stages of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. It is noted that the intermediate stages shown in FIGS. 2A to 2F may be replaced by the intermediate stages shown in FIGS. 10A to 10F. As shown in FIG. 10A, a first patterned photoresist PR1 (i.e., a mask layer) is formed on the bottom metal layer BM.
The intermediate stage shown in FIG. 10A may be sequentially followed by the intermediate stage shown in FIG. 10B. As shown in FIG. 10B, the bottom metal layer BM is etched through the first patterned photoresist PR1 to form a bottom metal pattern BP. The bottom metal pattern BP includes a gate electrode GE, a lower metal pattern LP, and a lower metal electrode LE. In some embodiments, the step of etching the bottom metal layer BM as shown in FIG. 10B is the same as or similar to that as shown in FIG. 2C, so it can be referred to the description about FIG. 2C and will not be repeated here.
The intermediate stage shown in FIG. 10B may be sequentially followed by the intermediate stage shown in FIG. 10C. As shown in FIG. 10C, the first patterned photoresist PR1 is removed.
The intermediate stage shown in FIG. 10C may be sequentially followed by the intermediate stage shown in FIG. 10D. As shown in FIG. 10D, a second patterned photoresist PR2 is formed on the top surface of the lower metal electrode LE.
The intermediate stage shown in FIG. 10D may be sequentially followed by the intermediate stage shown in FIG. 10E. As shown in FIG. 10E, the bottom metal pattern BP is anodized. The anodized lower metal electrode LE has a surface portion S1 that is unanodized and in contact with the second patterned photoresist PR2. In some embodiments, the step of anodizing the bottom metal pattern BP as shown in FIG. 10E is the same as or similar to that as shown in FIG. 2E, so it can be referred to the description about FIG. 2E and will not be repeated here.
The intermediate stage shown in FIG. 10E may be sequentially followed by the intermediate stage shown in FIG. 10F. As shown in FIG. 10F, the second patterned photoresist PR2 is removed to expose the surface portion S1 of the lower metal electrode LE that is unanodized.
Reference is made to FIGS. 11A to 11F. FIGS. 11A to 11F are schematic cross-sectional views of intermediate stages of a method of manufacturing a structure having anodized parts according to some embodiments of the present disclosure. It is noted that the intermediate stages shown in FIGS. 2A to 2F may be replaced by the intermediate stages shown in FIGS. 11A to 11F. In some embodiments, the steps as shown in FIGS. 11A to 11C are the same as or similar to those as shown in FIGS. 10A to 10C, so it can be referred to the description about FIGS. 10A to 10C and will not be repeated here.
The intermediate stage shown in FIG. 11C may be sequentially followed by the intermediate stage shown in FIG. 11D. As shown in FIG. 10D, a dielectric film DF is deposited on the bottom metal pattern BP, and a second patterned photoresist PR2 is formed on the dielectric film DF. The dielectric film DF covers the gate electrode GE, the lower metal pattern LP, and the lower metal electrode LE. A portion of the dielectric film DF above the lower metal electrode LE is exposed by the second patterned photoresist PR2.
The intermediate stage shown in FIG. 11D may be sequentially followed by the intermediate stage shown in FIG. 11E. As shown in FIG. 11E, the portion of the dielectric film DF above the lower metal electrode LE is etched through the second patterned photoresist PR2 until a surface portion S1 of the lower metal electrode LE is exposed.
The intermediate stage shown in FIG. 11E may be sequentially followed by the intermediate stage shown in FIG. 11F. As shown in FIG. 11F, the second patterned photoresist PR2 is removed.
According to the foregoing recitations of the embodiments of the disclosure, it can be seen that the method of manufacturing a TFT of the present disclosure only uses two sets of PEP. Therefore, the manufacturing cost can be significantly reduced and the manufacturing efficiency can be effectively enhanced.
Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.
Patent Application
20250188638
