The present invention relates to symmetric memory arrays generally and to contact areas therein in particular.
Symmetric memory arrays are known in the art. One type of symmetric memory array, shown in
Contacts 18, in contact areas 16, bring power to bit lines 10, typically by connecting between metal lines (not shown) and bit lines 10. Contacts 18 typically are large and thus, cannot fit within the standard spacing of word lines 12. In one type of array, each contact area 16 occupies the space of one word line 12 and the spacing to both of its neighboring word lines.
The following patents and patent applications describe a dual polysilicon process (DPP) for the NROM cell: US 2004/0157393 to Hwang describes a manufacturing process for a non-volatile memory cell of the SONOS type which attempts to reduce or minimize the undesirable effects of small dimension components. U.S. Pat. No. 6,686,242 B2 to Willer et al. describes an NROM cell that they claim can be implemented within a 4F2 area. U.S. Ser. No. 11/247,733, assigned to the common assignees of the present invention, describes a further process for manufacturing NROM cells.
In the DPP process, a first polysilicon layer is deposited in columns between which bit lines 10 are implanted. Bit line oxides (not shown) are deposited in the spaces between first polysilicon columns and may be formed as blocked columns covering bit lines 10. Word lines 12 may then be deposited as a second polysilicon layer, cutting the columns of the first polysilicon layer into islands between bit lines 10. For NROM cells, an ONO layer (also not shown) is laid down over the entire array prior to deposition of the polysilicon layers and it may be removed from above bit lines 10.
A common practice for NROM arrays is to silicide the second polysilicon layer in order to reduce the resistance of the word lines. This involves silicidation of the second polysilicon layer after its deposition but prior to patterning of the word lines. Tungsten silicide is typically used for this purpose. The double layer is then cut into the word lines.
Self-Aligned Silicidation, known as “Salicide”, is an alternative method for silicidation of word lines. In this process, word lines are first patterned, after which the second polysilicon layer is etched, to generate the word lines, and oxide spacers are then created on the array. After that has been completed, the array is silicided. The silicidation self-aligns to the second polysilicon word lines. Note that, in the word line areas, oxide spacers are not typically generated. Instead, the oxide for the spacers completely fills the gap between word lines. For the Salicide process, Copper or Nickel silicide are typically used.
It is know in industry that, during salicidation of the polysilicon, exposed silicon will be salicided as well. This is a particular problem in the area of the bit line contacts. If the bit line area is not protected, with an STI (Silicon Trench Isolation) or another dielectric layer, salicidation of this layer will create a leakage path.
NROM cells are described in many patents, for example in U.S. Pat. No. 6,649,972, assigned to the common assignees of the present invention, whose disclosure is incorporated herein. Where applicable, descriptions involving NROM are intended specifically to include related oxide-nitride technologies, including SONOS (Silicon-Oxide-Nitride-Oxide-Silicon), MNOS (Metal-Nitride-Oxide-Silicon), MONOS (Metal-Oxide-Nitride-Oxide-Silicon) and the like used for NVM devices. Further description of NROM and related technologies may be found at “Non Volatile Memory Technology”, 2005 published by Saiftin Semiconductor and materials presented at and through http://siliconnexus.com, “Design Considerations in Scaled SONOS Nonvolatile Memory Devices” found at:
http://klabs.org/richcontent/MemoryContent/nvmt_symp/nvmts—2000/presentations/bu_white_sonos_lehigh_univ.pdf,
“SONOS Nonvolatile Semiconductor Memories for Space and Military Applications” found at:
http://klabs.org/richcontent/MemoryContent/nvmt_symp/nvmts—2000/papers/adams_d.pdf,
“Philips Research—Technologies—Embedded Nonvolatile Memories” found at:
http://research.philips.com/technologies/ics/nvmemories/index.html, and
“Semiconductor Memory: Non-Volatile Memory (NVM)” found at:
http://ece.nus.edu.sg/stfpage/elezhucx/myweb/NVM.pdf, all of which are incorporated by reference herein in their entirety.
There is provided, in accordance with a preferred embodiment of the present invention, a non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area, an oxide-nitride-oxide (ONO) layer within the word line areas and at least partially within the contact areas and protective elements, generated when spacers are formed in the periphery area, to protect silicon under the ONO layer in the contact areas.
Moreover, in accordance with a preferred embodiment of the present invention, the protective elements are formed of one of the following: oxide, nitride and oxide-nitride-oxide.
Further, in accordance with a preferred embodiment of the present invention, the spacers are formed of liners of 50-150 nm thick.
Still further, in accordance with a preferred embodiment of the present invention, the word line areas include either Salicided or silicided word lines. The Salicided word lines may be Salicided with Copper or Nickel silicide and the silicided word lines may be silicided with Tungsten suicide.
There is also provided, in accordance with a preferred embodiment of the present invention, a non-volatile memory device including a plurality of word line areas each separated from its neighbor by a contact area and bit line oxides whose height is at least a quarter of the distance between neighboring bit line oxides.
Additionally, in accordance with a preferred embodiment of the present invention, the device also includes protective elements at least between the bit line oxides in the contact area.
Still further, in accordance with a preferred embodiment of the present invention, the word line areas include either Salicided or silicided word lines. The Salicided word lines may be Salicided with Copper or Nickel silicide and the silicided word lines may be silicided with Tungsten silicide.
The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:
It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention.
Applicants have realized that the Salicide process has drawbacks in the contact areas of a symmetric memory array.
Reference is now made to
Applicants have realized that the Salicide process may cause serious damage in contact areas 20 because the etching of one or both of the spacers and the word lines (1st and 2nd polysilicon layers) may over etch ONO layer 28B. The word line etch may remove the top oxide of the ONO layer 28 while the spacer etch may remove at least the nitride layer if not also the* some or all of the bottom oxide.
If ONO layer 28B is damaged, then the silicon, labeled 31, underneath ONO layer 28B (
Applicants have realized that the step which produces spacers 30 and 32 is the same step which generates spacers in the complementary metal oxide semiconductor (CMOS) periphery (not shown) of the memory array.
The etch back is designed to stop once the liner 40 is removed from on top of polysilicon gates 41. Since word lines 24 (
It will be appreciated that liner 40 covers the chip, which includes both the periphery and the memory array. As can be seen in
Applicants have realized that raising the height of bit line oxides 26 may provide the tall elements. This is shown in
In the prior art, bit line oxides 26 (
Typically, the liner thickness is determined by the standard processes of the* CMOS periphery. In the present invention, the ratio of the height of bit line oxides 36 to the distance D between bit lines depends on the liner thickness and on any process steps that may partially partial etch of bit line oxides 36.
It will be appreciated that the process described hereinabove is not limited to implementation with the Salicide process. Protecting silicon 31 in the contact area is important irrespective of the cause of the damage. Thus, increasing the height of the bit lines may be useful for word lines silicided by the standard silicide process and/or as a general protection for the silicon 31 in contact areas 20.
While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.
This application claims benefit from U.S. Provisional Patent Application No. 60/714,852, filed Sep. 8, 2005, which is hereby incorporated in its entirety by reference.
Number | Date | Country | |
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60714852 | Sep 2005 | US |