Patent Application
20060051903
The present invention relates to a method of manufacturing a thin film semiconductor device and a thin film semiconductor device, and particularly to a method of manufacturing a thin film semiconductor device and a thin film semiconductor device which are suitable for manufacturing a display drive panel in a flat panel display.
A flat panel display of a liquid crystal display, an organic EL display or the like is provided with thin film transistors (TFTs) as drive elements for pixel electrodes. Among these components, the poly-Si.TFT using polycrystalline silicon (poly-Si) as a semiconductor thin film is paid attention to on the ground that it can form a drive circuit, it enables incorporation of a high-function circuit in a panel and, hence, it enables conversion into the so-called system-on-glass structure. Meanwhile, in order to realize the formation of poly-Si.TFTs not on a quartz substrate but on an inexpensive glass substrate, the so-called low-temperature poly-Si process in which the manufacturing process temperature is suppressed to 600° C. or below has been developed.
In the manufacture of poly-Si ·TFTs by the low-temperature poly-Si process, there has been used a method in which a film of amorphous silicon (a-Si) is formed as a semiconductor thin film on a glass or other insulating substrate by a plasma CVD process and the film is polycrystallized by treating it through irradiation with an intense beam of excimer laser or the like (laser anneal). It is well known, however, that the poly-Si obtained in this manner contains a multiplicity of defective levels arising from the uncoupled bonds (dangling bonds) of silicon at grain boundaries or in crystal grains, and, due to the electric charges trapped in the defective levels, a grain boundary potential barrier is formed against the carriers, such as electrons and holes, running through the inside of crystals. Where the potential barrier is high, the carrier mobility is lowered, resulting in that high-performance TFTs cannot be formed.
In order to prevent such a deterioration of the performance of TFT, there has been well known the so-called hydrogenation anneal in which the dangling bonds are terminated by bonding hydrogen or the like thereto so as to reduce the defective levels. As the hydrogenation anneal, there have been known a method in whih a silicon oxide film, a silicon nitride film or the like is built up on the polycrystalline silicon film and thermal annealing is conducted to diffuse the hydrogen present in the silicon oxide or silicon nitride film into the polycrystalline silicon, and a method in which the substrate is exposed to a hydrogen plasma to achieve hydrogeneration. However, of the hydrogen introduced into the film by such a method, the hydrogen atoms contributing to termination of the dangling bonds are very few, and most of the dangling bonds are left unterminated. Besides, the Si—H bond energy is about 3.0 eV, and the hydrogen bonds would be lost upon the thermal anneal at 400 to 500° C.
In view of this, there has been proposed a process of conducting a heat treatment in a moisture atmosphere (water vapor anneal) to bond oxygen to the dangling bonds and thereby to lower the defective levels. The bond energy of Si—O bond is about 4.7 eV, which is higher than that of Si—H bond, so that the Si—O bond is stable against processes and hot carriers at a higher temperature. Particularly, since the water vapor anneal permits a batch process, it is more suited to mass production as compared with the oxygen plasma process, and it promises a higher oxidation rate as compared with the oxygen anneal process.
The manufacture of TFTs by application of the water vapor anneal is conducted as follows. First, a silicon oxide film is formed in the state of covering a polycrystallized semiconductor thin film. Next, water vapor anneal is conducted to bond oxygen to the dangling bonds in the semiconductor thin film constituting the TFTs, thereby terminating the dangling bonds. Thereafter, the silicon oxide film and the semiconductor thin film are patterned to achieve device isolation, then a gate insulation film is formed in the state of covering the patterns, and gate electrodes are formed. In the TFTs formed following such a manufacturing procedure, the silicon oxide film having been subjected to the water vapor anneal is also used as part of the gate insulation film (see Japanese Patent Laid-open No. 2002-151526); and Japanese Patent Laid-open No. 2002-208707).
Further, the silicon oxide film formed by a low-temperature process is low in film denseness, and the atoms constituting the film are liable to be present in the state of having dangling bonds, which may serve as electric charges in the film in some cases. In addition, in the silicon oxide film, silicon nitride film and the like, unreacted Si is left in the film, to serve as fixed electric charges in some cases. Further, damages arising from electrostatic discharge breaking out during or after the formation of the device are liable to be present in the film, and the damages are also liable to remain as fixed electric charges in the insulation film. When the fixed electric charges are left in the gate insulation film or layer insulation film in TFT, they cause a shift of the threshold voltage (Vth) of the TFT, leading to an increase in the leak current of the TFT; this will appear as defects of phosphor in the case of pixel TFTs, and as defects in circuit operation in the case of TFTs for peripheral drive circuits. In the worst case, dielectric breakdown occurs due to electrostatic discharge, leading to defects in insulation between input terminals, for example. In the cases of liquid crystal display, organic EL display and the like, devices are formed on a glass substrate which is an insulator and, therefore, are more liable to be electrostatically charged, as compared with semiconductor devices formed on an Si wafer; in addition, the devices on glass substrate are weak in electrostatic endurance of insulation film, so that electrostatically caused defects are frequently generated in the devices.
In order to obviate the above-mentioned problems, there has been proposed a method in which, after formation of a silicon oxide film on a semiconductor thin film, water vapor annealing is conducted in a pressurized atmosphere so as to contrive a higher denseness, like in the plasma CVD process (see Japanese Patent Laid-open No. 2003-188182).
However, the thin film transistor formed by applying the production method using the water vapor anneal as above-mentioned has the following problem. The carrier mobility in the semiconductor thin film is secured, but, particularly in the case of n-channel TFT, the threshold voltage (Vth) would be abnormally shifted in the minus direction.
In addition, even in the case of conducting water vapor anneal with the same timing as that in the conventional hydrogeneration anneal, an abnormal shift of the threshold voltage (Vth) is generated. Specifically, an abnormal shift of threshold voltage (Vth) in the minus direction is generated in the n-channel TFT in the same manner as above, even in the case where, as shown in
Further, in the manufacture of a thin film semiconductor device by a low-temperature process, it may be necessary for the layer insulation film covering the thin film transistor to be formed at a low temperature; however, as has been described above, a layer insulation film formed by a low-temperature process is low in film denseness. Therefore, as above-mentioned, fixed electric charges would remain in the layer insulation film to cause various defects, leading to a lowering in the reliability of the thin film semiconductor device.
Thus, there is a need for providing a method of manufacturing a thin film semiconductor device and a thin film semiconductor device which includes thin film transistors capable of securing the TFT threshold voltage irrespectively of conduction type and which is high in reliability.
In order to fulfill the above need, according to an embodiment of the present invention, there is provided a method of manufacturing a thin film transistor which includes the following steps. First, in a first step, a thin film transistor is formed on a substrate. Next, in a second step, a layer insulation film containing no hydroxyl group (—OH group) in at least a film constituting a lowermost layer is formed on the substrate in the state of covering the thin film transistor. Thereafter, in a third step, a heat treatment is conducted in a moisture atmosphere to link oxygen to dangling bonds present in a semiconductor thin film constituting the thin film transistor.
According to the manufacturing method as above, the layer insulation film containing no —OH group in the lowermost layer film is formed in the state of covering the thin film transistor (TFT). Therefore, in the subsequent heat treatment in the moisture atmosphere (water vapor anneal), oxygen is linked to the dangling bonds in the semiconductor thin film constituting the thin film transistor to thereby terminate the dangling bonds with oxygen or hydrogen, without inducing any influence of the —OH groups in the layer insulation film on the thin film transistor. Moreover, the layer insulation film is also subjected to the water vapor anneal, so that an enhancement of the denseness of the layer insulation film is contrived.
Here,
As is clear from
Therefore, it is seen that a thin film transistor free of the Vth shift to the minus side even in the n-channel can be obtained, also in the case where the layer insulation film containing no —OH group in at least the lowermost layer film is formed in the state of covering the thin film transistor (TFT) and thereafter the water vapor anneal for terminating the dangling bonds with oxygen (partly hydrogen) stably and securely is conducted, as in the manufacturing method according to an embodiment of the present invention.
Incidentally, the Vth shift dependent on the Si—OH bond concentration as described referring to
The reason why the large minus shift of Vth is observed only for the n-channel TFT device is considered as follows. As for the behavior of hydrogen atoms in silicon, it has been reported, as for example shown in Physical Review B, Volume 41, (1990), p.12354 and the like, that a P—H derivative is dissociated under the crystal field in silicon in the manner of P—H→P++H− . . . (1), to generate stable H— ions, which are moved in silicon due to the presence of an electric field. On the other hand, the Si—OH bond present solely cannot find the mate with which the hydrogen atom is to be coupled, and an annealing at a high temperature of 1000° C. or above is needed for complete dissociation of hydrogen from the OH bonds; in the n-channel thin film transistor, however, P atoms are present in the source/drain regions as the mate with which H is to be coupled, so that a P—H derivative is easily produced. It is considered that, once the P—H bonds are formed, H− ions are generated in silicon according to the formula (1), and the H− ions are moved into the channel under the drain field of the thin film transistor, so that negative charges are accumulated in the channel, resulting in the Vth shift in the minus direction. On the other hand, the impurity atoms contained in the source/drain regions in the p-channel thin film transistor are atoms of boron (B), and no Group V element (e.g., P) that is stably coupled with H is present (or little, if present), so that there is little influence on the Vth shift.
In addition, according to another embodiment of the present invention, there is provided a first thin film semiconductor device including a thin film transistor containing a Group V element in a source region and a drain region of a semiconductor thin film containing silicon as a main constituent, and a layer insulation film provided on a substrate in the state of covering the thin film transistor, wherein at least the lowermost layer of the layer insulation film includes a silicon nitride film.
In the first thin film semiconductor device as above, at least the lowermost layer of the layer insulation film covering the thin film transistor includes the silicon nitride film, whereby it is ensured that the lowermost layer of the layer insulation film contains few —OH groups, and a thin film transistor with little Vth shift as above-mentioned is obtained.
According to a further embodiment of the present invention, there is provided a second thin film semiconductor device including a thin film transistor containing a Group V element in a source region and a drain region of a semiconductor thin film containing silicon as a main constituent, and a layer insulation film provided on a substrate in the state of covering the thin film transistor, wherein the layer insulation film has been made denser by a heat treatment in a moisture atmosphere.
As has been described above, according to the method of manufacturing a thin film semiconductor device according to an embodiment of the present invention, a thin film transistor with a stable Vth irrespective of conduction type can be obtained, without abnormal shift of Vth of the n-channel thin film transistor, even in the case where a heat treatment in a moisture atmosphere is conducted. Moreover, it is possible to contrive an enhancement of the denseness of the layer insulation film covering the thin film transistor. Therefore, it is possible to enhance the electrostatic endurance of the layer insulation film and to prevent electrostatically caused defects from being generated. As a result, it is possible to contrive an enhancement of the reliability of the thin film semiconductor device.
In addition, according to the first thin film semiconductor device according to another embodiment of the present invention, at least the lowermost layer of the layer insulation film covering the thin film transistor includes a silicon nitride film, whereby it is possible to stabilize the threshold (Vth) of the n-channel TFT and to contrive a higher reliability.
Further, according to the second thin film semiconductor device according to a further embodiment of the present invention, the layer insulation film covering the thin film transistor has been made denser by a heat treatment in a moisture atmosphere, whereby it is possible to prevent defects or troubles from being generated by the influence of fixed electric charges in the layer insulation film and to contrive a higher reliability.
Now, some embodiments of the present invention will be described in detail below, based on the drawings. Incidentally, here, before description of the embodiments of the manufacturing method, the configuration of a treating apparatus used in the embodiments will be described, and then first to fourth embodiments will be described.
The treating chamber 3 is a quartz pipe whose inside surface is formed of quartz, and is so configured as to prevent metals from mixing in. In the treating chamber 3, a stage 3a on which a plurality of substrates to be treated (not shown) such as glass substrates and silicon substrates can be mounted is disposed so that the substrates to be treated can be treated in a batch treatment mode.
The heater 4 is provided so as to surround the periphery of the treating chamber 3, and is so configured that the inside of the treating chamber 3 can be maintained at a temperature of 300 to 700° C.
The pressure rise line 5 is connected to an air supply source, has a pressure reducing valve RV, a flowmeter FM, and a valve V, and is so designed as to introduce air into the pressure vessel 2 by opening and closing the valve V. On the other hand, the pressure reduction line 6 has a pressure reducing valve V, and can reduce the pressure inside the pressure valve 2 by exhausting.
At an upstream portion in the case of referring to the treating chamber 3 side as the downstream side, the gas supply line 7 is branched into an inert gas supply line 7a for supplying nitrogen gas (N2) or the like, a water supply line 7b, and a treating gas supply line for supplying a treating gas (oxygen or dinitrogen monoxide or the like) (not shown). In addition, the gas supply line 7 is provided, at a downstream portion for discharging the treating gas into the treating chamber 3, with a heater 7c for heating the treating gas to a temperature equivalent to the temperature inside the treating chamber 3.
The inert gas supply line 7a has a supply source of the inert gas such as nitrogen (N2), a pressure reducing valve RV, a flowmeter FM, and a valve V, and is so configured that the inert gas can be supplied into the treating chamber 3 by opening and closing the valve V, to provide a predetermined treating gas atmosphere in the treating chamber 3, and the pressure inside the treating chamber 3 can be raised to a value of 0.1 to 5 MPa. The water supply line 7b has a pump P and a valve V, and is so configured as to pump up water from a water source, to supply the water to the heater 7c by opening and closing the valve V, to evaporate the water by the heater 7c, and to supply water vapor into the treating chamber 3. The treating gas supply line (not shown here) is so configured that each of treating gases such as oxygen and dinitrogen monoxide is supplied from a pressure cylinder of the treating gas into the treating chamber 3.
In the treating apparatus 1 configured as above, a high-pressure water vapor atmosphere can be maintained inside the treating chamber 3, and a heat treatment in the high-pressure water vapor atmosphere (i.e., high-pressure water vapor anneal) can be applied to the substrates to be treated which are contained in the treating chamber 3. For example, when the high-pressure water vapor anneal is applied to a silicon oxide film formed on a substrate surface by a plasma CVD process or the like, unoxidized silicon remaining in silicon oxide can be oxidized, whereby an enhancement of the denseness of an oxide film and a reduction of fixed electric charges in the film can be contrived, so that an enhancement of the film quality of the oxide film can be contrived. On the other hand, the concentration of Si—OH bonds in the oxide film is increased by the water vapor anneal. Incidentally, the Si—OH bond concentration tends to be higher as the water vapor anneal temperature is lower.
The sectional step views in
First, as shown in
By use of a film forming method such as plasma CVD process and LPCVD process, a silicon nitride (SiNx) film 32 as a buffer layer is formed on the substrate 31, and a silicon oxide (SiOx) film 33 is formed in a film thickness of about 50 to 400 nm. In the case where the silicon nitride film 32 and the silicon oxide film 33 are formed by the plasma CVD process, first, the silicon nitride film 32 is formed by using an inorganic silane gas (SiH4, Si2H6 or the like) and ammonia gas (NH3) are used as film forming gases. The silicon oxide film 33 is formed by using the inorganic silane gas and oxygen (O2) or dinitrogen monoxide (N2O) as film forming gases. During the film formation, the substrate temperature is maintained at about 450° C.
After the above, a semiconductor thin film 34 composed of silicon or germanium or a laminate thereof is formed on the silicon oxide film 33 by plasma CVD process, reactive thermal CVD process, vacuum CVD process, or normal pressure CVD process. Here, the semiconductor thin film 34 has a film thickness of 10 to 100 nm, preferably 40 nm.
Thereafter, if necessary, dehydrogenation anneal for removing hydrogen remaining in the semiconductor thin film 34 is conducted.
Next, as shown in
Next, as shown in
Thereafter, as shown in
Next, as shown in
Thereafter, as shown in
Next, as shown in
Further, as shown in
After the above, as shown in
Next, as shown in
Incidentally, the layer insulation film 44 may be a laminate film having a silicon oxide film further formed in a film thickness of 100 to 200 nm on the silicon nitride film. In such a laminate structure, the lowermost layer of the layer insulation film 44 is composed of the silicon nitride film containing no —OH group in the film. It should be noted in this case that the formation of the silicon oxide film as the upper layer is preferably conducted by such a film forming method that hydroxyl groups will not be contained in the film. Here, the film forming method such that hydroxyl groups will not be contained in the film is, for example, an electron cyclotron resonance (ECR) CVD process or a magnetron sputtering process.
In addition, the layer insulation film 44 may be a layer of silicon oxynitride (SiNxOy). Silicon oxynitride can be obtained by use of plasma decomposition of a mixture of an inorganic silane gas (SiH4, Si2H6 or the like) and dinitrogen monoxide supplied in a predetermined flow rate ratio, and the amount of —OH bonds in the film can be extremely low and in the above-mentioned range.
Incidentally, in the case where a silicon oxide film is formed as the layer insulation film 44, the amount of Si—OH bonds (—OH group concentration) in the silicon oxide film can be determined by the Fourier-transform infrared spectroscopy (FT-IR), for example; in this method, when the OH bond amount is below the detection limit, the film can be deemed as containing no Si—OH bond.
After the layer insulation film 44 with the lowermost layer containing no —OH group is formed, an activation annealing treatment is conducted by a method appropriately selected from laser anneal, lamp anneal, furnace anneal and the like, for activating the impurity introduced into the semiconductor thin film 34.
Next, as shown in
Here, whether the layer insulation film 44 has been made denser can be confirmed from the fact that the half width of a peak appearing in the absorption spectrum in a specified wavelength region upon FT-IR is narrower than that for a film not subjected to the water vapor anneal. For example, in the case of silicon oxide, the FT-IR spectrum has an absorption peak in the vicinity of a wavelength of 1050 to 1090 cm−1, and the denseness of the silicon oxide film can be judged by the magnitude of the peak half-width. Besides, in the case of a silicon oxide film, the film can be judged as a comparatively coarse film when the half-width of the absorption peak appearing in the vicinity of 1050 to 1090 cm−1 is greater than 90 cm−1, and the film can be judged as a dense film when the half-width is smaller than 80 cm−.
Next, as shown in
Thereafter, a flattening insulation film 48 formed of an acrylic organic resin, for example, is formed by coating in a film thickness of about 1 μm, and the flattening insulation film 48 is provided with contact holes 49 reaching the wiring electrodes 47. Then, pixel electrodes 50 connected to the wiring electrodes 47 via the contact holes 49 are formed on the flattening insulation film 48. The pixel electrodes 50 are formed, for example, by sputtering a film of ITO (Indium Tin Oxide) as a transparent conductive material, followed by patterning. Besides, where the pixel electrodes 50 are formed of ITO, the pixel electrodes 50 are annealed in a nitrogen atmosphere at a temperature of about 220° C. for 30 min. By this, the thin film semiconductor device 51 to be a display drive panel is completed.
In the thin film semiconductor device 51 produced as above, as has been described above using
Particularly, since the high-pressure water vapor anneal can be conducted without any influence of the —OH groups in the layer insulation film 44 on the TFTs 40 and 43 as above-mentioned, an abnormal shift of the threshold (Vth) of the nTFT 40 is obviated, and it is possible to obtain the TFTs 40 and 43 with stable Vth irrespectively of the conduction type. In addition, since the gate insulation film 35 is patterned into the shape laminated on the gate electrodes 36 and the portions of the gate insulation film 35 overlapping with the semiconductor thin film 34 in other areas are removed as has been described above referring to
In addition, since the high-pressure water vapor anneal is applied also to the layer insulation film 44 as above-mentioned, an enhancement of the denseness of the layer insulation film 44 can be contrived. This ensures that the electrostatic endurance of the layer insulation film 44 can be enhanced, and electrostatically caused defects can be prevented from being generated.
As a result of the foregoing, an enhancement of the reliability of the thin film semiconductor device 51 can be contrived. In addition, with the thin film semiconductor device 51 used as a display drive panel, dispersion of TFT device characteristics in the substrate 31 is reduced, which can greatly contribute to realization of a system display liquid crystal panel, organic EL panel or the like in which high-function circuits are integrated on a display panel.
Besides, since the water vapor anneal is conducted in the method of terminating the dangling bonds in the semiconductor thin film 34 with oxygen or hydrogen, a high through-put can be achieved.
Now, the method of manufacturing a semiconductor thin film according to a second embodiment will be described below referring to the sectional step diagrams shown in
First, following the same procedure as described using
Incidentally, in the step shown in
Next, as shown in
Thereafter, an activation annealing treatment is conducted by a method appropriately selected from laser anneal, lamp anneal, furnace anneal and the like, for activating the impurity introduced into the semiconductor thin film 34.
Thereafter, the step shown in 5B is carried out by the same “high-pressure water vapor anneal” as described above using
Next, the step shown in
Even by such a manufacturing method, the layer insulation film 44′ containing no —OH group in the lowermost layer film formed of silicon nitride is formed in the state of covering the TFTs 40 and 43, and, thereafter, high-pressure water vapor anneal is conducted, as described referring to
Particularly, since the formation of the silicon oxide film constituting the gate insulation film 35 and the formation of the silicon oxide film constituting the upper layer of the layer insulation film 44′ are conducted by use of the ECR-CVD process or magnetron sputtering process, these films contain few —OH groups, so that the shift of the threshold (Vth) of the nTFTs 40 can be suppressed further securely.
Now, the method of manufacturing a semiconductor thin film according to a third embodiment will be described below referring to sectional step diagrams shown in
Specifically, after the formation of nTFTs 40 and pTFTs 43 in the same manner as in the second embodiment, as shown in
Thereafter, an activation annealing treatment is conducted by a method appropriately selected from laser anneal, lamp anneal, furnace anneal and the like, for activating the impurity introduced into the semiconductor thin film 34.
Thereafter, the step shown in
Next, the step shown in
In such a manufacturing method, as has been described above using
Now, the method of manufacturing a semiconductor thin film according to a fourth embodiment will be described below referring to sectional step diagrams shown in
First, as shown in
Next, as shown in
Next, if necessary, following to the formation of the semiconductor thin film 76, rapid temperature elevation by irradiation with energy E of pulse excimer laser, Xe arc lamp or the like or by blowing a high-temperature N2 gas is applied to the semiconductor thin film 76, thereby promoting crystallization of the semiconductor thin film 76. This step is conducted in the same manner as described above referring to
Thereafter, as shown in
Next, as shown in
Next, as shown in
Thereafter, as shown in
Next, as shown in
Next, an activation annealing treatment for the impurity introduced into the semiconductor thin film 76 is conducted. The activation annealing treatment is carried out by a method appropriately selected from laser anneal, lamp anneal, furnace anneal and the like.
Thereafter, as shown in
Next, the step shown in
After the above, the same steps as described above using
Even in such a manufacturing method, like in the manufacturing method according to the first embodiment described above, as has been described using
The results of measurement of characteristics of 28 independent TFTs formed in a matrix pattern on a glass substrate are shown in
As is clear from
In contrast, as is clear from
In addition, as shown in
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| P2004-227470 | Aug 2004 | JP | national |
