Patent Application
20080085001
The foregoing summary, as well as the following detailed description of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustration, there are shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.
In the drawings:
The connecting means C1 may be, for example, contact pads provided to co-operate with contact pads formed on the host processor HP2. Alternatively, the host processor HP2 is coupled to a contactless communication interface circuit to communicate with the controller NFCC.
In
According to one preferred embodiment, the smart card 1 into which the host processor HP2 is integrated comprises a contactless component CLC with units similar to those of the component NFCR1 described above. Thus, the component CLC particularly includes a controller NFCC and an interface circuit CLINT, for sending/receiving contactless data, equipped with an antenna circuit ACT1, but no hard-wire communication interfaces INT1, INT2. The processor HP2 is removable from the smart card 1 for insertion into the chipset, where it is connected to the component NFCR2 by the connecting means C1.
The processor HP2 and the component CLC have previously been customized and thus each store a secret data K1, K2. The secret data K1, K2 stored respectively by the processor HP2 and the component NFCR2 are linked to each other by a relation that it is possible to check. This relation may simply be an equality relation or any other relation, such as an encryption function. Therefore, the data K1 stored by the host processor may be a private key and the data K2 stored by the component NFCR2 may be a public key of a pair of asymmetric enciphering keys.
The host processor HP1 is, for example, the main processor of the chipset into which the component NFCR2 is embedded. The component NFCR2 and the processor HP2 each may be a secure processor, i.e., comprising the classic encryption and authentication circuits of secure processors. The processor HP1 is not secure. The chipset may also comprise a third host processor HP3.
For example, the chipset may be a mobile telephone. The processor HP1 is the main processor of the telephone, the processor HP2 is a chip of a SIM card, and the processor HP3 is a bank card chip.
The processor HP2 is removed from the card 1 into which the component CLC is integrated, and inserted into the chipset, where it is connected to the component NFCR2 as shown by
When the host processor HP2 is connected to the component NFCR2 and every time the chipset is initialized, an authentication sequence is triggered.
During a first step S1, the processor HP2 sends an authentication request to the controller NFCC. In the next step S2, the controller NFCC answers the request by supplying a random number “Rnd Nb” and information “NFC Info.” relating to the NFC component (for example a serial number, a manufacturing date, a software version number, or the like). In the next step S3, the processor HP2 uses the secret data K1 as an enciphering key to cipher the random number received, and possibly any other information received, and transmits the ciphered data to the controller NFCC.
In the next step S4, the controller NFCC deciphers the data received using the secret data K2 as an enciphering key. If the deciphered data corresponds to the data sent in step S2, the secret data K1, K2 are indeed linked by a predefined relation, and the controller NFCC considers the processor HP2 to be authenticated. If so, the controller NFCC transmits a message to the processor HP2 notifying it that it has been authenticated and containing a session key SK. The session key SK is, for example, a random number.
If the deciphering of the ciphered information does not supply the information it transmitted to the processor HP2, the controller NFCC considers the processor HP2 as not authenticated, and refuses any other communication with the processor HP2.
If the processor HP2 has been authenticated, the controller NFCC and the processor HP2 may exchange information, such as configuration and management information, in a ciphered form using the session key SK as a symmetric enciphering key (steps S5 and S6). For example, a routing table stored in the non-volatile memory of the controller NFCC can thus be transferred into the processor HP2 in order to be used in another NFC chipset (for example, another mobile telephone). Alternatively, the information stored in the non-volatile memory of the controller NFCC can also be transferred into the component CLC in order to be used in another NFC chipset.
The information transmitted in step S2 can also be ciphered by the controller NFCC using the secret data K2, the result of the enciphering being transmitted with the non-ciphered information. The processor HP2 may then decipher the result of the enciphering using the secret data K1 and check the identity between the information received and the result of the deciphering. In this way, the processor HP2 can check whether the controller NFCC has the secret data K2 corresponding to the secret data K1, and thus authenticate the controller NFCC. If the host processor HP2 does not authenticate the controller NFC, it refuses to communicate with the controller NFC.
If the processor HP2 installed in the NFC chipset is replaced with a new host processor, the new host processor will not have the session key SK and will not therefore be able to communicate with the controller NFCC, unless the component CLC corresponding to the new host processor is available and unless the execution of the authentication procedure described above with reference to
The interface CLINT and the ports INT1, INT2, INT3 each have a parallel-input input buffer BUF1 and a parallel-output output buffer BUF2 that is write-accessible and respectively read-accessible via the data bus and the address bus. The exchange of data forming the routing commands or the data frames between the host processors HP1, HP2, HP3 and the controller NFCC or the interface CLINT is thus performed by data blocks of the size of the buffers BUF1, BUF2, and is paced by the controller NFCC.
Each host processor HP1, HP2 includes at least four software layers, in an ascending order of level. A lowest level layer Hardware Management Layer (HWML) manages the operation of the hardware elements enabling the host processors HP1, P2 to exchange data with the controller NFCC. This is, for example, the management layer of the UART interface for the processor HP1 and the management layer of the ISO7816 interface for the processor HP2. An Interface Protocol Layer (INTPL) layer manages the protocol of the communication ports INT1, INT2, INT3. This is, for example, the management layer of the UART protocol for the processor HP1 and the management layer of the ISO7816 protocol for the processor HP2. An HCIL layer manages the HCI protocol according to one embodiment, i.e., manages the creation of a communication channel. The HCIL layer rests on the INTPL and HWML layers that are practically transparent to the HCIL layer. A high level Application layer APL manages the RFID applications such as those represented in
In a substantially similar manner, the controller NFCC includes the following software layers. Two HWML1 and INTPL layers are included and are of the same type as the HWML and INTPL layers present in the host processors HP1, HP2. For the sake of simplicity of the diagram, these layers are represented in the processor NFCC, but in reality are located in the ports INT1 and INT2, which are considered to be part of the controller, as well as the buses ADB, DTB, CTB. Indeed, the processing of the UART and 7816 protocols is performed here in the ports INT1, INT2, which make their input and output buffers BUF1, BUF2 available to the controller via the buses ADB, DTB, CTB. Another low level layer HWML2 enables the controller to write to the buffers BUF1 and to read the buffers BUF2, via the buses ADB, DTB, CTB, by breaking down the data frames or the commands into data blocks of the same size as the buffers. An HCI-ADMIN-L layer or HCI protocol administration layer communicates with the HCIL layers of the host processors HP1, HP2 as routing administrator. A CLINTCL (Contactless Interface Control Layer) layer manages the interface CLINT and indicates thereto the mode into which the interface CLINT must put itself and the protocol to be used to send data in a contactless communication channel. The CLINTCL layer also controls the interface CLINT in contactless data receipt mode and cyclically asks the interface CLINT to perform a scan of the modes (“reader” mode, “emulation” mode and “device” mode) and to search for incoming data in each mode. The interface CLINT thus emits a magnetic field at regular intervals to poll any contactless cards or tags (or other portable objects operating in a contactless manner) that could be present within its polling range. The interface CLINT also puts itself at regular intervals into a listening mode (“emulation” mode) to detect whether a reader in active mode is sending polling messages. An optional APL layer can itself manage applications, just like the host processors HP1, HP2. Indeed, although it has not been described until now, applications can also be managed by the NFC component itself.
Finally, the interface CLINT includes the following software layers. On the controller NFCC side, a HWML low level layer equivalent to the HWML2 layer of the controller NFCC manages the data buffers BUF1, BUF2 via the buses ADB, DTB, CTB. An HCIL layer (as indicated above) makes the interface CLINT compatible with the HCI protocol. On the antenna circuit ACT side, Contactless Protocol Layer (CLPTL) and Mode Control Layer (MCL) layers control or process the electric signals applied to the antenna circuit ACT or received thereby.
It will be understood by those skilled in the art that various alternative embodiments are possible. Thus, an NFC chipset may comprise a single host processor and an NFC component, where execution of applications are controlled.
Furthermore, other authentication procedures than the one described with reference to
Moreover, the secret data K2 may be transmitted to the component NFCR2 in other manners than by a contactless link. Thus, the secret data K2 can be transmitted by optically reading an optical code (e.g., a bar code) or by keyboarding the secret data K2 captured appearing on the card from which the SIM card (host processor HP2) is removed. The host processor HP1, which is connected to the image sensor or to the keyboard and to the controller NFCC, then transmits the secret data K2 captured to the controller NFC. In the case of the optical code, the processor HP1 also translates the optical code to obtain the secret data K2. These alternative embodiments are perfectly suited to the current architecture of mobile telephones, which have a keyboard and generally an image sensor.
It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 0608764 | Oct 2006 | FR | national |
