Claims
- 1. A method of producing a non-volatile semiconductor memory device, the method including a step of forming memory cells each having a duplicate gate structure in which a floating gate and a control gate are stacked, said step of forming memory cells comprising:a first step of forming a first gate insulation film, a first conductive film and an insulation film in due order on a semiconductor substrate of a first conductivity type; a second step of forming first and second semiconductor regions of a second conductivity type opposite to said first conductivity type on said semiconductor substrate so as to be self-aligned with side walls of said first conductive film; a third step of forming conductive side-wall portions on said side walls of said first conductive film and side walls of said insulation film; a fourth step of removing said insulation film; a fifth step of doping an impurity into said first conductive film and said conductive side-wall portions to thereby form said floating gate; a sixth step of forming a second gate insulation film and a second conductive film in due order so as to cover said floating gate; a seventh step of, after doping an impurity in said second conductive film, forming a mask of a shape matching a shape of a resultant floating gate on said second conductive film; and an eighth step of removing said second conductive film, said second gate insulation film, said conductive side-wall portions and said first gate insulation film along said mask, to thereby form said resultant floating gate and said control gate.
- 2. The method as set forth in claim 1, further comprising, before said second step, a step of forming a third semiconductor region having a lower impurity concentration than that of said first semiconductor region under the first semiconductor region.
- 3. The method as set forth in claim 2, further comprising, after said fifth step, a step of rounding top portions of said conductive side-wall portions.
- 4. The method as set forth in claim 3, wherein said step of rounding top portions of said conductive side-wall portions is carried out by thermally oxidizing said conductive side-wall portions at a predetermined temperature.
- 5. The method as set forth in claim 4, wherein said predetermined temperature is set to be 950° C. or more.
- 6. The method as set forth in claim 3, wherein said conductive side-wall portions are formed to have a thickness of 200 nm or more.
- 7. The method as set forth in claim 2, wherein said conductive side-wall portions are formed to have a thickness ranging from 100 nm to 300 nm.
- 8. The method as set forth in claim 1, wherein said first conductive film and said conductive side-wall portions are formed by polysilicon films, and said second conductive film is formed by a polysilicon film.
- 9. The method as set forth in claim 1, wherein said first conductive film and said conductive side-wall portions are formed by polysilicon films, and said second conductive film has a polysilicon film and a metal layer or a metal reaction layer stacked one on the other.
- 10. The method as set forth in claim 1, wherein said first and second gate insulation films are both formed by oxide films.
- 11. The method as set forth in claim 1, wherein said first gate insulation film is formed by an oxide film and said second gate insulation film has a structure in which oxide films and nitride films are alternately stacked.
- 12. The method as set forth in claim 1, further comprising, before said first step, a step of forming a step portion in a gate's lengthwise direction in a region on said semiconductor substrate which corresponds to a portion where said first conductive film is formed.
Priority Claims (1)
Number |
Date |
Country |
Kind |
10-314458 |
Nov 1998 |
JP |
|
Parent Case Info
This application is a divisional of prior application Ser. No. 09/302,398 filed Apr. 30, 1999 now U.S. Pat. No. 6,172,394.
US Referenced Citations (11)
Non-Patent Literature Citations (1)
Entry |
Kitamura et al., “A Low Voltage Operating Flash Memory Cell with High Coupling Ratio Using Horned Floating Gate with Fine HSG”, IEEE Symposium on VLSI Technology Digest of Technical Papers, Jun. 9-11, 1998, pp. 104-105. |