Claims
- 1. A method producing a semiconductor memory device, comprising the steps of:
- (1) preparing a semiconductor substrate having a principal surface, said substrate having a memory cell region of a first conductivity type in which memory cells are to be formed and a peripheral circuit region in which a peripheral circuit is to be formed;
- (2) forming a first insulator film on said principal surface of said substrate in said memory cell region and said peripheral circuit region;
- (3) selectively forming a second insulator film having oxidation resistance on said first insulator film so that said second insulator film covers a first active region in said memory cell region and a second active region in said peripheral circuit region;
- (4) selectively introducing first impurities of the first conductivity type into said principal surface of said peripheral circuit region, without introducing said first impurities in the memory cell region, by using the second insulator film formed on said peripheral circuit region as a mask in order to form a first channel stopper region in said peripheral circuit region without introducing the first impurities in the memory cell region;
- (5) after the step of selectively introducing said first impurities, selectively forming third and fourth insulator films on the principal surface of said substrate in said memory cell region and said peripheral circuit region respectively by using said second insulator film as an oxidation resistance mask, said third and fourth insulator films being thicker than said first insulator film;
- (6) removing said second insulator film from the upper surface of said first insulator film;
- (7) after the step of selectively forming the third and fourth insulator films, introducing second impurities of the first conductivity type all over said memory cell region, through at least said third insulator film, thereby to form a second channel stopper region of the first conductivity type, in said memory cell region, extending under the third insulator film, and a barrier region of the first conductivity type extending under a first active region, said barrier region having a higher impurity concentration than that of said memory cell region;
- (8) forming a MISFET included in each of said memory cells in said first active region within said memory cell region; and
- (9) forming MISFETs in said second active region within said peripheral circuit region, said MISFETs being included in said peripheral circuit.
- 2. A method of producing a semiconductor memory device according to claim 1, wherein the step (7) of introducing said second impurities of the first conductivity type all over said memory cell region, includes the sub-steps of:
- (7') forming a mask over the peripheral circuit region; and
- (7") introducing the second impurities using said mask over the peripheral circuit region to prevent introduction of the second impurities into the peripheral circuit region.
- 3. A method of producing a semiconductor memory device according to claim 1, includes the further step of forming a capacitance element, included in each of said memory cells, in said memory cell region.
- 4. A method of producing a semiconductor memory device according to claim 1, wherein said first insulator film is a silicon oxide film, said second insulator film is a silicon nitride film, and said third and fourth insulator films are silicon oxide films.
- 5. A method of producing a semiconductor memory device according to claim 1, wherein said first conductivity type is p-type conductivity, and wherein said MISFET included in each of said memory cells is a n-type conductivity opposite to said first conductivity type.
- 6. A method of producing a semiconductor memory device according to claim 1, wherein said peripheral circuit includes at least a sense amplifier.
- 7. A method of producing a semiconductor memory device according to claim 1, wherein said barrier region is a region serving as a potential barrier against electron-hole pairs generated by .alpha.-rays entering the semiconductor substrate.
- 8. A method of producing a semiconductor memory device according to claim 1, wherein the plurality of memory cells include semiconductor regions provided in the semiconductor substrate, and wherein the barrier region is formed so as to extend beneath said semiconductor regions and to be spaced from the semiconductor regions.
- 9. A method of producing a semiconductor memory device according to claim 1, wherein the first impurities, in step (4), are introduced only into said principal surface of said peripheral circuit region.
- 10. A method of producing a semiconductor memory device according to claim 1, wherein the impurity of the first conductivity type is introduced all over said memory cell region, so as to simultaneously form said channel stopper region in said memory cell region and said barrier region.
- 11. A method of producing a semiconductor memory device, comprising the steps of:
- preparing a semiconductor substrate having a principal surface, said substrate having a memory cell region in which a plurality of memory cells are to be formed and a peripheral circuit region in which a peripheral circuit is to be formed, wherein said memory cell region includes first active regions of a first conductivity type and a first isolation region for isolating said first active regions from each other, wherein said peripheral circuit region includes second and third active regions and a second isolation region for isolating said second and third active regions from each other, the second active region having the first conductivity type, the third active region having a second conductivity type opposite to the first conductivity type;
- selectively introducing first impurities of the first conductivity type into the principal surface on said peripheral circuit region without introducing said first impurities into the memory cell region, in order to form a first channel stopper region in said second isolation region;
- after the step of selectively introducing said first impurities, selectively forming a first insulator film on the principal surface of said substrate at said first isolation region in said memory cell region and a second insulator film on the principal surface of said substrate in said peripheral circuit region, respectively, said first channel stopper region being disposed under said second insulator film;
- after the step of selectively forming the first and second insulator films, implanting second impurities of the first conductivity type into said memory cell region, through at least said first insulator film, to thereby form a second channel stopper region of the first conductivity type under said first insulator film and an impurity-introduced region of the first conductivity type under said first active regions, said impurity-introduced region being integrally formed with said second channel stopper region in said substrate and having a higher concentration than that of said first active regions; and
- forming first MISFETs of said memory cells in said first active regions, and forming second and third MISFETs of said peripheral circuit in said second and third active regions, respectively.
- 12. A method of producing a semiconductor memory device according to claim 11, wherein a depth of said impurity-introduced region is greater than a depth of said second channel stopper region.
- 13. A method of producing a semiconductor memory device according to claim 11, including the further step of forming a capacitance element, included in each of said memory cells, in said first active regions within said memory cell region.
- 14. A method of producing a semiconductor memory device according to claim 11, wherein the first conductivity type is p-type conductivity, and said first and second impurities of the first conductivity type are each p-type impurity.
- 15. A method of producing a semiconductor memory device according to claim 11, wherein the second channel stopper region is formed in contact with the first insulator film.
- 16. A method of producing a semiconductor memory device according to claim 15, wherein said impurity-introduced region is in the semiconductor substrate under said first active regions, spaced from said first insulator film.
- 17. A method of producing a semiconductor memory device according to claim 11, wherein said second impurities of the first conductivity type are implanted so as to simultaneously form second channel stopper region under said first insulator film and said impurity-introduced region.
- 18. A method of producing a semiconductor memory device according to claim 11, wherein said memory cells include first semiconductor regions, and wherein said impurity-introduced region is formed so as to be disposed under said first semiconductor regions and spaced from the first semiconductor regions.
- 19. A method of producing a semiconductor memory device according to claim 11, wherein a depth of an upper surface of the impurity-introduced region, from the principal surface of the substrate, is greater than a depth of an upper surface of the second channel stopper region.
- 20. A method of producing a semiconductor memory device according to claim 19, wherein a position of a peak impurity concentration of said impurity-introduced region is about 0.5 microns depth from the principal surface of said substrate.
- 21. A method of producing a semiconductor memory device according to claim 1, wherein each memory cell is a memory cell of a dynamic random access memory.
- 22. A method of manufacturing a semiconductor memory device, comprising the steps of:
- (a) preparing a semiconductor substrate having a main surface, said substrate having a memory cell region in which a plurality of memory cells are to be formed, and having a peripheral circuit region in which a peripheral circuit is to be formed, wherein said memory cell region includes first active regions of a first conductivity type and a first isolation region for isolating said first active regions from each other, wherein said peripheral circuit region includes second active regions and a second isolation region for isolating said second active regions each other;
- (b) selectively forming a mask film on said main surface of said substrate so that said mask film covers first active regions and said first isolation region in said memory cell region and said second active regions in said peripheral circuit region;
- (c) selectively introducing first impurities of said first conductivity type into said main surface of said substrate by using mask film as a mask, to form a first channel stopper region of said first conductivity type at said second isolation region in said peripheral circuit region;
- (d) after the step (c), selectively forming an isolation oxide film on said main surface of said substrate so that said isolation oxide film is disposed at said first and second isolation regions;
- (e) after the step (d), introducing second impurities of said first conductivity type into said memory cell region of said substrate, through at least said isolation oxide film, to form a second channel stopper region of said first conductivity type under said isolation oxide film and a barrier region under said first active regions, said barrier region being integrally formed with said second channel stopper region in said substrate and having a higher impurity concentration than that of said first active regions of said memory cell region.
- 23. A method of producing a semiconductor memory device according to claim 22, wherein said barrier region is a region serving as a potential barrier against electron-hole pairs generated by .alpha.-rays entering the semiconductor substrate.
- 24. A method of producing a semiconductor memory device according to claim 23, wherein the impurity of the first conductivity type is introduced into said memory cell region, so as to simultaneously form said second channel stopper region and said barrier region.
- 25. A method of producing a semiconductor memory device according to claim 22, wherein a position of a peak impurity concentration of said barrier region, under the active region, is about 0.5 microns depth from the principal surface of said substrate.
- 26. A method of manufacturing a semiconductor memory device according to claim 22, wherein said mask film comprises at least an oxidation impermeable film, and wherein the step (d) includes, after selectively removing said oxidation impermeable film of said mask film which is disposed at said first isolation region, selectively oxidizing said main surface of said substrate in said first and second isolation regions by using said oxidation impermeable film as a mask, to form said isolation oxide film at said first and second isolation regions.
- 27. A method of manufacturing a semiconductor memory device according to claim 22, wherein the second impurities are introduced in step (e) so as to simultaneously form said second channel stopper region under the isolation oxide film and the barrier region under the first active regions.
- 28. A method of manufacturing a semiconductor memory device according to claim 27, further comprising the steps of:
- forming first MISFETs in said first active regions of said memory cell region, wherein each of said memory cells comprises a respective one of said first MISFETs; and
- forming second MISFETs in said second active regions of said peripheral circuit region, wherein said peripheral circuit comprises said second MISFETs.
- 29. A method of manufacturing a semiconductor memory device according to claim 28, further comprising the step of forming capacitance elements in said memory cell region, thereby to form said memory cells comprised of said capacitance elements and said first MISFETs.
- 30. A method of manufacturing a semiconductor memory device according to claim 29, wherein said first conductivity is a p-type conductivity, and each of said first MISFETs is of n-type conductivity opposite to said p-type conductivity.
- 31. A method of manufacturing a semiconductor memory device according to claim 27, wherein the step (c) of selectively introducing first impurities of said first conductivity type, and the step (e) of introducing second impurities of said first conductivity type, each include an ion implantation, and wherein said ion implantation in the step (e) is performed at an implantation energy higher than that of said ion implantation in the step (c).
- 32. A method of producing a semiconductor memory device according to claim 11, wherein the first impurities are selectively introduced only into the principal surface of said peripheral circuit region.
Priority Claims (1)
Number |
Date |
Country |
Kind |
60-140061 |
Jun 1986 |
JPX |
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Parent Case Info
This application is a continuation application of application Ser. No. 07/063,110, filed Jun 17, 1987, now abandoned.
US Referenced Citations (3)
Foreign Referenced Citations (8)
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Continuations (1)
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Number |
Date |
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Parent |
63110 |
Jun 1987 |
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