Patent Application
20080076263
While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the invention, this invention may be more readily understood and appreciated by one of ordinary skill in the art from the following description of the invention when read in conjunction with the accompanying drawings, in which:
As the feature sizes associated with semiconductor devices decrease, the need for inspection of semiconductor substrates during fabrication processes increases. In many instances, the diminishing feature sizes are dictating the use of more precise inspection methods and processes for inspecting semiconductor substrates, such as electron beam inspection processes. Damage to semiconductor substrates resulting directly from electron beam inspection of semiconductor substrates has been documented. However, it has now been discovered that electrical charge imbalances on semiconductor substrates resulting from electron beam inspection also facilitate corrosion of the semiconductor substrates in later processing steps, and particularly during semiconductor substrate rinse processes. According to particular embodiments of the invention, the corrosive damage to semiconductor substrates resulting from the charge imbalances caused by electron beam inspection of the semiconductor substrates may be reduced or eliminated by minimizing the charge imbalances on the surfaces of a semiconductor substrate.
Electron beam inspection of a semiconductor substrate causes an electron imbalance in the surface and subsurface of a semiconductor substrate. In some instances, the electron imbalance results in positively charged semiconductor substrate surfaces, and in others, negatively charged semiconductor substrate surfaces. For example, electron beam inspection may involve the extraction of electrons from the surfaces of a semiconductor substrate, resulting in a positively charged surface on the semiconductor substrate. Metal contacts or surfaces on the semiconductor substrate subjected to such extraction of electrons are positively charged following electron beam inspection of the semiconductor substrate.
The immersion or exposure of the positively charged semiconductor substrate to de-ionized (DI) water may result in corrosion of the semiconductor substrate and particularly the positively charged metals that are part of such surfaces. The positively charged metals may react with hydroxyl ions formed in the DI water in accordance with Reaction 1:
M+n+nH2OM(OH)n+nH+ (1),
where M is a metal and n is the charge of the metal. The formation of metal oxides or metal hydroxides may result in the corrosion of the semiconductor substrate.
Electron beam inspection of a semiconductor substrate may also damage or remove protective oxide layers existing on a semiconductor substrate prior to electron beam inspection. The removal or damage to the protective oxide layers may expose metals on the semiconductor substrate which may be corroded by exposure to DI water, such as during a DI water rinse process.
Other forms of corrosion may also occur on the semiconductor substrate as a result of a positive or negative charge on the surfaces of the semiconductor substrate, or damaged or removed protective oxide layers on the semiconductor substrate, resulting from exposure of the semiconductor substrate to electron beam inspection.
Corrosion resulting from rinse processes or chemical processes following electron beam inspection of a semiconductor substrate is undesirable. As the feature sizes on semiconductor substrates decrease, methods and processes for reducing corrosion resulting from rinse processes or chemical processes following electron beam inspection of semiconductor substrates are desired.
According to particular embodiments of the invention, a charge imbalance on the surface of a semiconductor substrate caused by electron beam inspection of the semiconductor substrate may be reduced subsequent to the electron beam inspection. The reduction of the charge imbalance on the surface of the semiconductor substrate may reduce the formation of defects in the semiconductor substrate resulting from the electron beam inspection of the semiconductor substrate. For example, reduction of the charge imbalance on the surface of a semiconductor substrate following exposure to electron beam inspection may reduce corrosion of metal in the semiconductor substrate triggered by the charge imbalance when the semiconductor substrate is immersed in a DI water bath or other semiconductor substrate rinse process.
According to some embodiments of the invention, a charge imbalance on surfaces of a semiconductor substrate may be reduced or eliminated by contacting the semiconductor substrates with a liquid or gas capable of reducing or eliminating the charge imbalance. For example, a semiconductor substrate exposed to an electron beam inspection process may be contacted with a small chain organic solvent in liquid or gaseous form. In other embodiments, an electron beam inspected semiconductor substrate may be contacted with a non-neutral pH based solution in liquid or gaseous form to reduce or eliminate the charge imbalance on the semiconductor substrate surfaces.
According to various embodiments of the invention, a process for reducing a charge imbalance in one or more surfaces of a semiconductor substrate may be performed following a process which causes the charge imbalance. For example, a process for reducing charge imbalances in the surfaces of a semiconductor substrate exposed to electron beam inspection following chemical-mechanical planarization (CMP) is illustrated in
The inclusion of the step of exposing the semiconductor substrate to a charge imbalance correcting composition 140 is unique to the semiconductor fabrication processes of embodiments of the invention and is not currently practiced with conventional semiconductor fabrication processes. The inclusion of such a step in a semiconductor fabrication process may reduce or eliminate charge imbalances in surfaces of a semiconductor substrate resulting in a reduction or elimination of corrosion in the surfaces of the semiconductor substrate during conventional rinsing processes.
In some embodiments of the invention, the exposure of a semiconductor substrate to a charge imbalance correcting composition 140 may include exposing the semiconductor substrate to a vapor composition comprising a small chain organic solvent. One such small chain organic solvent is 2-propanol, or isopropyl alcohol (IPA). In other embodiments, the small chain organic solvent vapor may include n-methypyrilidone (NMP). In still other embodiments of the invention, the small chain organic solvent vapor may include methanol.
Isopropyl alcohol is a chemical composition conventionally used with various semiconductor substrate fabrication processes and is therefore readily available in semiconductor fabrication processes. In some instances, IPA has been used as a rinse chemistry to remove chemicals or other pollutants from semiconductor substrates prior to exposure of such semiconductor substrates to a DI water rinse bath. In other instances, IPA has been used as a drying agent to dry semiconductor substrates exiting rinse baths. However, IPA has not been used in semiconductor fabrication processes to alter the charge state of semiconductor substrate surfaces prior to DI water rinse baths or as a rinse following exposure of a semiconductor substrate to electron beam inspection.
Similarly, n-methylpyrrolidone (NMP) is a chemical composition conventionally used with various semiconductor substrate fabrication processes, however, it has not been used in processes to reduce or eliminate charge imbalances in surfaces of semiconductor substrates. NMP is also readily available and may be easily incorporated into semiconductor substrate fabrication processes as a small chain organic solvent that may be used to reduce or eliminate charge imbalances in surfaces of semiconductor substrates.
In other embodiments of the invention, the exposure of a semiconductor substrate to a charge imbalance correcting composition 140 may include exposing the semiconductor substrate to a vapor composition comprising a non-neutral pH composition. The non-neutral pH composition may be selected to correct the charge imbalance in the surfaces of a semiconductor substrate. For example, if an electron beam inspection of a semiconductor substrate results in a net negative charge in the surfaces of the semiconductor substrate, a weak acid may be selected as the non-neutral pH composition. Weak acids have mobile hydrogen ions which, when contacted with the negatively charged surfaces of the semiconductor substrate, will neutralize the charge imbalance in the surface. The hydrogen ions may react with the negatively charged surface or with negatively charged species on the surfaces of the semiconductor substrate, such as hydroxyl ions, effectively canceling the charge imbalance in the surfaces of the semiconductor substrate or in negatively charged species on the semiconductor substrate.
Weak acids that may be used with various embodiments of the invention as a charge imbalance correcting composition include acids that do not fully ionize in solution. In addition, weak acids may include acids having low disassociation constants, such as, but not limited to, about 2.8 pKa to about 6.4 pKa. In addition, any weak acid or diluted acid capable of neutralizing negative charges on a semiconductor substrate may be used. For example, weak acids that may be used with embodiments of the invention may include, but are not limited to, compositions containing ethanoic acid, hydroxyacetic, methanoic acid, hydrogen carbonate, 2-hydroxy-1,2,3-propanetricarboxylic acid, butanoic acid, succinic acid, and mixtures thereof.
In those instances where electron beam inspection of a semiconductor substrate results in a net positive charge in the surfaces of the semiconductor substrate, or in other chemical species on the semiconductor substrate, a non-neutral pH composition capable of neutralizing the positive charge may be selected as a charge imbalance correcting composition. For example, a weak base may be applied to the semiconductor substrate to neutralize positive charges in the surfaces of the semiconductor substrate. Weak bases have an abundance of negatively charged hydroxyl ions which may react with the semiconductor substrate or otherwise neutralize the positive charge in the surfaces of the semiconductor substrate.
Weak bases that may be used with various embodiments of the invention as a charge imbalance correcting composition include any bases that do not fully ionize in an aqueous solution. Weak bases may also include bases or compositions containing a diluted base that are capable of neutralizing positive charges on a semiconductor substrate. In addition, weak bases may include bases having disassociation constants, such as, but not limited to, about 8.0 pKa to about 16.5 pKa. For instance, weak bases that may be used with embodiments of the invention may include, but are not limited to, compositions containing tromethamine, 2-amino-2-hydroxymethyl-1,3-propanediol, methylamine, trimethylamine, N-methyl-2-pyrrolidinone, and mixtures thereof.
Methods for exposing semiconductor substrates to vapors are well known and any conventional method capable of distributing a selected charge imbalance correcting composition may be used to expose a semiconductor substrate to a charge imbalance correcting composition according to embodiments of the invention. For example, one process for exposing a charge imbalanced semiconductor substrate 210 to a gaseous charge imbalance correcting composition 220 is illustrated in
According to other embodiments of the invention, a charge imbalance on a semiconductor substrate may be reduced or eliminated by exposing the semiconductor substrate to a liquid charge imbalance correcting composition, such as a composition comprising a small chain organic solvent. As with the exposure of semiconductor substrates to gaseous, or vapor, forms of small chain organic solvents, semiconductor substrates having charge imbalances in surfaces thereof may be exposed to compositions including liquid IPA, NMP, or methanol to reduce or eliminate the charge imbalances in surfaces of the semiconductor substrates.
In other embodiments, semiconductor substrates having charge imbalances may be exposed to a liquid composition containing a weak base or a weak acid. Exposure of a positively charged surface of a semiconductor substrate to a weak base may neutralize the positive charge of the surface of the semiconductor substrate. Similarly, exposure of a negatively charged surface of a semiconductor substrate to a weak acid may neutralize the negative charge of the surface of the semiconductor substrate.
Liquid charge imbalance correcting compositions may be applied to an electrically imbalanced semiconductor substrate in any numbers of ways. For example, in some embodiments, a charge imbalanced semiconductor substrate may be rinsed in a liquid bath of a charge imbalance correcting composition as illustrated in
In other embodiments, a liquid charge imbalance correcting composition such as small chain organic solvent, weak acid, weak base, or mixture thereof, may be sprayed onto the semiconductor substrate, thereby applying the liquid to the surfaces of the semiconductor substrate.
Application of a liquid or gaseous charge imbalance correcting composition to a semiconductor substrate according to embodiments of the invention may also be performed using equipment and processes that are available in conventional semiconductor fabrication processes. For example, charge imbalance correcting compositions according to embodiments of the invention may be used with vapor jet drying processes, GreenDry processes, Marangoni drying processes, enhanced Marangoni drying processes, and surface tension gradient processes.
The treatment of an electron beam inspected semiconductor substrate with a liquid or vapor charge imbalance correcting composition containing IPA, NMP, methanol, one or more weak acids, one or more weak bases, or mixtures thereof, may reduce, eliminate, or neutralize electrical charges on the semiconductor substrate. The reduction in the positive or negative electrical charges in surfaces of the semiconductor substrate may reduce or eliminate corrosion resulting from the exposure of such surfaces to a rinse bath following electron beam inspection.
According to other embodiments of the invention, a semiconductor substrate may be treated prior to electron beam inspection of the semiconductor substrate to reduce charge imbalances on the surface and subsurfaces of the semiconductor substrate resulting from electron beam inspection of the semiconductor substrate. For example, a process for reducing charge imbalances in the surfaces of a semiconductor substrate exposed to electron beam inspection following chemical-mechanical planarization (CMP) is illustrated in
Exposure of the semiconductor substrate to a charge imbalance correcting composition 440 may include the exposure of the semiconductor substrate to a small chain organic solvent such as IPA, NMP, or methanol, or exposure of the semiconductor substrate to a non-neutral pH composition such as a weak acid or a weak base. Liquid or vapor charge imbalance correcting compositions may be applied to the substrate using various methods, including those described with respect to other embodiments of the invention.
According to still other embodiments of the invention, corrosion of a semiconductor substrate following electron beam inspection may be reduced or eliminated by repairing, forming, or generating a protective oxide layer, nitride layer, or passivation layer over the semiconductor substrate following exposure to electron beams. The electron beam inspection of a semiconductor substrate may damage or remove protective layers on the semiconductor substrate, such as oxide layers. The formation or generation of one or more oxide layers, nitride layers, or passivation layers on the semiconductor substrate following such damage may protect features of the semiconductor substrate from corrosion during subsequent processing actions.
For example, a process 160 for forming an oxide layer on a semiconductor substrate following electron beam inspection is illustrated in
The oxide layers created during the oxide formation process 175 may provide a protective layer over one or more portions of the semiconductor substrate such that the one or more oxide layers protect the semiconductor substrate from corrosion during subsequent rinse baths or other chemical processes. According to some embodiments of the invention, the oxide formation process 175 may include a plasma deposition process. The plasma deposition process may deposit, or otherwise generate, one or more oxide layers on a semiconductor substrate. For example, a semiconductor substrate 510 may be exposed to a plasma 520 within a plasma deposition chamber 530 as illustrated in
The oxide formation process 175 may also be substituted with a nitride formation process or a passivation layer formation process. In other embodiments, one or more oxide formation processes, nitride formation processes, or passivation layer formation processes may be used to form, generate, or grow one or more oxide layers, nitride layers, or passivation layers on the semiconductor substrate.
Formation of an oxide, nitride, or passivation layer on one or more surfaces of the semiconductor substrate 510 may be performed by exposing the semiconductor substrate 510 to a plasma including argon, nitrogen, oxygen, or a mixture thereof.
According to some embodiments of the invention, one or more oxide layers may be generated on a semiconductor substrate using any number of conventional methods for forming an oxide layer. In other embodiments of the invention, one or more nitride layers may be deposited on a semiconductor substrate using any number of conventional methods for forming a nitride layer. In still other embodiments of the invention, one or more passivation layers may be formed on a semiconductor substrate using any number of conventional methods for forming a passivation layer.
A group of fabricated semiconductor substrate wafers was exposed to electron beam inspection and various post-electron beam inspection treatments in an attempt to analyze the damage caused by electron beam inspection. Three semiconductor substrate wafers were subjected to electron beam inspection and various post-inspection treatments. A summary of the tests performed on the semiconductor substrate wafers is listed in Table 1.
All of the wafers identified in Table 1 were subjected to a tungsten chemical-mechanical planarization (CMP) prior to electron beam inspection of the wafer. Wafer 1 was processed according to conventional methods, which do not include a post-electron beam inspection treatment. Wafer 2 was subjected to a dry strip treatment following electron beam inspection to passivate any damage to wafer 2 caused by the electron beam inspection. Both wafers 1 and 2 were subjected to a DI water nanospray rinse. Wafer 3 was subjected to a Marangoni dry instead of a post-electron beam inspection treatment and DI water rinse.
Wafer 1 was inspected for damage to the wafer prior to electron beam inspection. The results of the inspection are illustrated in
As illustrated by
In an attempt to limit damage caused by the electron beam inspection of a wafer, wafer 2 was subjected to a dry strip treatment following electron beam inspection. An inspection of wafer 2 prior to being exposed to an electron beam inspection is illustrated in
As illustrated by
Wafer 3 was inspected prior to electron beam inspection and the inspection is illustrated in
As illustrated in
The data and inspection results for wafers 1 through 3 indicate that damage promoted by the electron beam inspection of a wafer may be reduced or eliminated by treating the wafer, or passivating the surface of the wafer, prior to performing a DI water nanospray rinse or other chemical process on the wafer following electron beam inspection. Wafer 2 and wafer 3, treated according to embodiments of the invention, did not exhibit damage similar to the damage of wafer 1 caused by the electron beam inspection of the wafers.
Having thus described certain currently preferred embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are contemplated without departing from the spirit or scope thereof as hereinafter claimed.
