Patent Application
20120117305
The present invention relates to a method for storing efficiently a plurality of blocks of data among a plurality of independently read/writable non-volatile memory devices that have a block of data as the minimum amount of data that can be read from or written to the memory device. The plurality of blocks of data are received randomly in time. The method stores the plurality of blocks of data so that upon subsequent sequential readout of the blocks of data from the plurality of non-volatile memory devices, read efficiency is increased. The present invention also relates to a memory controller that executes the foregoing described method as well as a memory system with a memory controller that executes the method.
Non-volatile memory devices that store or read a block of data at a time, such as a page of data, are well known in the art. For example, NAND memory devices typically can store a page, such as 4 kilobytes, of data in the device at each read/write operation. Other types of non-volatile memory devices that store or read a block of data at a time, include so called managed NAND memory devices, such as the NANDrive (NANDrive is a trademark of Greenliant Systems, Inc.) memory device available from Greenliant Systems, Inc. of Santa Clara Calif. In a managed NAND memory device, such as the NANDrive memory device, a controller controls the raw (or unmanaged) NAND memory device so that standard interface, such as SATA (serial ATA) or PATA (parallel ATA) can be used to interface with the NANDrive memory device. As used herein, the term “NAND memory device” shall refer to both raw as well as managed NAND memory devices.
In a NAND memory device, the non-volatile memory device can be written to or read from only in blocks of data at a time. Because of their ability to read back a block of data at a time, NAND memory devices are useful to store large amounts of data.
In the prior art, many NAND memory devices are clustered to form a large storage system, to compete with the magnetic or optical storage medium to store a large amount of data. In such application, many NAND memory devices are used, with each NAND memory device being independently controllable to read from or to write to. Each NAND memory device is an integrated circuit chip (or in the case of NANDrive, a memory module with a NAND memory controller and a raw NAND memory chip) and includes a buffer for storing a block of data to be written to or read from the non-volatile memory cells in the memory array. As with the magnetic storage medium with which it replaces, each NAND memory device stores and retrieves blocks of data based upon a physical address for each block. Further, to the outside world, each block of data to be written into or read from has a logical address. All of this is well known to one of ordinary skill in the art. Therefore, memory controller operating the NAND memory device(s) must have an address mapping table mapping the logical address of the block of data with the physical address of where the data is stored.
Referring to
The problem with the storage of these blocks of data that are received randomly in time is that when it is desired to perform a read of sequential blocks of data from the system 10, there may be a bottleneck in the sequential read-out of the plurality of blocks of data. For example, during the sequential read out, Devices 20a and 20b (and in fact all of the devices) can be “turned on” to cause the read-out of the blocks of data from the non-volatile memory cells into the associated buffer. However, if the blocks of data having different logical addresses are stored in the same physical memory device 20, then the memory device 20 can be used to read only one block of data. Thus, until the device 20a finishes the read of the block of data having the logical address 1, device 20a cannot be used to read any other blocks of data. The reading of the block of data having logical address 2 has to wait until the read out of data from memory device 20a is completed. So long as Device 20a is still servicing the read out of the block of data associated with logical address 1, the block of data associated with logical address 2 cannot even begin to be processed, since the block of data from the non-volatile memory cells in the Device 20a are still stored in the buffer within the device 20a. Hence, in the prior art, such a bottleneck can cause a decrease in the read performance of sequential blocks of data.
Accordingly, in the present invention, a method of storing a plurality of blocks of data received, in a plurality of physically distinct memory devices with each memory device capable of being independently written to or read from. Each block of data received is the minimum amount of data that can be written to or read from the memory device and each block has an associated logical address, with the plurality of blocks of data received collectively having a logical address range. The method comprises assigning a different memory device to each different block of data received for storage based on the associated logical address of the received data block. The logical address range of the plurality of blocks of data is interleaved among the plurality of physically distinct memory devices. The plurality of blocks of data received are then stored in the plurality of distinct physical memory devices.
The present also relates to a memory controller for controlling a plurality of independent memory devices. The memory controller has a processor and a non-volatile memory for storing programming code for execution by the processor in accordance with the foregoing described method.
Finally, the present invention relates to a memory system having a plurality of independent memory devices and the foregoing described memory controller for controlling the plurality of memory devices.
Referring to
The memory controller 30 comprises a processor 32 and a non-volatile memory 34, typically NOR memory, for storing programming code to be executed by the processor 32. The programming code stored in the NOR memory 34 causes the processor 32 to operate the method of the present invention in controlling the storage of a plurality of blocks of sequential data to be stored in the plurality of NAND memory devices 20(a-h).
Referring to
The advantage of the method of the present invention is as follows. For a readout of the eight blocks of sequential data associated with logical addresses of Logical Address 1, 2, . . . and 8, all eight memory devices 20(a-h) can be activated to read the contents of the memory cells from their respective arrays in their physical addresses of A, B, . . . and H at the same time, and store them in the buffer of the associated memory devices 20(a-h). Thereafter, the data can be read from the buffers of the memory devices 20(a-h) in the order of 20a, 20b, . . . and 20h, by supplying data from the buffer of the memory device 20 onto the bus, 1 . . . 4. If the buses: Bus 1 . . . Bus 4 can be operated in parallel, then all four blocks of data can be outputted from the system 50 at the same time. If the buses: Bus 1. Bus 4 cannot be operated in parallel, then each block of data having the logical address of Logical Address 1 . . . 4 is transferred to the buses: Bus 1 . . . Bus 4, in sequence. Once a block of data, e.g. block of data from device 20a is transferred to Bus 1, the Bus 1 is available again, and the block of data in the buffer of memory device 20e can be transferred onto Bus 1, while the data from the other memory devices (b-d) is being transferred from the other buses. Alternatively, if the buses Bus 1 . . . . Bus 4 can be operated in parallel, then once all four blocks of data have been outputted, the data stored in the buffer of the memory devices 20(e-h) can be transferred on to the buses, Bus 1, Bus 2, . . . Bus 4, to be outputted from the memory system 50. In this way, a faster readout of the blocks of sequential data can be obtained compared to the method of the prior art.
To ensure that the memory controller 30 assign the logical address of a block of data to the physical address of a memory device different from a memory device associated with a different block of data, the following preferred method can be used. It should be noted that although the following method is preferred, it is by no means the only method.
In the preferred method of the present invention, the memory controller 30 must first determine the number N of independently read/writable memory devices 20(a-h) that can be used to store the plurality of blocks of data arriving randomly in time. In the preferred method of the present invention, the memory controller 30 takes the logical address of a block of data and performs a modulo N operation, and note the remainder. The remainder is then assigned as the device ID and can be concatenated to the physical address. The operation would then consist of REM (MOD (Logical Address X),N). The remainder can have a value between 0 and N−1. If the remainder of the operation is M, where M is between 0 and N−1, the same operation performed on an immediate subsequent block of data would result in M+1. Thus, in the example shown in
When the blocks of data are stored in the foregoing manner, a sequential read operation will result in much faster speed. Because the reading of the data from the non-volatile memory cells into the buffers of the various memory devices 20(a-h) can be done in parallel for the sequential blocks of data, the total read out time required for the read out of the sequential blocks of data can be reduced.
