Patent Application
20120042292
The present invention relates generally to a method of synthesis of electronic circuits and to a cell library comprising a plurality of logic cells.
Digital circuits based on CMOS technology comprise one or more logic devices each comprising P-channel MOS transistors coupled to a supply voltage and N-channel MOS transistors coupled to a ground voltage. These transistors are controlled by one or more input signals to perform specific logic functions. Examples of such logic devices include OR-gates, AND-gates, NAND-gates, NOR-gates, XOR-gates and NOR-NAND gates. Such gates can be automatically assembled by computer systems in an operation known as logic synthesis.
To reduce current leakage and thus improve energy efficiency, it has been proposed to increase the gate lengths of each transistor in such logic devices. However, there is a trade-off in increasing gate lengths as this also leads to a reduction in the speed of the device.
In new CMOS technologies, it has been proposed to use ultra low supply voltages to further improve energy efficiency. However, while this considerably decreases current leakage, when combined with the increased gate lengths, this leads to a high performance penalty and an increase in area.
There is thus a need for an improved design strategy for maintaining energy efficiency as well as maintaining high operating speeds of such devices.
It is an aim of at least one embodiment of the present invention to at least partially address one or more needs in the prior art.
According to one aspect of the present invention, there is provided a method of synthesis of at least one logic device coupled between first and second supply voltages and having a plurality of inputs and an output, the logic device comprising a plurality of transistors having a standard gate length, the method comprising: identifying, in said at least one logic device, one or more transistors connected between said first or second supply voltage and said output node; and increasing the gate length of each of said identified one or more transistors.
According to one embodiment, the identifying step further comprises identifying one or more transistors connected between said first or second supply voltage and one or more gates of said plurality of transistors.
According to another embodiment, each transistor identified in said identifying step is connected in parallel with at least one other of said plurality of transistors.
According to another embodiment, the method further comprises determining whether any of said plurality of transistors of said logic device forms an inverter, wherein during said identifying step transistors forming an inverter are excluded from identification.
According to another embodiment, the identifying step comprises identifying one or more transistors comprising a source connected to said first or said second voltage and a drain connected to said output node or one or more gates of said plurality of transistors.
According to another embodiment, the method further comprises, before said identifying step, synthesizing a layout of said at least one logic device such that each of said plurality of transistors of said at least one logic device has said standard length.
According to another embodiment, the method further comprises storing, in a cell library, a modified layout of said at least one logic device comprising said increased gate length of said identified one or more transistors.
According to another embodiment, the gate length of said identified one or more transistors is increased by between 1 and 100 percent.
According to another aspect of the present invention, there is provided an electronic storage medium storing a program that, when executed by a computer, implements the above method.
According to another aspect of the present invention, there is provided a cell library comprising a plurality of logic devices each coupled between first and second supply voltages and having a plurality of inputs and an output, wherein each of the plurality of logic devices comprises at least one transistor having a standard gate length, and one or more further transistors connected between said first or second supply voltage and said output node, each of said one or more further transistors having a gate length greater than said standard gate length.
According to another embodiment, each of said plurality of logic devices further comprises one or more further transistors connected between said first or second supply voltage and one or more gates of said plurality of transistors, each of said one or more further transistors having a gate length greater than said standard gate length.
According to another aspect of the present invention, there is provided an electronic storage medium storing the above cell library.
The foregoing and other purposes, features, aspects and advantages of the invention will become apparent from the following detailed description of embodiments, given by way of illustration and not limitation with reference to the accompanying drawings, in which:
The transistors of the circuit blocks 102 and 106 are each controlled by one of a pair of input signals A and B provided on respective input lines 108 and 110. While not illustrated, there may be one or more additional input signals for controlling transistors of the circuit block 102 and/or 106. The output node 104 has a voltage which is either close to the supply voltage level VDD or close to the ground voltage GND, depending on whether transistors (not illustrated) of the circuit block 102 or those in the circuit block 106 are conducting. The output voltage Z of the device may be provided by the voltage at the output node 104 directly, or by the voltage at an output node 104′ after one or more optional inverters 112.
Assuming a CMOS implementation, the circuit block 102 comprises PMOS transistors, while the circuit block 106 comprises NMOS transistors. A method of selectively increasing the gate length of certain transistors of the circuit blocks 102, 106 will now be described with reference to the flow diagram of
In a first step S1, a digital circuit is synthesized having N logic devices, which are designated as devices 1 to N. In each logic device, all the transistors initially have a standard gate length for the technology concerned. For example assuming a 45 nm technology, in which the smallest photolithography interval is around 45 nm, the gate lengths of all transistors are, for example, initially at around 40 nm.
In a next step S2, a variable “n” is initialized at a value 1.
In a next step S3, any transistors forming inverters in device n are detected. For example, such transistors can be listed in a list “INVLIST”. A CMOS inverter is recognized as an NMOS transistor having its source connected to ground and a PMOS transistor having its source connected to VDD, the P and N channel transistors sharing common gate and drain nodes.
In a next step S4, the logic device n, initially being a first logic device of the devices 1 to N, is analyzed to determine whether at least one transistor is identified as having its source connected to supply voltage VDD or ground voltage GND, and its drain connected to the output voltage Z or to only gates in device n. In other words, it is determined whether the circuit block 102 of
In step S5, it is determined whether any transistors identified in step S4 form inverters, by for example checking whether they are included in the list “INVLIST”. Any identified transistors that do not form inverters have their gate lengths increased with respect to the standard length. The next step after S5, and after S4 in the case that no transistors are identified, is S6.
In step S6, n is incremented. The next step is S7.
In S7 it is determined whether n is higher than N, in other words whether the final logic device has been analyzed. If not, the method returns to S3. If n is greater than N in step S7, the next step is S8 in which the method ends.
Examples of the application of the method of
Applying the method of
The increase in gate length applied to the transistors will depend on various factors, such as their original length and the level of the supply voltage. In the case that the transistors 308, 310, 312 and 314 all initially have the standard gate length of 40 nm, the gate lengths of transistors 312 and 314 are, for example, increased to around 50 nm, in other words by around 20 percent. In alternative embodiments, the increase could be anywhere between 1 and 100 percent, or even higher, depending on design specifications.
The logic device 400 also comprises NMOS transistors 420 and 422 coupled in series between the output line 410 and the ground voltage GND, and an NMOS transistor 424 connected directly between the output line 410 and the ground voltage GND.
The transistors 414 and 420 receive, at their gate nodes, the control signal A on an input line 404, while the transistors 416 and 422 receive, at their gate nodes, the input signal B via an input line 406. The transistors 418 and 424 receive at their gate nodes the signal C via an input line 412.
Applying the method of
Applying the method of
The computing device 600 comprises a processor 602, controlled by instructions loaded from an instruction memory 604. A further memory 606 contains a cell library, with a portion 608 storing one or more original layouts of synthesized logic devices having a standard gate length. Memory 606 also comprises a portion 610, which stores one or more modified layouts 610 of the logic devices, in which the gate length of at least some of the transistors have been selectively increased based on the method described herein.
In particular, under the control of the instruction memory 604, the processor 602 is arranged to take original logic device layouts from memory portion 608, perform the steps of
It will be apparent to those skilled in the art that, in alternative embodiments, the memory 606 storing the cell library could be at a remote location with respect to the computing device 600, for example coupled to the computing device 600 via an intermediate wired or wireless network.
The present inventors have found that, by selectively increasing the gate lengths of transistors coupled directly between the supply or ground voltages and the output voltage Z or the gate of another transistor, the overall current leakage can be significantly reduced without significantly reducing the speed of the device. On the contrary, the present inventors have found that where multiple transistors are coupled in series between one of the supply voltages and the output node, an increase in the gate lengths of these transistors has a high impact on the speed of the device, and a lesser impact on the current leakage. Preferably, the gate lengths of transistors forming the inverter are not increased.
As an example, on average over a number of devices, applying the selective gate enlargement of the present invention, assuming an initial gate length of 40 nm, an enlarged length of 50 nm, and a supply voltage of 0.35 V, resulted in only a 4 percent increase in delay time, but still a reduction in current leakage of nearly 30 percent. This can be compared with a 50 percent increase in delay times if the gate lengths of the transistors are all enlarged. Similar results can be seen when the supply voltage is at 1.1 V.
Furthermore, an advantage of providing a cell library containing logic devices synthesized according to the method described herein is that circuits generated using such a cell library will have relatively high speed and low current leakage.
Having thus described at least one illustrative embodiment of the invention, various alterations, modifications and improvements will readily occur to those skilled in the art.
For example, while a number of specific examples of applications of the synthesis method described herein have been given with reference to
Furthermore, while examples have been described that use CMOS technology at 45 nm, it will be apparent to those skilled in the art that the synthesis method described herein could be applied to other CMOS technologies such as 65 nm or 32 nm, or to technologies other than CMOS.
Additionally, the synthesis method can be applied to a library of cells having larger gate sizes than a standard gate size, in order to selectively enlarge some gate cells to an even greater extent.
Such alterations, modifications and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The invention is limited only as defined in the following claims and the equivalent thereto.
