Method of transmitting data between different clock domains

Abstract

A method of transmitting data between different clock domains includes receiving data bits on the basis of a receiving clock, sequentially storing the data bits in a ring buffer, simultaneously transmitting a number of the stored data bits from the ring buffer on the basis of a first transmitting clock, and transmitting the stored data bits from the ring buffer on the basis of a second transmitting clock.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

FIG. 1 schematically illustrates a device for transmitting data between different clock domains according to an embodiment of the invention.

FIG. 2 schematically illustrates cyclic registers in a ring buffer according to an embodiment of the invention.

FIG. 3 schematically illustrates a circuit for implementing a cyclic register according to an embodiment of the invention.

FIG. 4 schematically illustrates an embodiment of a circuit for implementing the device of FIG. 1.

FIG. 5 schematically illustrates an example ring buffer.

FIG. 6 schematically illustrates an example memory device according to a parallel-loop-forward architecture.

Claims

1. A method of transmitting data between different clock domains, the method comprising: receiving data bits on the basis of a receiving clock;sequentially storing the data bits in a ring buffer;simultaneously transmitting a number of the stored data bits from the ring buffer on the basis of a first transmitting clock; andtransmitting the stored data bits from the ring buffer on the basis of a second transmitting clock.

2. The method according to claim 1, wherein the number of data bits simultaneously transmitted from the ring buffer is an odd number.

3. The method according to claim 2, wherein the number of data bits simultaneously transmitted from the ring buffer is nine.

4. The method according to claim 1, wherein sequentially storing the data bits in the ring buffer comprises: accessing the ring buffer for write operations on the basis of a write pointer and advancing the write pointer by one bit position at each cycle of the receiving clock.

5. The method according to claim 1, wherein simultaneously transmitting the number of the stored data bits from the ring buffer comprises: accessing the ring buffer for read operations on the basis of a first read pointer and advancing the first read pointer by a number of bit positions corresponding to the number of data bits at each cycle of the first transmitting clock.

6. The method according to claim 1, wherein transmitting the stored data bits from the ring buffer comprises: accessing the ring buffer for read operations on the basis of a second read pointer.

7. The method according to claim 1, wherein the frequency of the second transmitting clock corresponds to the frequency of the receiving clock.

8. The method according to claim 1, wherein the ring buffer is subdivided into a number of N cyclic registers in such a way that adjacent bits of the ring buffer are located in different cyclic registers, and wherein the method comprises: accessing the cyclic registers for write operations on the basis of a corresponding divided clock having 1/Nth times the frequency of the receiving clock and advancing a corresponding write pointer of each cyclic register at each cycle of the corresponding divided clock.

9. The method according to claim 8, wherein the number N of cyclic registers is four.

10. The method according to claim 8, wherein the divided clocks corresponding to the different cyclic registers are phase-shifted with respect to each other.

11. The method according to claim 10, wherein the phase shift between the divided clocks of cyclic registers containing adjacent bits of the ring buffer corresponds to 1/Nth times the clock cycle of the divided clocks.

12. The method according to claim 8, wherein transmitting the stored data bits from the ring buffer comprises: accessing the ring buffer for read operations on the basis of a second read pointer and advancing the read pointer by a number of bit positions corresponding to the number N of cyclic registers at each clock cycle of one of the divided clocks.

13. A device configured to transmit data between different clock domains, the device comprising: a receiver configured to receive data bits on the basis of a receiving clock;a ring buffer configured to sequentially store the data bits;a first transmitter configured to simultaneously transmit a number of the stored data bits from the ring buffer on the basis of a first transmitting clock; anda second transmitter configured to transmit the stored data bits from the ring buffer on the basis of a second transmitting clock.

14. The device according to claim 13, wherein the ring buffer is configured to sequentially store the data bits on the basis of a write pointer, configured to advance by one bit position at each cycle of the receiving clock.

15. The device according to claim 13, wherein the ring buffer is configured to be accessed for simultaneously reading out the number of data bits on the basis of a first read pointer which is advanced by a number of bit positions corresponding to the number of data bits at each cycle of the first transmitting clock.

16. The device according to claim 13, wherein the ring buffer is configured to be accessed for reading out the stored data bits on the basis of a second read pointer.

17. The device according to claim 13, wherein the frequency of the second transmitting clock corresponds to the frequency of the receiving clock.

18. The device according to claim 13, wherein the ring buffer is subdivided into a number of N cyclic registers in such a way that adjacent bits of the ring buffer are located in different cyclic registers; and wherein the cyclic registers are configured to be accessed for write operations on the basis of a corresponding divided clock having 1/N times the frequency of the receiving clock, a corresponding write pointer of each cyclic register being advanced at each cycle of the corresponding divided clock.

19. The device according to claim 18, wherein the divided clocks corresponding to the different cyclic registers are phase-shifted with respect to each other.

20. The device according to claim 19, wherein the phase shift between the divided clocks of cyclic registers containing adjacent bits of the ring buffer corresponds to 1/Nth times the clock cycle of the divided clocks.

21. The device according to claim 18, wherein the ring buffer is configured to be accessed for read operations on the basis of a second read pointer, the second read pointer being advanced by a number of bit positions corresponding to the number N of cyclic registers at each clock cycle of one of the divided clocks.

22. The device according to claim 18, wherein the ring buffer comprises a number of data registers configured to store the data bits and a shift register configured to sequentially enable one of the data registers for storing the data bits.

23. The device according to claim 18, wherein each of the cyclic registers comprises a number of data registers configured to store the data bits and a shift register configured to sequentially enable one of the data registers for storing the data bits.

24. A memory module, comprising: a memory core configured to store data;a receiver configured to receive data bits from a memory controller or a further memory module on the basis of a receiving clock;a ring buffer configured to sequentially store the data bits;a first transmitter configured to simultaneously transmit a number of the stored data bits from the ring buffer to the memory core on the basis of a first transmitting clock; anda second transmitter configured to transmit the stored data bits from the ring buffer to a further memory module on the basis of a second transmitting clock.

25. An apparatus for transmitting data between different clock domains, the apparatus comprising: means for receiving data bits based on a receiving clock;means for sequentially storing the data bits in a ring buffer;means for simultaneously transmitting a number of the stored data bits from the ring buffer based on a first transmitting clock; andmeans for transmitting the stored data bits from the ring buffer based on a second transmitting clock.