Claims
- 1. A memory system associated with a host microprocessor, the memory system comprising:
a plurality of virtual memory spaces, each based on a distinct virtual address translation scheme and defined by a distinct page table structure; a single physical memory space; and a plurality of hardware mechanisms, each associated with one of the virtual memory spaces, for translating a virtual address in the associated virtual memory space into a physical address for the physical memory space in accordance with the virtual address translation scheme for the associated virtual memory space.
- 2. The memory system of claim 1, further comprising a plurality of memory access operations sets, where the number of the memory access operations sets equals the number of the virtual spaces.
- 3. The memory system of claim 2, wherein each of the memory access operations sets is associated with one of the virtual memory spaces, wherein the operations in each set access only the associated virtual memory space.
- 4. The memory system of claim 3, further comprising an additional memory access operations set for accessing the single physical memory space directly.
- 5. A host microprocessor capable of executing a native instruction set and a plurality of foreign instruction sets, the microprocessor comprising:
a memory system including:
a plurality of virtual memory spaces, each based on a distinct virtual address translation scheme and defined by a distinct page table structure; a single physical memory space; a plurality of hardware mechanisms, each associated with one of the virtual memory spaces, for translating a virtual address in the associated virtual memory space into a physical address for the physical memory space in accordance with the virtual address translation scheme for the associated virtual memory space; and a plurality of memory access operations sets, wherein the number of the memory access operations sets equals the number of the virtual spaces; and means for simulating execution of instructions from multiple foreign instruction sets.
- 6. The host microprocessor of claim 5, wherein only one of the available virtual memory spaces (native virtual memory space) contains native instructions, executable directly by the microprocessor, and associated data.
- 7. The host microprocessor of claim 6, wherein all available virtual memory spaces are accessible in a mixed fashion by a host-executable application at the time of its execution by using the corresponding memory access operations sets.
- 8. The host microprocessor of claim 6, wherein all other virtual memory spaces (foreign virtual memory spaces) contain foreign instructions, which cannot be executed directly by the host microprocessor, and associated data.
- 9. The host microprocessor of claim 8, wherein each foreign virtual memory space is defined so as to mimic a virtual memory space of a foreign microprocessor, and wherein the means for simulating execution of instructions from multiple foreign instruction sets includes means for simulating execution of instructions for each foreign microprocessor being mimicked.
- 10. The host microprocessor of claim 5, wherein the means for simulating execution of instructions from multiple foreign instruction sets comprises a binary translation process.
- 11. The host microprocessor of claim 6, wherein the means for simulating execution of instructions from multiple foreign instruction sets comprises a binary translation process code, and wherein the binary translation process code and binary translated codes are located in the native virtual memory space only.
- 12. A method of creating a plurality of virtual memory spaces for a host application using a plurality of hardware access mechanisms, implemented in a host microprocessor having a single physical memory space, the method comprising:
creating a plurality of virtual memory spaces, each based on a distinct virtual address translation scheme and defined by a distinct page table structure, wherein each of said plurality of hardware mechanisms is associated with one of the virtual memory spaces, and wherein each hardware mechanism translates a virtual address in the associated virtual memory space into a physical address for the physical memory space in accordance with the virtual address translation scheme for the associated virtual memory space; and creating a plurality of memory access operations sets, wherein the number of the memory access operations sets equals the number of the virtual spaces.
- 13. The method of claim 12, further including:
simulating execution of instructions from multiple foreign instruction sets; wherein only one of the available virtual memory spaces (native virtual memory space) contains native instructions, executable directly by the host microprocessor, and associated data, and wherein all other virtual memory spaces (foreign virtual memory spaces) contain foreign instruction sets, which cannot be executed directly by the host microprocessor, and associated data.
- 14. The method of claim 13, wherein a host application, located in the native virtual memory space, simulates the behavior of execution of a foreign application, located in one of the foreign virtual memory spaces.
- 15. The method of claim 14, wherein the host application, which is simulating the behavior of the foreign application from one of the foreign virtual spaces, accesses the contents of the associated foreign virtual memory space in accordance with the semantics of the foreign operations being simulated by using host memory access operations provided for accessing only the associated foreign virtual memory space.
- 16. A computer system comprising:
a host microprocessor; a memory system associated with the host microprocessor, the memory system including:
a single physical memory space; a plurality of virtual memory spaces, each based on a distinct virtual address translation scheme and defined by a distinct page table structure; a plurality of hardware mechanisms, each associated with one of the virtual memory spaces, for translating a virtual address in the associated virtual memory space into a physical address for the physical memory space in accordance with the virtual address translation scheme for the associated virtual memory space; and a plurality of memory access operations sets, wherein the number of the memory access operations sets equals the number of the virtual spaces; and a binary translation software module configured to simulate execution of instructions from multiple foreign instruction sets.
- 17. The computer system of claim 16, wherein host executable applications are stored in a first one of the virtual memory spaces, which is designated to store host executable codes, and are executed by the host microprocessor directly.
- 18. The computer system of claim 17, wherein the remaining one or more virtual memory spaces are used to store foreign applications, which are compiled for different architecture computer systems and cannot be executed by the host microprocessor directly.
- 19. The computer system of claim 18, wherein a host application, located in the first virtual memory space, simulates the behavior of execution of a foreign application located in one of the remaining virtual memory spaces, and wherein the host application accesses the contents of the associated foreign virtual memory space in accordance with the semantics of the foreign operations being simulated by using host memory access operations provided for accessing only the associated foreign virtual memory space.
- 20 A computer system comprising:
a host microprocessor; a memory system associated with the host microprocessor, the memory system including:
a single physical memory space; means for creating multiple different virtual memory spaces for a host application; and means for accessing multiple virtual memory spaces by a host application during its execution by using separate sets of host memory access operations provided for each of the supported virtual memory spaces; and a binary translation software module configured to simulate execution of instructions from multiple foreign instruction sets.
- 21. The host microprocessor of claim 5, wherein each of the memory access operations sets is associated with one of the virtual memory spaces, wherein the operations in each set access only the associated virtual memory space.
- 22. The method of claim 12, wherein each of the memory access operations sets is associated with one of the virtual memory spaces, wherein the operations in each set access only the associated virtual memory space.
- 23. The computer system of claim 16, wherein each of the memory access operations sets is associated with one of the virtual memory spaces, wherein the operations in each set access only the associated virtual memory space.
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] This application is a continuation-in-part application of U.S. application Ser. No. 09/506,672, filed Feb. 17, 2000, which is a non-provisional of U.S. Provisional Patent Application Serial No. 60/120,344, filed Feb. 17, 1999, entitled “USING TWO VIRTUAL MEMORY SPACES FOR EFFECTIVENESS AND RELIABLE BINARY TRANSLATION BETWEEN DIFFERENT INSTRUCTION SETS,” the disclosure of each of which is hereby incorporated by reference in its entirety. This application is also related to the following co-pending U.S. Patent Applications, the disclosures of which are each hereby incorporated by reference in its entirety: patent application Ser. No. 09/505,652, entitled “SYSTEM FOR IMPROVING TRANSLATION OF SOFTWARE FROM A NATIVE COMPUTER PLATFORM TO A TARGET COMPUTER PLATFORM” (Attorney Docket No. 020181-005700US), filed Feb. 17, 2000; patent application Ser. No. 09/506,411, entitled “METHOD AND APPARATUS FOR EXECUTION OF MULTIPLE INSTRUCTION SETS ON THE HOST ARCHITECTURE THROUGH OPTIMIZING BINARY TRANSLATION” (Attorney Docket No. 020181-001500US), filed Feb. 17, 2000; and patent application Ser. No. 09/505,654, entitled “METHOD AND APPARATUS FOR CALL/RETURN PAIR SUPPORT WHILE EXECUTING ANOTHER INSTRUCTION SET ON THE HOST PLATFORM” (Attorney Docket No. 020181-001600US), filed Feb. 17, 2000.
Provisional Applications (1)
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Number |
Date |
Country |
|
60120344 |
Feb 1999 |
US |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
09506672 |
Feb 2000 |
US |
Child |
10453448 |
Jun 2003 |
US |