Claims
- 1. A method for determining validity of a proposed loop iteration schedule comprising:
receiving a dependence graph including operations and edges between said operations; receiving a performance specification; receiving an assignment of latencies to operations of said dependence graph; and determining existence of a placement of clock cycle-boundaries in said dependence graph such that all dependence and timing constraints are satisfied for said performance specification.
- 2. The method of claim 1 further including:
receiving a macrocell library; and assigning latencies to operations of said dependence graph.
- 3. The method of claim 1 further including:
reporting said existence as validity of said proposed iteration schedule.
- 4. The method of claim 3 wherein said performance specification includes:
a proposed initiation interval; and a proposed clock cycle-time.
- 5. The method of claim 4 further including:
receiving a proposed loop iteration scheduling vector; and calculating omegas for edges included in said dependence graph.
- 6. The method of claim 5 wherein for every recurrence cycle in said dependence graph, the total number of clock cycle-boundaries equals the said proposed initiation interval multiplied by the sum of the omegas for the edges belonging to said recurrence cycle.
- 7. The method of claim 5 wherein the maximum delay between successive clock cycle-boundaries is no greater than the said proposed clock cycle-time.
- 8. The method of claim 5 wherein the existence of a placement of clock cycle-boundaries in said dependence graph is done such that:
for every recurrence cycle in said dependence graph, the total number of clock cycle-boundaries so placed equals the said proposed initiation interval multiplied by the sum of the omegas for the edges belonging to said recurrence cycle, and the maximum delay between successive clock cycle-boundaries so placed is no greater than the said proposed clock cycle-time.
- 9. The method of claim 8 further including:
determining said placement.
- 10. The method of claim 9 further including:
determining a comparative cost of said proposed loop iteration schedule as a function of said placement.
- 11. The method of claim 10 wherein said comparative cost equals the number of cycle-boundary bits in said placement.
- 12. The method of claim 8 wherein said existence is determined by:
enumerating all recurrence cycles in said dependence graph; for each such recurrence cycle, determining a placement of clock cycle-boundaries along said recurrence cycle such that:
the total number of clock cycle-boundaries so placed equals the said proposed initiation interval multiplied by the sum of the omegas for the edges belonging to said recurrence cycle; the maximum delay between successive clock cycle-boundaries so placed is no greater than the said proposed clock cycle-time; and deriving said existence to be existence of a placement of clock cycle-boundaries along each said recurrence cycle.
- 13. The method of claim 12 wherein said placement of clock cycle-boundaries along said recurrence cycle further includes the condition that the clock cycle-boundaries so placed are consistent with previous clock cycle-boundary placements.
- 14. The method of claim 13 further including combining said placement of clock cycle-boundaries along each said recurrence cycle into said placement of clock cycle-boundaries in said dependence graph.
- 15. The method of claim 14 further including determining a comparative cost of said proposed loop iteration schedule as a function of said placement of clock cycle-boundaries in said dependence graph.
- 16. The method of claim 8 wherein said existence is determined by:
transforming said dependence graph into a synchronous circuit; retiming said synchronous circuit such that it satisfies the said proposed clock cycle-time; and deriving said existence to be existence of a solution to said retiming problem.
- 17. The method of claim 16 further including determining a comparative cost of said proposed loop iteration schedule as a function of the solution to said retiming problem, if one exists.
- 18. The method of claim 9 wherein said placement of clock cycle-boundaries in said dependence graph is determined by:
transforming said dependence graph into a synchronous circuit; retiming said synchronous circuit such that it satisfies the said proposed clock cycletime and has a minimal number of register bits; and deriving said placement from the solution to said retiming problem, if a solution exists.
- 19. An apparatus for validating a proposed loop iteration schedule comprising:
means for assigning latency to dependence graph operations; means for calculating omegas for each of edge associated with said dependence graph operations; means for determining existence of placement of clock cycle boundaries in said dependence graph; and means for determining a validity of proposed iteration schedule vectors.
- 20. The apparatus of claim 19 further including:
means for determining said placement of said clock cycle boundaries.
- 21. The apparatus of claim 20 further including means for determining a comparative cost of said proposed loop iteration schedule as a function of said placement of said clock cycle boundaries in said dependence graph.
- 22. The apparatus of claim 19 wherein said means for determining existence of said placement of clock cycle-boundaries includes:
for every recurrence cycle in said dependence graph, the total number of clock cycle-boundaries so placed equals a proposed initiation interval multiplied by a sum of the omegas for the edges belonging to the associated recurrence cycle of said dependence graph; and the maximum delay between successive clock cycle-boundaries so placed is no greater than a proposed clock cycle-time.
- 23. The apparatus of claim 22 wherein said means for determining existence includes:
enumerating all recurrence cycles in said dependence graph; for each such recurrence cycle, determining a placement of clock cycle-boundaries along said recurrence cycle such that:
the total number of clock cycle-boundaries so placed equals the said proposed initiation interval multiplied by the sum of the omegas for the edges belonging to said recurrence cycle; the maximum delay between successive clock cycle-boundaries so placed is no greater than the said proposed clock cycle-time; and deriving said existence to be existence of a placement of clock cycle-boundaries along each said recurrence cycle.
- 24. The apparatus of claim 22 wherein said means for determining existence includes:
transforming said dependence graph into a synchronous circuit; retiming said synchronous circuit such that it satisfies the said proposed clock cycletime; and deriving said existence to be existence of a solution to said retiming problem.
- 25. A computer product program comprising:
a memory having computer readable code embodied therein for assigning latency to dependence graph operations; code means for calculating omegas for each edge associated with said dependence graph operations; code means for determining existence of placement of clock cycle boundaries in said dependence graph; and code means for determining a validity of proposed iteration schedule vectors.
- 26. The computer product program of claim 25 comprising:
code means for determining said placement of said clock cycle boundaries.
- 27. The computer program of claim 26 further including code means for determining a comparative cost of said proposed loop iteration schedule as a function of said placement of said clock cycle boundaries in said dependence graph.
- 28. The computer program of claim 25 wherein said code means for determining existence of said placement of clock cycle-boundaries includes:
for every recurrence cycle in said dependence graph, the total number of clock cycle-boundaries so placed equals a proposed initiation interval multiplied by a sum of the omegas for the edges belonging to the associated recurrence cycle of said dependence graph; and the maximum delay between successive clock cycle-boundaries so placed is no greater than a proposed clock cycle-time.
- 29. The computer program of claim 26 wherein said code means for determining existence includes:
enumerating all recurrence cycles in said dependence graph; for each such recurrence cycle, determining a placement of clock cycle-boundaries along said recurrence cycle such that:
the total number of clock cycle-boundaries so placed equals the said proposed initiation interval multiplied by the sum of the omegas for the edges belonging to said recurrence cycle; the maximum delay between successive clock cycle-boundaries so placed is no greater than the said proposed clock cycle-time; and deriving said existence to be existence of a placement of clock cycle-boundaries along each said recurrence cycle.
- 30. The computer program of claim 26 wherein said code means for determining existence includes:
transforming said dependence graph into a synchronous circuit; retiming said synchronous circuit such that it satisfies the said proposed clock cycletime; and deriving said existence to be existence of a solution to said retiming problem.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application is related to commonly assigned U.S. Patent Application Serial No. [Attorney Docket No. 100200559-1] entitled “SYSTEM FOR AND METHOD OF CLOCK CYCLE-TIME ANALYSIS USING MODE-SLICING MECHANISM,” and U.S. Patent Application Serial No. [Attorney Docket No. 100200560-1] entitled “METHOD FOR DESIGNING MINIMAL COST, TIMING CORRECT HARDWARE DURING CIRCUIT SYNTHESIS,” filed concurrently herewith, the disclosures of which are hereby incorporated by reference in their entireties.