(A) Field of the Invention
The present invention is related to a method of wear leveling for a non-volatile memory.
(B) Description of Related Art
In consideration of limitations to RAM size, a wear leveling technology usually divides a non-volatile memory into a plurality of windows (zones) for write and/or erase functions. For wear leveling to blocks on a window basis, the blocks within a window are worn equally, but normally the wearing in different windows is not equalized.
Usually, the initial blocks of the first window (Window 0) store some system information such as the file table or directory table. For example, Block 0 of Window 0 may store the File Allocation Table (FAT), which is updated whenever data is written to any window. Because Block 0 of Window 0 usually stores the FAT, the erase function (wear) occurs more often in Window 0 than in other windows. Therefore, although Window 0 also undergoes wear leveling, the high wear counts caused by the frequent use of the FAT increases the average wear counts in Window 0 more quickly than in the other windows.
Consequently, the blocks in Window 0 have higher erase counts than those of other windows, as shown in
Therefore, it is useful to decrease the wear count in the first window (Window 0), so as to equalize the wear in all windows. As such, the endurance of the non-volatile memory will be increased.
The present invention provides a method of wear leveling for a non-volatile memory, by which the blocks of a window having higher wear counts will be allocated to other blocks in other windows, so that the wear in all windows can be substantially equalized and the endurance of the non-volatile memory will be increased.
According to the method of wear leveling for a non-volatile memory of the present invention, the non-volatile memory is divided into a plurality of windows, and a mapping table of the non-volatile memory allocates the logical block addresses having frequently accessed data to the plurality of windows equally. In an embodiment, the logical block addresses may store a file allocation table (FAT) or a directory table, therefore the windows they locate will be written or erased more frequently.
In an embodiment related to four windows, the plurality of windows comprise Windows 0, 1, 2 and 3, the logical block addresses comprise logical block addresses 0, 1, 2 and 3, and logical block addresses 0, 1, 2 and 3 point to Windows 0, 1, 2 and 3, respectively.
In accordance with the present invention, because the logical block addresses having frequently accessed data are allocated to the plurality of windows equally, the wear count will not be concentrated on a single window. Consequently, the endurance or lifetime of the non-volatile memory can be significantly increased.
Embodiments of the present invention will now be described with reference to the accompanying drawings.
Referring to
Assuming the physical block addresses pointed to by the logical block addresses L0, L1, L2 and L3 store system information such as the File Allocation Table (FAT) and/or directory table, the data is frequently accessed in the physical blocks directed by L0, L1, L2 and L3. In order to avoid the wear concentrating on Window 0, L1 is allocated to point to P1024, i.e., the first block of Window 1, L2 is allocated to point to P2048, and L3 is allocated to point to P3072. Then, other logical block addresses point to Window 0 first. When Window 0 is used completely, logical block addresses are allocated to Window 1. Likewise, the remaining logical block addresses are allocated to Window 2 and Window 3 when Window 1 and Window 2 are used completely. Accordingly, logical block addresses L4 to L1026 point to Window 0, logical block addresses L1027 to L2049 point to Window 1, logical block addresses L2050 to L3072 point to Window 2, and logical block addresses L3073 to L4095 point to Window 3. As a result, the erase count would be equalized among different windows as shown in
In practice, L0, L1, L2 and L3 are not limited to be directed to Window 0, Window 1, Window 2 and Window 3, respectively. As long as the four logical block addresses can be directed on a one-to-one basis to the four windows, e.g., logical block addresses L0, L1, L2 and L3 can be directed to Window 1, Window 0, Window 3 and Window 2 as shown in
In
A non-volatile memory of a large size may be divided into 8 windows as shown in
In summary, the present invention provides an efficient way to disperse the frequently accessed data to be equally allocated to different windows, thereby equalizing the wear count across windows and improving the endurance and lifetime of the non-volatile memory.
The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.