A divider may be used to calculate a Quotient, denoted Q, corresponding to division of a number, denoted P (also referred to as a “dividend”), by a divider, denoted D.
A conventional divider may implement a division algorithm, e.g., a Sweeney, Robertson and Tocher (SRT) division algorithm, which may include a series of division cycles, wherein a given cycle may yield a quotient digit.
The divider may include a Quotient-digit Selection Logic (QSL) for generating the quotient digit according to the value of a partial remainder of a previous division cycle, for example, based on a predetermined PD-Plot.
The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanied drawings in which:
It will be appreciated that for simplicity and clarity of illustration, elements shown in the drawings have not necessarily been drawn accurately or to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity or several physical components included in one functional block or element. Further, where considered appropriate, reference numerals may be repeated among the drawings to indicate corresponding or analogous elements. Moreover, some of the blocks depicted in the drawings may be combined into a single function.
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits may not have been described in detail so as not to obscure the present invention.
Unless specifically stated otherwise, as apparent from the following discussions, it is appreciated that throughout the specification discussions utilizing terms such as “processing,” “computing,” “calculating,” “determining,” or the like, refer to the action and/or processes of a computer or computing system, or similar electronic computing device, that manipulate and/or transform data represented as physical, such as electronic, quantities within the computing system's registers and/or memories into other data similarly represented as physical quantities within the computing system's memories, registers or other such information storage, transmission or display devices In addition, the term “plurality” may be used throughout the specification to describe two or more components, devices, elements, parameters and the like.
Reference is made to
According to some exemplary embodiments, platform 100 may include a processor 104. Processor 104 may include, for example, a Central Processing Unit (CPLU), a Digital Signal Processor (DSP), a microprocessor, a host processor, a plurality of processors, a controller, a chip, a microchip, or any other suitable multi-purpose or specific processor or controller.
According to some exemplary embodiments of the invention, processor 104 may include at least one Arithmetic Logic Unit (ALU) 105. ALU 105 may include at least one divider 120 able to determine a Quotient, denoted Q corresponding to a division of a dividend, denoted P, by a divider, denoted D, as described below.
According to some exemplary embodiments of the invention, platform 100 may also include an input unit 132, an output unit 133, a memory unit 134, and/or a storage unit 135. Platform 100 may additionally include other suitable hardware components and/or software components. In some embodiments, platform 100 may include or may be, for example, a computing platform, e.g., a personal computer, a desktop computer, a mobile computer, a laptop computer, a notebook computer, a terminal, a workstation, a server computer, a Personal Digital Assistant (PDA) device, a tablet computer, a network device, a micro-controller, a cellular phone, a camera, or any other suitable computing and/or communication device.
Input unit 132 may include, for example, a keyboard, a mouse, a touch-pad, or other suitable pointing device or input device Output unit 133 may include, for example, a Cathode Ray Tube (CRT) monitor, a Liquid Crystal Display (LCD) monitor, or other suitable monitor or display unit
Storage unit 135 may include, for example, a hard disk drive, a floppy disk drive, a Compact Disk (CD) drive, a CD-Recordable (CD-R) drive, or other suitable removable and/or fixed storage unit
Memory unit 134 may include, for example, a Random Access Memory (RAM), a Read Only Memory (ROM), a Dynamic RAM (DRAM), a Synchronous DRAM (SD-RAM), a Flash memory, a volatile memory, a non-volatile memory, a cache memory, a buffer, a short term memory unit, a long term memory unit, or other suitable memory units or storage units
According to some exemplary embodiments of the invention, divider 120 may determine the quotient Q using a division algorithm, e.g., a Sweeney, Robertson and Tocher (SRT) division algorithm as is known in the art, for performing x division cycles. A quotient Qm+1 of a division cycle m+1, m=0 . . . x, may be determined, for example, using the following recursive equations:
R0=P, Q0=0 (1)
Rm+1=rRm−qm+1D (2)
Qm+1=rQm+qm+1 (3)
wherein Rm denotes a partial remainder value corresponding to a previous cycle m, qm+1 denotes a quotient digit corresponding to cycle M+1, Rm+1 denotes a partial remainder value corresponding to cycle M+1, Qm denotes a quotient corresponding to cycle m, and r denotes a radix of divider 120. The radix r may be determined, for example, by the following equation:
r=2p (4)
wherein p denotes a value related to the number of bits of the quotient digit qm+1.
According to some exemplary embodiments of the invention, divider 120 may include a quotient digit selector 129 to generate quotient digit qm+1 by applying a predetermined criterion to a plurality of expected partial remainder values related to a plurality of possible quotient digits, e.g., as described in detail below.
According to some exemplary embodiments of the invention, divider 120 may also include a main loop module 127 to determine the quotient Qm+1 and/or the partial remainder Rm+1, e.g., in accordance with Equations 1, 2, and/or 3. Main loop module 127 may include any suitable configuration, for example, a configuration including one or more adders, multiplexers, Carry-Save-Adders (CSAs), latches, flip flop units, and/or any other element, eg., as is known in the art..
According to some exemplary embodiments of the invention, divider 120 may include a high-radix divider, e.g., having a radix of at least four. Accordingly, quotient digit selector 129 may generate two or more bits representing quotient digit qm+1, as described below.
Although the scope of the present invention is not limited in this respect, as part of the description of some embodiments of the present invention, reference may be made to a high radix divider, e.g., a divider having a radix r≧4. However, it would be obvious to those with ordinary skills in the art of that other embodiments of the invention may include a low-radix divider, e.g., a divider having a radix r=2.
Reference is made to
Although the invention is not limited in this respect, quotient digit selector 200 may perform the functionality of quotient digit selector 129 (
According to exemplary embodiments of the invention, quotient digit selector 200 may generate quotient digit qm+1 by applying a predetermined criterion to a plurality of expected partial remainder values related to a plurality of possible quotient digits, e.g., as described in detail below.
According to some exemplary embodiments of the invention, the plurality of possible quotient digits may correspond to a plurality of predetermined integer values, i=l+1, l, . . . , h, e.g., wherein (−r)≦l and h≦r are predetermined boundary values. The boundary values l and/or h may be predetermined, for example, according to a convergence criterion and/or any other desired criterion, e.g., a desired efficiency level and/or a desired accuracy level of the division operation, as described below.
According to some exemplary embodiments of the invention, the quotient digit qm+1 may be generated such that an absolute value of partial remainder Rm+1 corresponding to quotient digit qm+1 is relatively reduced, e.g., minimized. This may be achieved, for example, by detecting a change in a mathematical property, e.g., a sign, of expected partial remainder values corresponding to two consecutive separator values related to the possible partial remainder values; and generating the quotient digit based on the detected change in property, as described below.
According to exemplary embodiments of the invention, the plurality of expected partial remainder values of the cycle m+1 may include a plurality of values, denoted R im+1, corresponding to a plurality of separator values ci. Separator values ci may be related to the plurality of integer values i, respectively. For example, the plurality of separator values may be shifted by a predetermined shift value in relation to the plurality of possible quotient digits, e.g., such that there is one of integer values i between each pair of consecutive separators, ci and ci+1. The separator values may be determined, for example, based on the convergence criterion, e.g., as described below.
According to exemplary embodiments of the invention, a change between the signs of two expected partial remainder values corresponding to two consecutive integer values, j and j+1, may indicate the partial remainder Rm+1 may be relatively reduced, e.g., minimized, by generating a quotient digit qm+1 corresponding to one of the values j and j+1. The plurality of separator values may be implemented, for example, to determine one of the two consecutive values j and j+1 for which the partial remainder value Rm+1 may be relatively reduced, e.g., minimized. For example, a change of sign between two expected partial remainder values corresponding to two consecutive separators, cj and cj+1, may indicate that the partial remainder value Rm+1 may be reduced, e.g., minimized, by generating the quotient digit qm+1 corresponding to the integer value 1, which may be between separators cj and cj+1.
According to some exemplary embodiments of the invention, quotient digit selector 200 may include a partial-remainder generator 204 to generate the plurality of expected partial remainder values corresponding to division cycle m+1, for example, based on data signals 208 and/or 211. Data signals 208 and/or 211 may be received, for example, from main loop module 127 (
Generator 204 may generate signals 212 and/or 214 corresponding to the values Rim+1, for example, using the following equation:
Rim+1=rRim−ciD (5)
wherein Rim denotes the expected partial remainder value of the cycle m corresponding to integer value i. Generator 214 may include any suitable configuration, e.g., as described below with reference to
According to some exemplary embodiments of the invention, data 208 and/or data 211 may include truncated data in a redundant form. For example, data 208 may correspond to a predetermined truncation number, n, of most-significant bits of the product rRm in a redundant form. Data 211 may include, for example, n most-significant bits of one or more values corresponding to dividend D, as described below Accordingly, signals 214 and 212 may correspond to truncated expected partial remainder values in a redundant form. The truncation number n may be determined, for example, based on the convergence criterion and/or any other criterion, e.g., a desired efficiency and/or accuracy level of the division operation, as described below.
According to some exemplary embodiments of the invention, selector 200 may also include a sign generator 216 for generating a plurality of sign signals 220 corresponding to the plurality of expected partial remainder values, respectively. Generator 216 may include any suitable configuration, e.g., as described below with reference to
According to some exemplary embodiments of the invention, selector 200 may also include a detector 218 to detect a change between the signs represented by signals 220. For example, detector 218 may compare the value of one or more pairs of sign signals 220 corresponding to consecutive separator values. Detector may generate one or more indication signals 222 having a value indicative of a change of sign between two consecutive signals 220. Detector 218 may include any suitable detection configuration, e.g., as described below with reference to
According to some exemplary embodiments of the invention, selector 200 may also include a quotient digit generator 202 to generate quotient digit qm+1, e.g., based on one or more of indication signals 222. For example, indication signals 222 may indicate a change between two signs, denoted sj and sj+1, of expected partial remainder values Rim+1 and Rj+1m+1 corresponding to two separator values cj and cj+1, respectively Accordingly, quotient bit generator 202 may generate quotient digit qm+1 e.g., according to the following conditions:
qm+1=j if j:[l+1 . . . h]
qm+1=l if j=l−1 (6)
qm+1=h if j=h−1
The generated quotient digit qm+1 may be provided, for example, to main loop 127 (
Reference is made to
Although the scope of the present invention is not limited in this respect, according to some exemplary embodiments of the invention, partial remainder generator 300, sign generator 330, and/or detector 370 may be implemented as part of a quotient digit selector, e.g., selector 129, for generating a quotient digit qm+1 corresponding to one of seventeen possible quotient digits. Accordingly partial remainder generator 300, sign generator 330 and/or detector 370 may be implemented, for example, as part of a quotient selector for performing a division operation of a radix of eight or more. However, it will be appreciated by those skilled in the art, that in other embodiments of the invention partial remainder generator 300, sign generator 330, and/or detector 370 may be modified to enable generating a quotient digit qm+1 corresponding to one of any other desired number of possible quotient digits.
According to the exemplary embodiments of
According to some exemplary embodiments of the invention, generator 300 may include a plurality of 3:2 CSAs to receive a plurality of signals corresponding to a plurality of products of the divider D and the integer values i, respectively The plurality of CSAs may also receive a pair of input signals 310 and 311 corresponding to the difference rRM−D/2. For example, signal 310 may have a value corresponding to the carry value of the difference rRm−D/2, and signal 311 may have a value corresponding to the save value of the difference rRm−D/2. Signals 310 and/or 311 may be generated using any suitable method. For example, the value D/2 may be determined by performing a “right shift” to the value of D, which may be received from main loop module 127 (
According to the exemplary embodiments of
According to some exemplary embodiments of the invention, generator 330 may include a plurality of adders to receive the plurality of carry-save signal pairs representing the plurality of expected partial remainders; and generate a plurality of sign signals corresponding to the signs of the plurality of expected partial remainders, respectively. For example, a sign signal corresponding to an expected partial remainder value may have a zero value, e.g., if the expected partial remainder is positive; or a value of one, e.g., if the expected partial remainder is negative.
According to the exemplary embodiments of
According to some exemplary embodiments of the invention, detector 370 may include a plurality of exclusive-or (XOR) gates to receive the plurality of sign signals representing the signs of the plurality of expected partial remainders; and generate a plurality of indication signals having values indicative of a change between the signs of two consecutive expected partial remainder values.
According to the exemplary embodiments of
According to some exemplary embodiments of the invention, one of the indication signals may have a value one, while other indication signals may have the value zero. Generating the quotient bit qm+1, based on a possible quotient digit corresponding to the indication signal having the value one, may result in a relatively reduced, e.g., minimal, partial remainder Rm+1. For example, if signal 379 has a value of one, then the sign of expected partial remainder rRm−5.5D, which corresponds to separator value C−6=5.5, may be different than the sign of expected partial remainder value rRm−6.5D, which corresponds to separator value C−7=−6.5. This may indicate that generating quotient digit qm+1=−6 may result in a reduced, e.g., minimal, partial remainder value Rm+1 compared to the partial remainder values resulting from the other possible quotient digits.
Some exemplary embodiments of the invention, e.g., as described herein, relate to generating one or more of the expected partial remainder values based on Equation 5, and using a sign generator, e.g., sign generator 330, and/or a detector, e.g., detector 370, adapted for detecting a change of sign between the expected partial remainder values. However, it will be appreciated by those skilled in the art that the expected partial remainder values may be determined using any other suitable equation and/or method. For example, one or more of the expected partial remainder values may be generated according to the equation Rim+1=ciD−rRim. The sign generator and/or the detector may be modified, according to the equation and/or method used for generating the expected partial remainder values. For example, signal 373 may have a value corresponding to the sign of the value D, and/or signal 389 may have a value corresponding to the sign of the value (−D), e.g., if one or more of the expected partial remainder values are generated according to the equation Rim+1=ciD−rRim.
Reference is made to
Although the scope of the present invention is not limited in this respect, according to some exemplary embodiments of the invention, quotient digit generator 400 may be implemented as part of a quotient digit selector, e.g., selector 129, for generating a five-bit quotient digit qm+1, corresponding to one of seventeen possible quotient digits, e.g., corresponding to the values −8, −7, −6, −5, −4, −3, −2, −1, 0, 1, 2, 3, 4, 5, 6, 7 and 8. Accordingly generator 400 may be implemented, for example, as part of a quotient selector for performing a division operation of a radix of eight or more. However, it will be appreciated by those skilled in the art, that in other embodiments of the invention quotient digit generator 400 may be modified to enable generating any other quotient digit qm+1.
According to the exemplary embodiments of
According to some exemplary embodiments of the invention, one or more of the truncation number n and the boundary values l and h, may be predetermined based on one or more criterions. The one or more criterions may include, for example, a criterion corresponding to a convergence of the division operation, a desired efficiency level of the division operation, and/or a desired accuracy level of the division cycle, as described in detail below.
According to some exemplary embodiments of the invention, one or more of the expected partial remainder values may be determined using a truncated redundant form, e.g., including 17 bits after a fixed point of the redundant representation, as described above. Accordingly, the following equation may be used, for example, for representing the partial remainder corresponding to separator ci:
ciD−rRm−Ai+Ei (7)
wherein Ai denotes the truncated expected partial remainder corresponding to separator ci, and Ei denotes a truncation error. The truncated expected partial remainder may be represented, for example, as follows:
Ai=αpαp−1 . . . α0·α−1 . . . α−n (8)
The sign of the expected partial remainder corresponding to separator ci may be determined, for example, as follows:
Sign (ciD−rRm)=αp (9)
Sign values sj corresponding to expected partial remainder value Rjm+1, wherein j=1 . . . h, may be determined, for example, based on the following conditions:
s1=sign (−D)
si=sign(ciD−rRm) for i−l+1, . . . h−1 (10)
sh=sign(D)
According to some exemplary embodiments of the invention, a change between signs si and si+1, i.e., si≠si+1, may indicate that Ai+1≧0 and Ai<0, which in turn may be equivalent to:
Ai≦2−n (11)
Substituting Equation 11 into Equation 7 may result in:
ciD−rRm≦Ei−2−n
ci+1D−rRm≧Ei+1 (12)
which may be equivalent to:
ciD−Ei+2−n≦rRm≦ci+1D−Ei+1 (13)
Equation 13 may be equivalent to the following equation, e.g., since ci<i≦ci+1:
(ci−i)D−Ei2−n≦rRm−iD≦(ci+1−i)D−Ei+1 (14)
The partial remainder Rm+1, may be in the interval a≦Rm+1≦b, and the quotient digit qm+1 may be in the interval l≦qm+1<h, e.g., if the partial remainder Rm is in the interval a<Rm<b, wherein:
and wherein:
Substituting Equations 15 and 16 into Equation 14 may yield the following convergence criterion:
Substituting i+1 with i in Equation set 17 may yield the following convergence criterion:
Equation 18 may be rearranged as follows:
According to some exemplary embodiments of the invention, one or more of truncation number n, and limit values l and/or h, may be determined based on the convergence criterion of Equation 19, e.g., as described below.
According to one exemplary embodiment of the invention, the limit values l=−8 and h=8 may be selected, e.g., if r=16. Thus, according to Equation 19, the plurality of separator values ci may be selected within the following interval:
Selecting the truncation n=p+1=5, may result in the following separator values:
It is noted that the element 1/32D of Equation 21 may not depend on i. Accordingly, the separator values may be determined as follows:
Accordingly, the truncation error may be within the interval:
According to another exemplary embodiment of the invention, the limit values l=−8 and h=8 may be selected, e.g., if r=−8. Thus, according to Equation 19, the plurality of separator values ci may be selected within the following interval:
Selecting the truncation n=0, i.e., truncation of the fractional part of the partial remainder, may enable using the following separator values:
ci=i, −8<i≦8 (25)
Accordingly, the truncation error may be within the interval:
According to a further exemplary embodiment of the invention, the limit values l=−4 and h=4 may be selected, e.g., if r=4. Thus, according to Equation 19, the plurality of separator values ci may be selected within the following interval:
Selecting the truncation n=0, i.e., truncation of the fractional part of the partial remainder, may enable using the separator values ci=i.
Accordingly, the truncation error may be within the interval:
Reference is made to
As indicated at block 500 the method may include generating quotient digit qm+1 corresponding to a quotient of cycle m+1 by applying a predetermined criterion to a plurality of expected partial remainder values related to a plurality of possible quotient digits. Generating quotient digit qm+1 may include, for example, using a quotient digit selector, e.g., selector 200 as described above with reference to
As indicated at block 502, generating quotient digit qm+1 may include generating the plurality of expected partial remainder values. Generating the plurality of expected partial remainder values may include generating a plurality of expected partial remainder values corresponding to a plurality of separator values, which may be related to the plurality of possible quotient digits. Generating the plurality of expected partial remainder values may include, for example, using a partial remainder generator, e.g., generator 300 as described above with reference to
As indicated at block 503, generating quotient digit qm+1 may include determining at least one property, e.g., a sign, of one or more of the expected partial remainder values. Determining the sign of one or more of the expected partial remainder values may include, for example, using a sign generator, e.g., generator 330 as described above with reference to
As indicated at block 504, generating quotient digit qm+1 may include detecting a change in a mathematical property between one or more pairs of values of the plurality of expected partial remainder values. For example, the method may include detecting a change of sign between two expected partial remainder values. This may be achieved, for example, by comparing one or more pairs of consecutive sign values. Detecting the change of sign may include, for example, using detector, e.g., detector 370 as described above with reference to
As indicated at block 506, generating quotient digit qm+1 may include generating quotient digit qm+1 based on the detected change in property. Generating the quotient digit based on the detected change in property may include, for example, using a quotient digit generator, e.g., generator 400 as described above with reference to
Embodiments of the present invention may be implemented by software, by hardware, or by any combination of software and/or hardware as may be suitable for specific applications or in accordance with specific design requirements. Embodiments of the present invention may include units and sub-units, which may be separate of each other or combined together, in whole or in part, and may be implemented using specific, multi-purpose or general processors, or devices as are known in the art. Some embodiments of the present invention may include buffers, registers, storage units and/or memory units, for temporary or long-term storage of data and/or in order to facilitate the operation of a specific embodiment.
While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents may occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.
What is claimed is: