Rosen et al. Global Value Numbers and Redundant Computations. ACM. pp. 12-27, Jan. 1988. |
Gupta. Code Optimization as a Side Effect of Instruction Scheduling. High Performance Computing, 1997. Proceedings. Fourth International Conference. pp. 370-377, Dec. 1997. |
Choi et al. Scheduling of Conditional Branches Using SSA From for Superscalar/VLIW Processors. IEEE. pp. 344-351, Jun. 1996. |
Park et al. Evolution of Scheduling Techniques on a SPARC-Based VLIW Testbed. IEEE. pp. 104-113, Jan. 1997. |
Gupta et al. Path Profile Guided Partial Redundancy Elimination Using Speculation. IEEE. pp. 230-239, Feb. 1998. |
Chow et al., "A New Algorithm for Partial Redundancy Elimination based on SSA Form", Proceedings of the ACM SIGPLAN '97 Conference on Programming Language Design and Implemention, pp. 273-286, Jun. 1997. |
Gupta et al, "Path Profile Guided Dead Code Elimination Using Prediction", Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, pp. 102-113, Nov. 1997. |
Gupta et al., "Resource-Sensitive Profile-Directed Data Flow Analysis for Code Optimization", Proceedings of the 30.sup.th Annual International Symposium on Microarchitecture, pp. 358-368, Dec. 1997. |