Patent Grant
7478031
The present invention relates, in general, to integrated circuits and systems of integrated circuits. More particularly, the present invention relates to a method, system and program for developing and scheduling adaptive integrated circuitry having fixed, application specific computational elements and also corresponding control or configuration information.
This application is related to Paul L. Master et al., U.S. patent application Ser. No. 09/815,122, entitled “Adaptive Integrated Circuitry With Heterogeneous And Reconfigurable Matrices Of Diverse And Adaptive Computational Units Having Fixed, Application Specific Computational Elements”, filed Mar. 22, 2001, commonly assigned to QuickSilver Technology, Inc., and incorporated by reference herein, with priority claimed for all commonly disclosed subject matter (the “first related application”).
This application is also related to Eugene Hogenauer, U.S. patent application Ser. No. 09/872,397, entitled “Method and System for Scheduling in an Adaptable Computing Engine”, filed May 31, 2001, commonly assigned to QuickSilver Technology, Inc., and incorporated by reference herein, with priority claimed for all commonly disclosed subject matter (the “second related application”).
This application is further related to Paul L. Master et al., U.S. patent application Ser. No. 09/997,987, entitled “Apparatus, Method, System and Executable Module For Configuration and Operation Of Adaptive Integrated Circuitry Having Fixed, Application Specific Computational Elements”, filed Nov. 30, 2001, commonly assigned to QuickSilver Technology, Inc., and incorporated by reference herein, with priority claimed for all commonly disclosed subject matter (the “third related application”).
The first related application discloses a new form or type of integrated circuitry which effectively and efficiently combines and maximizes the various advantages of processors, application specific integrated circuits (“ASICs”), and field programmable gate arrays (“FPGAs”), while minimizing potential disadvantages. The first related application illustrates a new form or type of integrated circuit (“IC”), referred to as an adaptive computing engine (“ACE”), which provides the programming flexibility of a processor, the post-fabrication flexibility of FPGAs, and the high speed and high utilization factors of an ASIC. This ACE integrated circuitry is readily reconfigurable or adaptive, in advance, in real-time or potentially slower, is capable of having corresponding, multiple modes of operation, and further minimizes power consumption while increasing performance, with particular suitability for low power applications, such as for use in hand-held and other battery-powered devices.
The adaptive computing engine (“ACE”) circuit of the first related application, for adaptive or reconfigurable computing, includes a plurality of heterogeneous computational elements coupled to an interconnection network, rather than the homogeneous units of FPGAs. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time or potentially slower to adapt and re-adapt (configure and reconfigure) the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. In turn, this configuration and reconfiguration of heterogeneous computational elements, forming various computational units and adaptive matrices (or adaptive nodes), in real-time or across time, generates the selected operating mode of the ACE integrated circuit, for the performance of a wide variety of tasks.
This ACE integrated circuit, as indicated above, is controlled by a series or sequence of bits, referred to as “configuration information”, which generates the configurations and reconfigurations which provide and create one or more operating modes for the ACE circuit, such as wireless communication, radio reception, personal digital assistance (“PDA”), MP3 music playing, or other desired functions.
Current system development tools, typically embodied as computer programs, do not address the particular needs and difficulties of designing ACE circuitry, and developing and scheduling configuration information to allow the ACE IC to perform a selected operating mode. As a consequence, a need remains for a suite of development tools which may design and develop ACE circuitry, adapt one or more algorithms for performance on ACE circuitry, schedule a selected algorithm for execution on selected ACE computational elements, and generate a bit file (as configuration information) for control of the ACE circuitry for the selected operating mode.
The present invention provides a method, system and program for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit.
The exemplary method (and program) begins with selecting an algorithm for performance by the adaptive computing integrated circuit, such as one or more algorithms which may be used in mobile communications, for example. The algorithm also may be profiled for performance on the adaptive computing integrated circuit.
A plurality of adaptive computing descriptive objects (“ADOs”) are then determined. In general, an ADO includes a description of a function, the I/O for the function, a description of a memory resource for the function, the I/O for the memory resource, and a connection between the function and the memory resource. The types of functions which may form an ADO include linear operations, such as addition and multiplication; non-linear operations such as discrete cosine transformation; finite state machine operations; control sequences; bit level manipulations; memory, and memory management.
The method and system then schedule the algorithm with the plurality of adaptive computing descriptive objects to produce a scheduled algorithm and a selected adaptive computing circuit version. Preferably, this includes generating a plurality of adaptive computing circuit versions from the plurality of adaptive computing descriptive objects; scheduling the algorithm with the plurality of adaptive computing descriptive objects of each of the plurality of adaptive computing circuit versions; and using a selection parameter of a plurality of selection parameters, selecting an adaptive computing circuit version, of the plurality of adaptive computing circuit versions, to form the selected adaptive computing circuit version. The plurality of selection parameters, in general, include power consumption, speed of operation, latency, bandwidth requirements, a competing operating mode, and versatility for a plurality of operating modes.
The selected adaptive computing circuit version is converted to a hardware description language for subsequent fabrication to form the adaptive computing integrated circuit. From the scheduled algorithm and the selected adaptive computing circuit version, the method and system generate the configuration information for the performance of the algorithm by the adaptive computing integrated circuit. In the exemplary embodiment, the configuration information is compiled into an adaptive computing integrated circuit bit file, for loading into the adaptive computing integrated circuit.
In the exemplary embodiment, a plurality of versions (or libraries) of configuration information are generated, with each configuration information version corresponding to a selection parameter of a plurality of selection parameters. The plurality of selection parameters include a competing operating mode, versatility for a plurality of operating modes, a selected operational feature set of a plurality of operational feature sets, selected operating conditions of a plurality of operating conditions, and a selected adaptive computing circuit version of a plurality of adaptive computing circuit versions.
This capability for numerous configuration information versions or libraries creates significant versatility for the adaptive computing integrated circuit, for one or more selected operating modes, different hardware versions, different feature sets, different operating conditions, and pre-existing operating modes. An entire library or database of these versions of configuration information may be created in advance or in real time, for each of these different considerations. In addition, additional versions may also be created for different operating conditions, such as power consumption, latency, speed of operation, and bandwidth considerations. A library of such versions (as “multiple binaries”) may be stored in multiple locations, such as on a network server, for download into a given adaptive computing circuit by a corresponding service provider.
All of the various processes of the present invention may run off a single set of descriptions, the adaptive computing descriptive objects (or ADOs), for any number of different operating modes, with corresponding algorithms bound-to the hardware through the scheduling process.
Numerous other advantages and features of the present invention will become readily apparent from the following detailed description of the invention and the embodiments thereof, from the claims and from the accompanying drawings.
The foregoing and other objects, features and advantages of the present invention will be more readily appreciated upon reference to the following disclosure when considered in conjunction with the accompanying drawings, in which:
While the present invention is susceptible of embodiment in many different forms, there are shown in the drawings and will be described herein in detail specific embodiments thereof, with the understanding that the present disclosure is to be considered as an exemplification of the principles of the invention and is not intended to limit the invention to the specific embodiments illustrated.
As indicated above, a need remains for a method, program and system to design an ACE circuit, including determining the type, number, placement, and matrix interconnection network (“MIN”) routing of or for computational units 200 and computational elements 250, for subsequent fabrication into an integrated circuit. Similarly, how such computational units 200 and computational elements 250 are to be configured and reconfigured to perform a given task must also be determined. In accordance with the present invention, these two sets of tasks occur approximately jointly and interactively, optimizing the IC for a plurality of functions and operating modes. In addition, the present invention enables further IC optimization for speed, size, utilization factors, and power consumption, with additional emphasis on enabling concurrent or parallel computing across multiple computational units 200 and computational elements 250.
In the following discussion, the adaptive integrated circuit (ACE) is described in detail with reference to
A significant departure from the prior art, the ACE 100 does not utilize traditional (and typically separate) data, direct memory access (DMA), random access, configuration and instruction busses for signaling and other transmission between and among the reconfigurable matrices 150, the controller 120, and the memory 140, or for other input/output (“I/O”) functionality. Rather, data, control and configuration information are transmitted between and among these matrix 150 elements, utilizing the matrix interconnection network 110, which may be configured and reconfigured, to provide any given connection between and among the reconfigurable matrices 150, including those matrices 150 configured as the controller 120 and the memory 140, as discussed in greater detail below.
It should also be noted that once configured, the MIN 110 also and effectively functions as a memory, directly providing the interconnections for particular functions, until and unless it is reconfigured. In addition, such configuration and reconfiguration may occur in advance of the use of a particular function or operation, and/or may occur in real-time or at a slower rate, namely, in advance of, during or concurrently with the use of the particular function or operation. Such configuration and reconfiguration, moreover, may be occurring in a distributed fashion without disruption of function or operation, with computational elements in one location being configured while other computational elements (having been previously configured) are concurrently performing their designated function. This configuration flexibility of the ACE 100 contrasts starkly with FPGA reconfiguration, both which generally occurs comparatively slowly, not in real-time or concurrently with use, and which must be completed in its entirety prior to any operation or other use.
The matrices 150 configured to function as memory 140 may be implemented in any desired or preferred way, utilizing computational elements (discussed below) of fixed memory elements, and may be included within the ACE 100 or incorporated within another IC or portion of an IC. In the exemplary embodiment, the memory 140 is included within the ACE 100, and preferably is comprised of computational elements which are low power consumption random access memory (RAM), but also may be comprised of computational elements of any other form of memory, such as flash, DRAM, SRAM, SDRAM, MRAM, FeRAM, ROM, EPROM or E2PROM. As mentioned, this memory functionality may also be distributed across multiple matrices 150, and may be temporally embedded, at any given time, as a particular MIN 110 configuration. In addition, in the exemplary embodiment, the memory 140 preferably includes direct memory access (DMA) engines, not separately illustrated.
The controller 120 is preferably implemented, using matrices 150A and 150B configured as adaptive finite state machines, as a reduced instruction set (“RISC”) processor, controller or other device or IC capable of performing the two types of functionality discussed below. The first control functionality, referred to as “kernel” control, is illustrated as kernel controller (“KARC”) of matrix 150A, and the second control functionality, referred to as “matrix” control, is illustrated as matrix controller (“MARC”) of matrix 150B.
The matrix interconnection network 110 of
The various matrices or nodes 150 are reconfigurable and heterogeneous, namely, in general, and depending upon the desired configuration: reconfigurable matrix 150A is generally different from reconfigurable matrices 150B through 150N; reconfigurable matrix 150B is generally different from reconfigurable matrices 150A and 150C through 150N; reconfigurable matrix 150C is generally different from reconfigurable matrices 150A, 150B and 150D through 150N, and so on. The various reconfigurable matrices 150 each generally contain a different or varied mix of adaptive and reconfigurable computational (or computation) units (200,
The ACE architecture utilizes a plurality of fixed and differing computational elements, such as (without limitation) correlators, multipliers, complex multipliers, adders, demodulators, interconnection elements, routing elements, combiners, finite state machine elements, reduced instruction set (RISC) processing elements, bit manipulation elements, input/output (I/O) and other interface elements, and the lower-level “building blocks” which form these units, which may be configured and reconfigured, in response to configuration information, to form the functional blocks (computational units and matrices) which may be needed, at any given or selected time, to perform higher-level functions and, ultimately, to execute or perform the selected operating mode, such as to perform wireless communication functionality, including channel acquisition, voice transmission, multimedia and other data processing. Through the varying levels of interconnect, corresponding algorithms are then implemented, at any given time, through the configuration and reconfiguration of fixed computational elements (250), namely, implemented within hardware which has been optimized and configured for efficiency, i.e., a “machine” is configured in real-time which is optimized to perform the particular algorithm.
Next, the present invention also utilizes a tight coupling (or interdigitation) of data and configuration (or other control) information, within one, effectively continuous stream of information. This coupling or commingling of data and configuration information, referred to as “silverware” or as a “silverware” module, is the subject of the third related application. For purposes of the present invention, however, it is sufficient to note that this coupling of data and configuration information into one information (or bit) stream, which may be continuous or divided into packets, helps to enable real-time reconfigurability of the ACE 100, without a need for the (often unused) multiple, overlaying networks of hardware interconnections of the prior art. For example, as an analogy, a particular, first configuration of computational elements at a particular, first period of time, as the hardware to execute a corresponding algorithm during or after that first period of time, may be viewed or conceptualized as a hardware analog of “calling” a subroutine in software which may perform the same algorithm. As a consequence, once the configuration of the computational elements has occurred (i.e., is in place), as directed by (a first subset of) the configuration information, the data for use in the algorithm is immediately available as part of the silverware module. The same computational elements may then be reconfigured for a second period of time, as directed by second configuration information (i.e., a second subset of configuration information), for execution of a second, different algorithm, also utilizing immediately available data. The immediacy of the data, for use in the configured computational elements, provides a one or two clock cycle hardware analog to the multiple and separate software steps of determining a memory address and fetching stored data from the addressed registers. This has the further result of additional efficiency, as the configured computational elements may execute, in comparatively few clock cycles, an algorithm which may require orders of magnitude more clock cycles for execution if called as a subroutine in a conventional microprocessor or DSP.
This use of silverware modules, as a commingling of data and configuration information, in conjunction with the reconfigurability of a plurality of heterogeneous and fixed computational elements 250 to form adaptive, different and heterogeneous computation units 200 and matrices 150, enables the ACE 100 architecture to have multiple and different modes of operation. For example, when included within a hand-held device, given a corresponding silverware module, the ACE 100 may have various and different operating modes as a cellular or other mobile telephone, a music player, a pager, a personal digital assistant, and other new or existing functionalities. In addition, these operating modes may change based upon the physical location of the device. For example, while configured for a first operating mode, using a first set of configuration information, as a CDMA mobile telephone for use in the United States, the ACE 100 may be reconfigured using a second set of configuration information for an operating mode as a GSM mobile telephone for use in Europe.
Referring again to
Continuing to refer to
Continuing to refer to
In the exemplary embodiment, the various computational elements 250 are designed and grouped together, into the various adaptive and reconfigurable computation units 200. In addition to computational elements 250 which are designed to execute a particular algorithm or function, such as multiplication, correlation, clocking, synchronization, queuing, sampling, or addition, other types of computational elements 250 are also utilized in the exemplary embodiment. As illustrated in
With the various types of different computational elements 250 which may be available, depending upon the desired functionality of the ACE 100, the computation units 200 may be loosely categorized. A first category of computation units 200 includes computational elements 250 performing linear operations, such as multiplication, addition, finite impulse response filtering, clocking, synchronization, and so on. A second category of computation units 200 includes computational elements 250 performing non-linear operations, such as discrete cosine transformation, trigonometric calculations, and complex multiplications. A third type of computation unit 200 implements a finite state machine, such as computation unit 200C as illustrated in
In the exemplary embodiment, in addition to control from other matrices or nodes 150, a matrix controller 230 may also be included or distributed within any given matrix 150, also to provide greater locality of reference and control of any reconfiguration processes and any corresponding data manipulations. For example, once a reconfiguration of computational elements 250 has occurred within any given computation unit 200, the matrix controller 230 may direct that that particular instantiation (or configuration) remain intact for a certain period of time to, for example, continue repetitive data processing for a given application.
As may be apparent from the discussion above, the design of an adaptive computing circuit, such as an ACE 100 circuit, including determining the type, number, placement, and MIN routing of or for computational units 200 and computational elements 250, for subsequent fabrication into an integrated circuit, may be a daunting task. Similarly, how such computational units 200 and computational elements 250 are to be configured and reconfigured to perform a given task must also be determined. In accordance with the present invention, these two sets of tasks occur approximately jointly and interactively, optimizing the adaptive computing IC for a plurality of functions and operating modes. In addition, the present invention enables further IC optimization for speed, size, utilization factors, and power consumption, with additional emphasis on enabling concurrent or parallel computing across multiple computational units 200 and computational elements 250. (It should be noted that optimization is used herein in a very broad sense, to mean and include merely desired or acceptable for one or more purposes, for example, and not just meaning “most” desired or favorable.)
As a consequence, the method proceeds to step 305, to select or generate the desired algorithm, function or program. Preferably jointly, the method also proceeds to generate one or more descriptions of a plurality of computational elements 250 and computational units 200, step 310, preferably as hardware descriptions, to form “objects” referred to as adaptive computing (or ACE) descriptive objects (“ADOs”) in the exemplary embodiment, and which preferably function as “objects” within the method of the invention, as objects are generally defined and used in object oriented programming languages and systems.
In the exemplary embodiment, the algorithm, function or program selection or generation step 305 is conducted using a comparatively high-level language, such as the C or C++ programming languages, or the “Q” language which is the subject of a related patent application. For example, a given algorithm or function may be programmed in C, C++ or Q. Alternatively, there may be existing C or C++ programs, and even engineering standards expressed in C or C++, which are or have been selected for execution on an ACE 100 or other adaptive computing circuit. Such programs or code, especially legacy code designed for execution on a processor, are not necessarily optimized for execution on an ACE 100 or other adaptive computing circuit. As a consequence, the selected programs or algorithms of step 305 are then profiled and optimized for comparatively optimal execution an ACE 100 or other adaptive computing circuit in step 315. For selected programs or algorithms of step 305 which have already been designed or developed for an adaptive computing circuit such as the ACE 100, the method may proceed directly to step 335 (bypassing the profiling and other intervening steps 315, 320, 325 and 330).
The profiling of step 315 analyzes the program code or other algorithm based upon a plurality of data parameters (or data metrics), with identification of the corresponding algorithmic element. While profiling on the basis of data parameters is the subject of another related patent application, the plurality of data parameters may comprise one or more of the following parameters, in addition to other forms of data measurement:
data location (for static data), such as a memory or register location;
data type, such as input data, intermediate calculation data, output data, other forms of operand data, and so on;
data size (input and output), such as number of bits, bandwidth required (bus or interconnect width), which may also be a function of or otherwise related to data type;
data source and destination locations (for dynamic data), such as memory or register locations;
data pipeline length, such as how long a data stream is;
locality of reference, such as how far the data is from the computing elements which will process or use it;
distance of data movement (for dynamic data), such as a distance between various caches, registers, or other memory locations, and/or the distance the data moves between or among the lines of code being profiled;
speed of data movement (for dynamic data), namely, how fast was the data able to be moved from a source location to a computing element and/or to a destination location, such as the number of computation cycles utilized in the data transfer;
data access frequency, such as how often was the data accessed;
data loads and stores (load/stores) into registers, caches or other memory;
degree of cache, register or memory usage; and
data persistence, such as how long did the data remain in use, either unchanged or as (repeatedly) modified and used.
Based upon the results of profiling using the data parameters (i.e., profiled data parameter results or measured data parameters), portions of the profiled code are selected for execution on the adaptive computing architecture, step 320. The profiling statistics are calculated iteratively in the exemplary embodiment, as portions of code are identified as capable of acceleration in the ACE hardware, and subsequently removed from the program code. The profiling process is repeated until optimal performance of the configuration and the ACE architecture is achieved, step 325. Those of skill in the art will realize that this iterative profiling process may also be expressed through one or more other conditional statements or expressions. In addition, those of skill in the art will also recognize that other forms of profiling may also be utilized, in lieu of or in addition to the exemplary data profiling of the present invention, and are within the scope of the present invention.
In the exemplary embodiment, data parameters for the profiling of step 315 include one or more of the following attributes, as mentioned above: data location (for static data), data type, data size (input and output), data source and destination locations (for dynamic data), data pipeline length, locality of reference, distance of data movement, speed of data movement, data access frequency, number of data load/stores, degree of cache, register or memory usage, and data persistence.
In the exemplary embodiment, all of the algorithm or program is ultimately selected for execution in the adaptive computing circuit, such as the ACE 100. In other embodiments, however, portions of the algorithm or program which may not be selected for execution in the ACE 100 in step 320 may be selected for execution in a processor, such as a RISC processor, step 330, when such a processor is available or desirable in the selected embodiment.
Following step 305 or step 325, the algorithms, functions or programs for execution on an adaptive computing circuit, such as the ACE 100, are then “scheduled” in step 335, as discussed in greater detail below.
Independently of steps 305 and 315 through 330, the “hardware” descriptions are generated in step 310, preferably as adaptive computing (ACE) descriptive objects (ADOs). Step 310 may occur at any time, such as before, concurrently with or subsequent to steps 305 and 315 through 330. In the exemplary embodiment, a plurality of adaptive computing descriptive objects are defined and generated using a comparatively high-level language such as Java, and are stored in a library or other database for subsequent use in the method, such as in steps 335, 340 and 345, discussed below. Such adaptive computing descriptive objects, for example, may describe an adder, its inputs and outputs, a register file and its inputs and outputs, and how the adder and register file are to be connected to each other. Such ADOs are generated for every type of computational element, and the number of such ADOs is generally only limited by the number of matrices 150 which are to be available in the IC. In general, an adaptive computing descriptive object should include a description of the desired function (such as addition or multiplication), with description of its inputs and outputs, such as 16 or 32 bit I/O; in the exemplary embodiment, an ADO further includes a description of memory resources for operand and result data (such as a register file) and its I/O, and desired connections between the desired function and corresponding memory resources. In the exemplary embodiment, step 310 is implemented through a descriptive object “creator” process, which may convert higher-level descriptions into adaptive computing descriptive objects.
The adaptive computing descriptive objects may then be selected and combined into various groups or sets to perform various functions or algorithms; in the exemplary embodiment, this selecting and combining is performed during the scheduling process of step 335, as discussed in greater detail below. This scheduling process is also discussed in greater detail in the second related application. The various combinations of these adaptive computing descriptive objects which are selected, ultimately then form or comprise corresponding, multiple versions of adaptive computing circuitry, for use in steps 335 and 340. These adaptive computing circuit versions will vary depending upon the selected operating modes of the ACE 100 and the algorithms or functions the adaptive computing circuit is to perform. As discussed in greater detail below, these adaptive computing circuit versions may also differ according to their operational feature set, or optimization for various goals, such as comparatively low power consumption, comparatively low latency, bandwidth, comparatively high speed, and versatility for performance of a plurality of operating modes or algorithms. In the exemplary embodiment, an adaptive computing circuit version is generated through an iterative scheduling process (of step 335), which selects one or more ADOs for the performance of an algorithmic or functional element, maps the algorithmic elements to corresponding adaptive computing descriptive objects for execution, and provides corresponding timing information for execution of the algorithmic element on the selected hardware, as discussed in greater detail below.
As indicated above, the scheduling process of step 335 (also referred to and embodied as a “scheduler” of
One of the aims of the scheduling process of step 335 is to achieve a one-to-one correspondence between each algorithmic element and a computational element 250 needed to execute the algorithmic element. Furthermore, algorithmic elements may be scheduled with ADOs to reduce power consumption and/or latency, or to reduce bandwidth required for data movement across processes. The scheduler is also designed to recognize potentially competing resources, and to iteratively optimize the performance of the algorithm or program on a potential ACE circuit version, utilizing the plurality of ACE circuit versions which have been iteratively generated and which are thereby available, ultimately selecting one ACE circuit (or hardware) version as optimal or acceptable in light of the selected algorithms, available resources, competing operating modes, versatility, power consumption, latency, bandwidth, speed of operation, and the other considerations mentioned above, step 340. As a consequence, the scheduler of step 335 coordinates available adaptive computing (hardware) resources, over time, with the processes to be performed for the selected operating mode, generating the selected adaptive computing circuit version, with a corresponding scheduled algorithm or program for performance of the desired operating mode of the adaptive computing circuit.
In the exemplary embodiment, information is also output from the scheduling process and may be utilized to generate static reports, step 365, such as resource utilization reports (e.g., number and type of computational elements 250), and may be run through a simulation process (step 370), generating a dynamic report, such as describing power utilization, speed, bandwidth, and so on, step 375. These various reports may be used, for example, for evaluation purposes, and additional input may be provided back into the scheduler of step 335 to further optimize the adaptive computing circuit.
Once the scheduling process (or the various reports) indicate no comparatively greater opportunity or need for optimization of the selected circuit version (of step 340), the selected adaptive computing circuit version is converted into a hardware description, step 345, using a hardware description language as known in the field (such as Verilog), and ultimately fabricated to produce an ACE 100 or other adaptive computing integrated circuit corresponding to the selected circuit version, step 355.
The scheduling process of step 335 also provides an output indicating which computational elements 250 are in use in the adaptive computing circuit (such as the ACE 100), when, and how they are connected, i.e., an output of a scheduled algorithm or program for providing an operating mode to the selected adaptive computing circuit. This information is then compiled (converted or assembled) in step 350 into configuration information corresponding to the algorithmic element as scheduled for execution on selected computational elements 250. In the exemplary embodiment, the configuration information is an adaptive computing circuit (ACE) bit file, such as a stream or packet of bits which indicate, throughout the entire adaptive computing (ACE 100) circuit, the state (such as an initial state and any state changes) of various multiplexers, demultiplexers, or switches, which turn on or off different paths of interconnect (MIN), for connecting and reconnecting various computational elements, for routing of operand data and results, and for routing of configuration information within the IC. The resulting configuration information may then be compiled and/or loaded into one or more fabricated adaptive computing circuits, step 360, and the process may end, return step 380.
There are particularly novel features of the method illustrated in
Second, the method enables the creation of multiple versions of configuration information, for a selected operating mode, corresponding to either different hardware versions (used in step 340 to select an optimal version), or a different (operational) feature set of an ACE 100 circuit. For example, suppose three separate adaptive computing circuit versions are fabricated, hardware version 1, hardware version 2, and hardware version 3, each with different computational capabilities. The various adaptive computing circuit versions may have been optimized for different goals such as, for example, minimizing power consumption, maximizing speed of operation, minimizing cost, minimizing latency, maximizing versatility for having multiple operating modes, and so on. Each version, however, at a minimum will have a CDMA mobile communications operating mode, for this example. As a consequence, the scheduling and compiling of configuration information (of, respectively, steps 335 and 350) may generate corresponding sets of configuration information, enabling each hardware version to have the corresponding operating mode, with potentially differing operational feature sets (or more simply, feature sets), for the hardware version's given capabilities. Different feature sets (for an operating mode such as CDMA mobile communications) may include, for example, different memory and dialing list capability, different automatic dialing options, different alerting (ringing) options, different data transmission capabilities, and any other similar capabilities, such as feature sets for other potential operating modes such as paging, message display, electronic mail (email), or internet access capability. (It should be noted that depending upon the degree of convergence of multiple technologies, distinctions between an operating mode and a feature set may easily be blurred; for example, a CDMA mobile station may also include a paging function as part of its feature set, which would otherwise be an operating mode in a stand-alone pager.)
Continuing with the example, each of these hardware versions may then acquire additional operating modes, and have different capabilities or versatility for having additional operating modes. For example, hardware version 1 may also be capable of and select a GSM mobile communications operating mode and MP3 music playing capacity, while hardware versions 2 and 3 may be capable of only an additional MP3 music playing operating mode (given the now pre-existing CDMA operating mode). Multiple variations are clearly possible, especially given that new operating modes may be acquired, with or without retention of previous or pre-existing operating modes. Again, in light of the capabilities of each hardware version and its other operating modes (as competing for the same resources), the scheduling and compiling of configuration information steps 335 and 350 may generate corresponding sets or versions of configuration information, enabling each hardware version to have the corresponding operating mode, such as GSM or MP3, also with potentially differing feature sets, and also for the hardware version's given capabilities.
Third, and especially useful, an entire library or database of these versions of configuration information may be created in advance or in real time, based upon any one or more of a plurality of selection parameters, such as for each desired operating mode, for each hardware version, for each selected feature set, and in light of pre-existing or competing operating modes. In addition, additional versions may also be created for different operating conditions, such as power consumption, latency, and bandwidth considerations. A library of such versions (as “multiple binaries”) may be stored in multiple locations, such as on a network server, in a base station transceiver, or in another intelligent network device (such as an intelligent peripheral, a service circuit node, and so on), for download into a given ACE 100 by a corresponding service provider.
Fourth, all of the various processes may run off a single set of descriptions, the adaptive computing descriptive objects (or ADOs), for any number of different operating modes, with corresponding algorithms bound to the hardware through the scheduling process.
Fifth, the process is dynamic, with selected changes available when the configuration information is compiled or assembled into a corresponding bit file for loading into the ACE 100.
An exemplary system embodiment 400 in accordance with the present invention is illustrated in
Referring to
Continuing to refer to
Numerous advantages of the present invention are readily apparent. The invention provides control over the entire design and development process, from algorithm to loading a configuration bit file into an ACE 100. The invention enables the creation of multiple versions of configuration information for an adaptive computing circuit, for one or more selected operating modes, corresponding to different hardware versions, different feature sets, different operating conditions, and pre-existing operating modes. An entire library or database of these versions of configuration information may be created in advance or in real time, for each desired operating mode, for each hardware version, for each selected feature set, and in light of pre-existing or competing operating modes. In addition, additional versions may also be created for different operating conditions, such as power consumption, latency, and bandwidth considerations. A library of such versions (as “multiple binaries”) may be stored in multiple locations, such as on a network server, for download into a given adaptive computing circuit by a corresponding service provider. All of the various processes of the present invention may run off a single set of descriptions, the adaptive computing descriptive objects (or ADOs), for any number of different operating modes, with corresponding algorithms bound to the hardware through the scheduling process. Lastly, the process is dynamic, with selected changes available when the configuration information is compiled or assembled into a corresponding bit file for loading into the adaptive computing circuit.
From the foregoing, it will be observed that numerous variations and modifications may be effected without departing from the spirit and scope of the novel concept of the invention. It is to be understood that no limitation with respect to the specific methods and apparatus illustrated herein is intended or should be inferred. It is, of course, intended to cover by the appended claims all such modifications as fall within the scope of the claims.
| Number | Name | Date | Kind |
|---|---|---|---|
| 3409175 | Byrne | Nov 1968 | A |
| 3666143 | Weston | May 1972 | A |
| 3938639 | Birrell | Feb 1976 | A |
| 3949903 | Benasutti et al. | Apr 1976 | A |
| 3960298 | Birrell | Jun 1976 | A |
| 3967062 | Dobias | Jun 1976 | A |
| 3991911 | Shannon et al. | Nov 1976 | A |
| 3995441 | McMillin | Dec 1976 | A |
| 4076145 | Zygiel | Feb 1978 | A |
| 4143793 | McMillin et al. | Mar 1979 | A |
| 4172669 | Edelbach | Oct 1979 | A |
| 4174872 | Fessler | Nov 1979 | A |
| 4181242 | Zygiel | Jan 1980 | A |
| RE30301 | Zygiel | Jun 1980 | E |
| 4218014 | Tracy | Aug 1980 | A |
| 4222972 | Caldwell | Sep 1980 | A |
| 4237536 | Enelow et al. | Dec 1980 | A |
| 4252253 | Shannon | Feb 1981 | A |
| 4302775 | Widergren et al. | Nov 1981 | A |
| 4333587 | Fessler et al. | Jun 1982 | A |
| 4354613 | Desai et al. | Oct 1982 | A |
| 4377246 | McMillin et al. | Mar 1983 | A |
| 4393468 | New | Jul 1983 | A |
| 4413752 | McMillin et al. | Nov 1983 | A |
| 4458584 | Annese et al. | Jul 1984 | A |
| 4466342 | Basile et al. | Aug 1984 | A |
| 4475448 | Shoaf et al. | Oct 1984 | A |
| 4509690 | Austin et al. | Apr 1985 | A |
| 4520950 | Jeans | Jun 1985 | A |
| 4549675 | Austin | Oct 1985 | A |
| 4553573 | McGarrah | Nov 1985 | A |
| 4560089 | McMillin et al. | Dec 1985 | A |
| 4577782 | Fessler | Mar 1986 | A |
| 4578799 | Scholl et al. | Mar 1986 | A |
| RE32179 | Sedam et al. | Jun 1986 | E |
| 4633386 | Terepin | Dec 1986 | A |
| 4658988 | Hassell | Apr 1987 | A |
| 4694416 | Wheeler et al. | Sep 1987 | A |
| 4711374 | Gaunt et al. | Dec 1987 | A |
| 4713755 | Worley, Jr. et al. | Dec 1987 | A |
| 4719056 | Scott | Jan 1988 | A |
| 4726494 | Scott | Feb 1988 | A |
| 4747516 | Baker | May 1988 | A |
| 4748585 | Chiarulli et al. | May 1988 | A |
| 4760525 | Webb | Jul 1988 | A |
| 4760544 | Lamb | Jul 1988 | A |
| 4765513 | McMillin et al. | Aug 1988 | A |
| 4766548 | Cedrone et al. | Aug 1988 | A |
| 4781309 | Vogel | Nov 1988 | A |
| 4800492 | Johnson et al. | Jan 1989 | A |
| 4811214 | Nosenchuck et al. | Mar 1989 | A |
| 4824075 | Holzboog | Apr 1989 | A |
| 4827426 | Patton et al. | May 1989 | A |
| 4850269 | Hancock et al. | Jul 1989 | A |
| 4856684 | Gerstung | Aug 1989 | A |
| 4901887 | Burton | Feb 1990 | A |
| 4921315 | Metcalfe et al. | May 1990 | A |
| 4930666 | Rudick | Jun 1990 | A |
| 4932564 | Austin et al. | Jun 1990 | A |
| 4936488 | Austin | Jun 1990 | A |
| 4937019 | Scott | Jun 1990 | A |
| 4960261 | Scott et al. | Oct 1990 | A |
| 4961533 | Teller et al. | Oct 1990 | A |
| 4967340 | Dawes | Oct 1990 | A |
| 4974643 | Bennett et al. | Dec 1990 | A |
| 4982876 | Scott | Jan 1991 | A |
| 4993604 | Gaunt et al. | Feb 1991 | A |
| 5007560 | Sassak | Apr 1991 | A |
| 5021947 | Campbell et al. | Jun 1991 | A |
| 5040106 | Maag | Aug 1991 | A |
| 5044171 | Farkas | Sep 1991 | A |
| 5090015 | Dabbish et al. | Feb 1992 | A |
| 5129549 | Austin | Jul 1992 | A |
| 5139708 | Scott | Aug 1992 | A |
| 5156301 | Hassell et al. | Oct 1992 | A |
| 5156871 | Goulet et al. | Oct 1992 | A |
| 5165575 | Scott | Nov 1992 | A |
| 5190083 | Gupta et al. | Mar 1993 | A |
| 5190189 | Zimmer et al. | Mar 1993 | A |
| 5193151 | Jain | Mar 1993 | A |
| 5193718 | Hassell et al. | Mar 1993 | A |
| 5202993 | Tarsy et al. | Apr 1993 | A |
| 5203474 | Haynes | Apr 1993 | A |
| 5240144 | Feldman | Aug 1993 | A |
| 5261099 | Bigo et al. | Nov 1993 | A |
| 5263509 | Cherry et al. | Nov 1993 | A |
| 5269442 | Vogel | Dec 1993 | A |
| 5280711 | Motta et al. | Jan 1994 | A |
| 5297400 | Benton et al. | Mar 1994 | A |
| 5301100 | Wagner | Apr 1994 | A |
| 5303846 | Shannon | Apr 1994 | A |
| 5335276 | Thompson et al. | Aug 1994 | A |
| 5339428 | Burmeister et al. | Aug 1994 | A |
| 5343716 | Swanson et al. | Sep 1994 | A |
| 5361362 | Benkeser et al. | Nov 1994 | A |
| 5368198 | Goulet | Nov 1994 | A |
| 5379343 | Grube et al. | Jan 1995 | A |
| 5381546 | Servi et al. | Jan 1995 | A |
| 5381550 | Jourdenais et al. | Jan 1995 | A |
| 5388212 | Grube et al. | Feb 1995 | A |
| 5392960 | Kendt et al. | Feb 1995 | A |
| 5437395 | Bull et al. | Aug 1995 | A |
| 5450557 | Kopp et al. | Sep 1995 | A |
| 5454406 | Rejret et al. | Oct 1995 | A |
| 5465368 | Davidson et al. | Nov 1995 | A |
| 5479055 | Eccles | Dec 1995 | A |
| 5490165 | Blakeney, II et al. | Feb 1996 | A |
| 5491823 | Ruttenberg | Feb 1996 | A |
| 5507009 | Grube et al. | Apr 1996 | A |
| 5515519 | Yoshioka et al. | May 1996 | A |
| 5517600 | Shimokawa | May 1996 | A |
| 5519694 | Brewer et al. | May 1996 | A |
| 5522070 | Sumimoto | May 1996 | A |
| 5530964 | Alpert et al. | Jun 1996 | A |
| 5534796 | Edwards | Jul 1996 | A |
| 5542265 | Rutland | Aug 1996 | A |
| 5553755 | Bonewald et al. | Sep 1996 | A |
| 5555417 | Odnert et al. | Sep 1996 | A |
| 5560028 | Sachs et al. | Sep 1996 | A |
| 5560038 | Haddock | Sep 1996 | A |
| 5570587 | Kim | Nov 1996 | A |
| 5572572 | Kawan et al. | Nov 1996 | A |
| 5590353 | Sakakibara et al. | Dec 1996 | A |
| 5594657 | Cantone et al. | Jan 1997 | A |
| 5600810 | Ohkami | Feb 1997 | A |
| 5600844 | Shaw et al. | Feb 1997 | A |
| 5602833 | Zehavi | Feb 1997 | A |
| 5603043 | Taylor et al. | Feb 1997 | A |
| 5607083 | Vogel et al. | Mar 1997 | A |
| 5608643 | Wichter et al. | Mar 1997 | A |
| 5611867 | Cooper et al. | Mar 1997 | A |
| 5623545 | Childs et al. | Apr 1997 | A |
| 5625669 | McGregor et al. | Apr 1997 | A |
| 5626407 | Westcott | May 1997 | A |
| 5630206 | Urban et al. | May 1997 | A |
| 5635940 | Hickman et al. | Jun 1997 | A |
| 5646544 | Iadanza | Jul 1997 | A |
| 5646545 | Trimberger et al. | Jul 1997 | A |
| 5647512 | Assis Mascarenhas deOliveira et al. | Jul 1997 | A |
| 5667110 | McCann et al. | Sep 1997 | A |
| 5684793 | Kiema et al. | Nov 1997 | A |
| 5684980 | Casselman | Nov 1997 | A |
| 5687236 | Moskowitz et al. | Nov 1997 | A |
| 5694613 | Suzuki | Dec 1997 | A |
| 5694794 | Jerg et al. | Dec 1997 | A |
| 5699328 | Ishizaki et al. | Dec 1997 | A |
| 5701482 | Harrison et al. | Dec 1997 | A |
| 5704053 | Santhanam | Dec 1997 | A |
| 5706191 | Bassett et al. | Jan 1998 | A |
| 5706976 | Purkey | Jan 1998 | A |
| 5712996 | Schepers | Jan 1998 | A |
| 5720002 | Wang | Feb 1998 | A |
| 5721693 | Song | Feb 1998 | A |
| 5721854 | Ebicioglu et al. | Feb 1998 | A |
| 5732563 | Bethuy et al. | Mar 1998 | A |
| 5734808 | Takeda | Mar 1998 | A |
| 5737631 | Trimberger | Apr 1998 | A |
| 5742180 | DeHon et al. | Apr 1998 | A |
| 5742821 | Prasanna | Apr 1998 | A |
| 5745366 | Highma et al. | Apr 1998 | A |
| RE35780 | Hassell et al. | May 1998 | E |
| 5751295 | Becklund et al. | May 1998 | A |
| 5754227 | Fukuoka | May 1998 | A |
| 5758261 | Wiedeman | May 1998 | A |
| 5768561 | Wise | Jun 1998 | A |
| 5778439 | Trimberger et al. | Jul 1998 | A |
| 5784636 | Rupp | Jul 1998 | A |
| 5787237 | Reilly | Jul 1998 | A |
| 5790817 | Asghar et al. | Aug 1998 | A |
| 5791517 | Avital | Aug 1998 | A |
| 5791523 | Oh | Aug 1998 | A |
| 5794062 | Baxter | Aug 1998 | A |
| 5794067 | Kadowaki | Aug 1998 | A |
| 5802055 | Krein et al. | Sep 1998 | A |
| 5818603 | Motoyama | Oct 1998 | A |
| 5822308 | Weigand et al. | Oct 1998 | A |
| 5822313 | Malek et al. | Oct 1998 | A |
| 5822360 | Lee et al. | Oct 1998 | A |
| 5828858 | Athanas et al. | Oct 1998 | A |
| 5829085 | Jerg et al. | Nov 1998 | A |
| 5835753 | Witt | Nov 1998 | A |
| 5838165 | Chatter | Nov 1998 | A |
| 5845815 | Vogel | Dec 1998 | A |
| 5860021 | Klingman | Jan 1999 | A |
| 5862961 | Motta et al. | Jan 1999 | A |
| 5870427 | Tiedemann, Jr. et al. | Feb 1999 | A |
| 5873045 | Lee et al. | Feb 1999 | A |
| 5881106 | Cartier | Mar 1999 | A |
| 5884284 | Peters et al. | Mar 1999 | A |
| 5886537 | Macias et al. | Mar 1999 | A |
| 5887174 | Simons et al. | Mar 1999 | A |
| 5889816 | Agrawal et al. | Mar 1999 | A |
| 5890014 | Long | Mar 1999 | A |
| 5892900 | Ginter et al. | Apr 1999 | A |
| 5892961 | Trimberger | Apr 1999 | A |
| 5894473 | Dent | Apr 1999 | A |
| 5901884 | Goulet et al. | May 1999 | A |
| 5903886 | Heimlich et al. | May 1999 | A |
| 5907285 | Toms et al. | May 1999 | A |
| 5907580 | Cummings | May 1999 | A |
| 5910733 | Bertolet et al. | Jun 1999 | A |
| 5912572 | Graf, III | Jun 1999 | A |
| 5913172 | McCabe et al. | Jun 1999 | A |
| 5917852 | Butterfield et al. | Jun 1999 | A |
| 5920801 | Thomas et al. | Jul 1999 | A |
| 5931918 | Row et al. | Aug 1999 | A |
| 5933642 | Greenbaum et al. | Aug 1999 | A |
| 5940438 | Poon et al. | Aug 1999 | A |
| 5949415 | Lin et al. | Sep 1999 | A |
| 5950011 | Albrecht et al. | Sep 1999 | A |
| 5950131 | Vilmur | Sep 1999 | A |
| 5951674 | Moreno | Sep 1999 | A |
| 5953322 | Kimball | Sep 1999 | A |
| 5956518 | DeHon et al. | Sep 1999 | A |
| 5956967 | Kim | Sep 1999 | A |
| 5959811 | Richardson | Sep 1999 | A |
| 5959881 | Trimberger et al. | Sep 1999 | A |
| 5963048 | Harrison et al. | Oct 1999 | A |
| 5966534 | Cooke et al. | Oct 1999 | A |
| 5970254 | Cooke et al. | Oct 1999 | A |
| 5987105 | Jenkins et al. | Nov 1999 | A |
| 5987611 | Freund | Nov 1999 | A |
| 5991302 | Berl et al. | Nov 1999 | A |
| 5991308 | Fuhrmann et al. | Nov 1999 | A |
| 5993739 | Lyon | Nov 1999 | A |
| 5999734 | Willis et al. | Dec 1999 | A |
| 6005943 | Cohen et al. | Dec 1999 | A |
| 6006249 | Leong | Dec 1999 | A |
| 6016395 | Mohamed | Jan 2000 | A |
| 6021186 | Suzuki et al. | Feb 2000 | A |
| 6021492 | May | Feb 2000 | A |
| 6023742 | Ebeling et al. | Feb 2000 | A |
| 6023755 | Casselman | Feb 2000 | A |
| 6028610 | Deering | Feb 2000 | A |
| 6036166 | Olson | Mar 2000 | A |
| 6039219 | Bach et al. | Mar 2000 | A |
| 6041322 | Meng et al. | Mar 2000 | A |
| 6041970 | Vogel | Mar 2000 | A |
| 6046603 | New | Apr 2000 | A |
| 6047115 | Mohan et al. | Apr 2000 | A |
| 6052600 | Fette et al. | Apr 2000 | A |
| 6055314 | Spies et al. | Apr 2000 | A |
| 6056194 | Kolls | May 2000 | A |
| 6059840 | Click, Jr. | May 2000 | A |
| 6061580 | Altschul et al. | May 2000 | A |
| 6073132 | Gehman | Jun 2000 | A |
| 6076174 | Freund | Jun 2000 | A |
| 6078736 | Guccione | Jun 2000 | A |
| 6085740 | Ivri et al. | Jul 2000 | A |
| 6088043 | Kelleher et al. | Jul 2000 | A |
| 6091263 | New et al. | Jul 2000 | A |
| 6091765 | Pietzold, III et al. | Jul 2000 | A |
| 6094065 | Tavana et al. | Jul 2000 | A |
| 6094726 | Gonion et al. | Jul 2000 | A |
| 6111893 | Volftsun et al. | Aug 2000 | A |
| 6111935 | Hughes-Hartogs | Aug 2000 | A |
| 6115751 | Tam et al. | Sep 2000 | A |
| 6120551 | Law et al. | Sep 2000 | A |
| 6122670 | Bennett et al. | Sep 2000 | A |
| 6138693 | Matz | Oct 2000 | A |
| 6141283 | Bogin et al. | Oct 2000 | A |
| 6150838 | Wittig et al. | Nov 2000 | A |
| 6154494 | Sugahara et al. | Nov 2000 | A |
| 6157997 | Oowaki et al. | Dec 2000 | A |
| 6175854 | Bretscher | Jan 2001 | B1 |
| 6175892 | Sazzad et al. | Jan 2001 | B1 |
| 6181981 | Varga et al. | Jan 2001 | B1 |
| 6185418 | MacLellan et al. | Feb 2001 | B1 |
| 6192070 | Poon et al. | Feb 2001 | B1 |
| 6192255 | Lewis et al. | Feb 2001 | B1 |
| 6192388 | Cajolet | Feb 2001 | B1 |
| 6195788 | Leaver et al. | Feb 2001 | B1 |
| 6198924 | Ishii et al. | Mar 2001 | B1 |
| 6199181 | Rechef et al. | Mar 2001 | B1 |
| 6202130 | Scales, III et al. | Mar 2001 | B1 |
| 6219697 | Lawande et al. | Apr 2001 | B1 |
| 6219756 | Kasamizugami | Apr 2001 | B1 |
| 6219780 | Lipasti | Apr 2001 | B1 |
| 6223222 | Fijolek et al. | Apr 2001 | B1 |
| 6226387 | Tewfik et al. | May 2001 | B1 |
| 6230307 | Davis et al. | May 2001 | B1 |
| 6237029 | Master et al. | May 2001 | B1 |
| 6246883 | Lee | Jun 2001 | B1 |
| 6247125 | Noel-Baron et al. | Jun 2001 | B1 |
| 6249251 | Chang et al. | Jun 2001 | B1 |
| 6258725 | Lee et al. | Jul 2001 | B1 |
| 6263057 | Silverman | Jul 2001 | B1 |
| 6266760 | DeHon et al. | Jul 2001 | B1 |
| 6272579 | Lentz et al. | Aug 2001 | B1 |
| 6281703 | Furuta et al. | Aug 2001 | B1 |
| 6282627 | Wong et al. | Aug 2001 | B1 |
| 6289375 | Knight et al. | Sep 2001 | B1 |
| 6289434 | Roy | Sep 2001 | B1 |
| 6289488 | Dave et al. | Sep 2001 | B1 |
| 6292822 | Hardwick | Sep 2001 | B1 |
| 6292827 | Raz | Sep 2001 | B1 |
| 6292830 | Taylor et al. | Sep 2001 | B1 |
| 6301653 | Mohamed et al. | Oct 2001 | B1 |
| 6305014 | Roediger et al. | Oct 2001 | B1 |
| 6311149 | Ryan et al. | Oct 2001 | B1 |
| 6321985 | Kolls | Nov 2001 | B1 |
| 6346824 | New | Feb 2002 | B1 |
| 6347346 | Taylor | Feb 2002 | B1 |
| 6349394 | Brock et al. | Feb 2002 | B1 |
| 6353841 | Marshall et al. | Mar 2002 | B1 |
| 6356994 | Barry et al. | Mar 2002 | B1 |
| 6359248 | Mardi | Mar 2002 | B1 |
| 6360256 | Lim | Mar 2002 | B1 |
| 6360259 | Bradley | Mar 2002 | B1 |
| 6360263 | Kurtzberg et al. | Mar 2002 | B1 |
| 6363411 | Dugan et al. | Mar 2002 | B1 |
| 6366999 | Drabenstott et al. | Apr 2002 | B1 |
| 6377983 | Cohen et al. | Apr 2002 | B1 |
| 6378072 | Collins et al. | Apr 2002 | B1 |
| 6381735 | Hunt | Apr 2002 | B1 |
| 6385751 | Wolf | May 2002 | B1 |
| 6405214 | Meade, II | Jun 2002 | B1 |
| 6408039 | Ito | Jun 2002 | B1 |
| 6410941 | Taylor et al. | Jun 2002 | B1 |
| 6411612 | Halford et al. | Jun 2002 | B1 |
| 6421372 | Bierly et al. | Jul 2002 | B1 |
| 6421809 | Wuytack et al. | Jul 2002 | B1 |
| 6430624 | Jamtgaard et al. | Aug 2002 | B1 |
| 6433578 | Wasson | Aug 2002 | B1 |
| 6434590 | Blelloch et al. | Aug 2002 | B1 |
| 6438737 | Morelli et al. | Aug 2002 | B1 |
| 6456996 | Crawford, Jr. et al. | Sep 2002 | B1 |
| 6459883 | Subramanian et al. | Oct 2002 | B2 |
| 6473609 | Schwartz et al. | Oct 2002 | B1 |
| 6507947 | Schreiber et al. | Jan 2003 | B1 |
| 6510138 | Pannell | Jan 2003 | B1 |
| 6510510 | Garde | Jan 2003 | B1 |
| 6538470 | Langhammer et al. | Mar 2003 | B1 |
| 6556044 | Langhammer et al. | Apr 2003 | B2 |
| 6563891 | Eriksson et al. | May 2003 | B1 |
| 6570877 | Kloth et al. | May 2003 | B1 |
| 6577678 | Scheuermann | Jun 2003 | B2 |
| 6587684 | Hsu et al. | Jul 2003 | B1 |
| 6590415 | Agrawal et al. | Jul 2003 | B2 |
| 6601086 | Howard et al. | Jul 2003 | B1 |
| 6601158 | Abbott et al. | Jul 2003 | B1 |
| 6604085 | Kolls | Aug 2003 | B1 |
| 6606529 | Crowder et al. | Aug 2003 | B1 |
| 6615333 | Hoogerbrugge et al. | Sep 2003 | B1 |
| 6618434 | Heidari-Bateni et al. | Sep 2003 | B2 |
| 6640304 | Ginter et al. | Oct 2003 | B2 |
| 6653859 | Sihlbom et al. | Nov 2003 | B2 |
| 6675265 | Barroso et al. | Jan 2004 | B2 |
| 6691148 | Zinky et al. | Feb 2004 | B1 |
| 6711617 | Bantz et al. | Mar 2004 | B1 |
| 6718182 | Kung | Apr 2004 | B1 |
| 6721286 | Williams et al. | Apr 2004 | B1 |
| 6721884 | De Oliveira Kastrup Pereira et al. | Apr 2004 | B1 |
| 6732354 | Ebeling et al. | May 2004 | B2 |
| 6735621 | Yoakum et al. | May 2004 | B1 |
| 6738744 | Kirovski et al. | May 2004 | B2 |
| 6748360 | Pitman et al. | Jun 2004 | B2 |
| 6754470 | Hendrickson et al. | Jun 2004 | B2 |
| 6760587 | Holtzman et al. | Jul 2004 | B2 |
| 6766165 | Sharma et al. | Jul 2004 | B2 |
| 6778212 | Deng et al. | Aug 2004 | B1 |
| 6785341 | Walton et al. | Aug 2004 | B2 |
| 6819140 | Yamanaka et al. | Nov 2004 | B2 |
| 6823448 | Roth et al. | Nov 2004 | B2 |
| 6829633 | Gelfer et al. | Dec 2004 | B2 |
| 6832250 | Coons et al. | Dec 2004 | B1 |
| 6836839 | Master et al. | Dec 2004 | B2 |
| 6865664 | Budrovic et al. | Mar 2005 | B2 |
| 6871236 | Fishman et al. | Mar 2005 | B2 |
| 6883084 | Donohoe | Apr 2005 | B1 |
| 6894996 | Lee | May 2005 | B2 |
| 6901440 | Bimm et al. | May 2005 | B1 |
| 6912515 | Jackson et al. | Jun 2005 | B2 |
| 6985517 | Matsumoto et al. | Jan 2006 | B2 |
| 6986021 | Master et al. | Jan 2006 | B2 |
| 6988139 | Jervis et al. | Jan 2006 | B1 |
| 7032229 | Flores et al. | Apr 2006 | B1 |
| 7044741 | Leem | May 2006 | B2 |
| 7082456 | Mani-Meitav et al. | Jul 2006 | B2 |
| 7139910 | Ainsworth et al. | Nov 2006 | B1 |
| 7142731 | Toi | Nov 2006 | B1 |
| 7249242 | Ramchandran | Jul 2007 | B2 |
| 20010003191 | Kovacs et al. | Jun 2001 | A1 |
| 20010023482 | Wray | Sep 2001 | A1 |
| 20010029515 | Mirsky | Oct 2001 | A1 |
| 20010034795 | Moulton et al. | Oct 2001 | A1 |
| 20010039654 | Miyamoto | Nov 2001 | A1 |
| 20010048713 | Medlock et al. | Dec 2001 | A1 |
| 20010048714 | Jha | Dec 2001 | A1 |
| 20010050948 | Ramberg et al. | Dec 2001 | A1 |
| 20020010848 | Kamano et al. | Jan 2002 | A1 |
| 20020013799 | Blaker | Jan 2002 | A1 |
| 20020013937 | Ostanevich et al. | Jan 2002 | A1 |
| 20020015435 | Rieken | Feb 2002 | A1 |
| 20020015439 | Kohli et al. | Feb 2002 | A1 |
| 20020023210 | Tuomenoksa et al. | Feb 2002 | A1 |
| 20020024942 | Tsuneki et al. | Feb 2002 | A1 |
| 20020024993 | Subramanian et al. | Feb 2002 | A1 |
| 20020031166 | Subramanian et al. | Mar 2002 | A1 |
| 20020032551 | Zakiya | Mar 2002 | A1 |
| 20020035623 | Lawande et al. | Mar 2002 | A1 |
| 20020041581 | Aramaki | Apr 2002 | A1 |
| 20020042907 | Yamanaka et al. | Apr 2002 | A1 |
| 20020061741 | Leung et al. | May 2002 | A1 |
| 20020069282 | Reisman | Jun 2002 | A1 |
| 20020072830 | Hunt | Jun 2002 | A1 |
| 20020078337 | Moreau et al. | Jun 2002 | A1 |
| 20020083305 | Renard et al. | Jun 2002 | A1 |
| 20020083423 | Ostanevich et al. | Jun 2002 | A1 |
| 20020087829 | Snyder et al. | Jul 2002 | A1 |
| 20020089348 | Langhammer | Jul 2002 | A1 |
| 20020101909 | Chen et al. | Aug 2002 | A1 |
| 20020107905 | Roe et al. | Aug 2002 | A1 |
| 20020107962 | Richter et al. | Aug 2002 | A1 |
| 20020119803 | Bitterlich et al. | Aug 2002 | A1 |
| 20020120672 | Butt et al. | Aug 2002 | A1 |
| 20020138716 | Master et al. | Sep 2002 | A1 |
| 20020141489 | Imaizumi | Oct 2002 | A1 |
| 20020147845 | Sanchez-Herrero et al. | Oct 2002 | A1 |
| 20020159503 | Ramachandran | Oct 2002 | A1 |
| 20020162026 | Neuman et al. | Oct 2002 | A1 |
| 20020168018 | Scheuermann | Nov 2002 | A1 |
| 20020181559 | Heidari-Bateni et al. | Dec 2002 | A1 |
| 20020184291 | Hogenauer | Dec 2002 | A1 |
| 20020184498 | Qi | Dec 2002 | A1 |
| 20020191790 | Anand et al. | Dec 2002 | A1 |
| 20030007606 | Suder et al. | Jan 2003 | A1 |
| 20030012270 | Zhou et al. | Jan 2003 | A1 |
| 20030018446 | Makowski et al. | Jan 2003 | A1 |
| 20030018700 | Giroti et al. | Jan 2003 | A1 |
| 20030023830 | Hogenauer | Jan 2003 | A1 |
| 20030026242 | Jokinen et al. | Feb 2003 | A1 |
| 20030030004 | Dixon et al. | Feb 2003 | A1 |
| 20030046421 | Horvitz et al. | Mar 2003 | A1 |
| 20030061260 | Rajkumar | Mar 2003 | A1 |
| 20030061311 | Lo | Mar 2003 | A1 |
| 20030063656 | Rao et al. | Apr 2003 | A1 |
| 20030076815 | Miller et al. | Apr 2003 | A1 |
| 20030088223 | Chang et al. | May 2003 | A1 |
| 20030102889 | Master et al. | Jun 2003 | A1 |
| 20030105949 | Master et al. | Jun 2003 | A1 |
| 20030110485 | Lu et al. | Jun 2003 | A1 |
| 20030142818 | Raghunathan et al. | Jul 2003 | A1 |
| 20030154357 | Master et al. | Aug 2003 | A1 |
| 20030163723 | Kozuch et al. | Aug 2003 | A1 |
| 20030172138 | McCormack et al. | Sep 2003 | A1 |
| 20030172139 | Srinivasan et al. | Sep 2003 | A1 |
| 20030200538 | Ebeling et al. | Oct 2003 | A1 |
| 20030212684 | Meyer et al. | Nov 2003 | A1 |
| 20040006584 | Vandeweerd | Jan 2004 | A1 |
| 20040010645 | Scheuermann et al. | Jan 2004 | A1 |
| 20040015970 | Scheuermann | Jan 2004 | A1 |
| 20040025159 | Scheuermann et al. | Feb 2004 | A1 |
| 20040057505 | Valio | Mar 2004 | A1 |
| 20040062300 | McDonough et al. | Apr 2004 | A1 |
| 20040081248 | Parolari | Apr 2004 | A1 |
| 20040093479 | Ramchandran | May 2004 | A1 |
| 20040168044 | Ramchandran | Aug 2004 | A1 |
| 20050166038 | Wang et al. | Jul 2005 | A1 |
| 20050198199 | Dowling | Sep 2005 | A1 |
| 20060031660 | Master et al. | Feb 2006 | A1 |
| Number | Date | Country |
|---|---|---|
| 100 18 374 | Oct 2001 | DE |
| 0 301 169 | Feb 1989 | EP |
| 0 166 586 | Jan 1991 | EP |
| 0 236 633 | May 1991 | EP |
| 0 478 624 | Apr 1992 | EP |
| 0 479 102 | Apr 1992 | EP |
| 0 661 831 | Jul 1995 | EP |
| 0 668 659 | Aug 1995 | EP |
| 0 690 588 | Jan 1996 | EP |
| 0 691 754 | Jan 1996 | EP |
| 0 768 602 | Apr 1997 | EP |
| 0 817 003 | Jan 1998 | EP |
| 0 821 495 | Jan 1998 | EP |
| 0 866 210 | Sep 1998 | EP |
| 0 923 247 | Jun 1999 | EP |
| 0 926 596 | Jun 1999 | EP |
| 1 056 217 | Nov 2000 | EP |
| 1 061 437 | Dec 2000 | EP |
| 1 061 443 | Dec 2000 | EP |
| 1 126 368 | Aug 2001 | EP |
| 1 150 506 | Oct 2001 | EP |
| 1 189 358 | Mar 2002 | EP |
| 2 067 800 | Jul 1981 | GB |
| 2 237 908 | May 1991 | GB |
| 62-249456 | Oct 1987 | JP |
| 63-147258 | Jun 1988 | JP |
| 4-51546 | Feb 1992 | JP |
| 7-064789 | Mar 1995 | JP |
| 7066718 | Mar 1995 | JP |
| 10233676 | Sep 1998 | JP |
| 10254696 | Sep 1998 | JP |
| 11296345 | Oct 1999 | JP |
| 2000315731 | Nov 2000 | JP |
| 2001-053703 | Feb 2001 | JP |
| WO 8905029 | Jun 1989 | WO |
| WO 8911443 | Nov 1989 | WO |
| WO 9100238 | Jan 1991 | WO |
| WO 9313603 | Jul 1993 | WO |
| WO 9511855 | May 1995 | WO |
| WO 9633558 | Oct 1996 | WO |
| WO 9832071 | Jul 1998 | WO |
| WO 9903776 | Jan 1999 | WO |
| WO 9921094 | Apr 1999 | WO |
| WO 9926860 | Jun 1999 | WO |
| WO 9965818 | Dec 1999 | WO |
| WO 0019311 | Apr 2000 | WO |
| WO 0065855 | Nov 2000 | WO |
| WO 0069073 | Nov 2000 | WO |
| WO 0111281 | Feb 2001 | WO |
| WO 0122235 | Mar 2001 | WO |
| WO 0176129 | Oct 2001 | WO |
| WO 0212978 | Feb 2002 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 20040093601 A1 | May 2004 | US |
