METHOD, SYSTEM AND RELATED SYNCHRONIZER FOR CONTROLLING DATA SYNCHRONIZATION IN FIFO MEMORIES

Abstract

A system for detecting during write/read operations the status of a FIFO memory having N memory locations includes a first and a second Gray-code counter each configured to take values out of 2*N possible values. The first and second Gray-code counters are configured to be initialized to a value J, and incremented on each write operation and each said read operation. The first and second Gray-code counters are configured to be set to the value 0 if their count values reach 2*N. A comparator block monitors the distance of the value of the first counter to the value of said second counter and detects the full status of the FIFO memory if that distance is equal to N. The comparator block may similarly detect the empty status of the FIFO memory if the distance in question is equal to 0.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described, by way of example only, by referring to the enclosed representations, wherein:

FIG. 1, already discussed in the foregoing, is a chart showing the different bit consumptions of Gray-coding and TWO-HOT encoding,

FIG. 2 shows a table of the Full-Gray-Code,

FIG. 3 shows a table containing the Gray-Coded symbols associated to certain FIFO memory dimension,

FIG. 4 is a block diagram illustrating an embodiment of a hard FIFO memory using a shifted write Gray-code counter,

FIG. 5 is a block diagram illustrating an alternative embodiment of a hard FIFO memory using a shifted read Gray-code counter,

FIG. 6 is a block diagram illustrating an embodiment of a soft FIFO memory using a shifted write Gray-code counter,

FIG. 7 is a block diagram illustrating an alternative embodiment of a soft FIFO memory using a shifted read Gray-code counter, and

FIG. 8 is a block diagram illustrating an embodiment of a soft FIFO memory using a 1-hot encoder and a shifter.

In order to improve comprehensibility of the figures, the same numbers will be maintained for the same functional blocks in subsequent figures.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The arrangement described herein is based on the usage of a Gray-code, which includes 2*N symbols for a FIFO memory having either an odd or an even number of FIFO memory lines N. Preferably, this Gray-code is obtained by a standard full Gray-code of log₂(2*N) bits as can be seen in FIG. 2.

In a preferred embodiment, the full Gray-coded symbols are obtained from the immediately preceding Gray-coded symbols (i.e. having N−1 bits) mirroring all values at a “Mirror line” (100) and then adding a column of zeros on the left for the original set of symbols and a column of ones for the mirrored symbols.

In FIG. 2, a table is shown containing the Gray-coded symbols GCS for 1, 2, 3 and 4 bits, including also the respective “Mirror Lines” 100.

For a certain number of FIFO memory lines not necessarily all available Gray-coded symbols will be required. For instance, for the encoding of N=3 FIFO memory lines only 6 (2*N) Gray-Coded symbols are necessary, while 8 (2³) Gray-coded symbols are available. In order to guarantee that only a single bit value changes in the case of “wrapping” from the last to the first Gray-coded symbol the central 2*N Gray coded symbols are selected. In that respect, FIG. 3 shows exemplary associations of Gray-coded symbols (GCS) to certain numbers of FIFO memory lines N.

Those of skill in the art will appreciate that other methods for obtaining such Gray-code symbols can be used to provide 2N symbols with correct “wrapping” from the last to first element while respecting the rule of having only one single bit change.

In that respect, throughout this description (and, more to the point, in the claims that follow) reference will be repeatedly made to counts/counters being reset to the value 0 when the count/counter “reaches the value 2*N”. Those of skill in the art will promptly appreciate that the count/counter “reaching” the value 2*N will typically involve the count/counter switching directly from ((2*N)−1)) to 0, without the count/counter properly taking on the value 2*N.

A Gray-code counter, which provides the desired wrapping on these 2N symbols and that can be reset to an initial specific symbol is implemented and used in several instances of the FIFO memory control. It will be appreciated that Gray-code counters per se are well known in the art, which makes it unnecessary to provide a more detailed description herein, since any implementation of Gray-code counters will be generally satisfactory for the purposes of the arrangement described herein.

As indicated, the arrangement described herein has the primary aim of detecting the “FULL” and “EMPTY” conditions of FIFO memories by using a set of such Gray-code counters.

Instead of using N values to encode the current FIFO memory status, a total of 2*N values are used. In this way, the symbol at position J and the symbol at position (J+N) will represent the same memory location, but will be different symbols. This is important for detecting the FULL condition as will be explained in the following.

Generally, two Gray-code counters are used to initially hold the same value of one of the 2*N Gray-coded symbols. The first read Gray-code counter increments on each read operation, the second write Gray-code counter increments on each write operation.

The “EMPTY” condition can be obtained when the distance between the read counter and the write counter is equal to zero, in other words when the two counters hold the same value.

The “FULL” condition is obtained when the distance between the write counter and the read counter is equal to N (i.e. the FIFO memory contains N elements). In a preferred embodiment, in order to calculate the distance between the two wrapping Gray-code counters a comparison is performed between the value of one of the two counters respect to the value of the other counter increased by N. In this way, the fact that the two values are equal implies that the distance between the write and read counters was actually N and therefore the FIFO memory has to be considered as “FULL”.

In one embodiment the value is encoded with a third Gray-code counter initialized to symbols at position (J+N) and incremented either on a read or a write operation.

In another embodiment the value can be derived from 1-hot encoding the Gray-coded symbols and then using a shift of N bit to derive from the 1-hot encoded value of the symbol at position J the 1-hot encoded value of the symbol at position (J+N). Those of skill in the art will appreciate that other methods, not described explicitly herein, will permit to derive the value of the symbol at distance N providing the same effect.

FIG. 4 shows a block diagram of an embodiment of a hard FIFO memory. As better detailed in the following, this embodiment includes a third shifted Gray-coded counter, which is incremented on each write operation.

In the embodiment of FIG. 4 two clock domains are present. The write clock domain 20 is shown on the left hand side, and the read clock domain 40 is shown on the right hand side.

A dual port FIFO memory 10 is used to synchronize a data flow. To that end, incoming data on a data-in bus DI will be recorded in a FIFO memory location pointed by a write-address counter 204 when a write-enable signal WE is active on a write clock W_CLK rising edge. Out-coming data on a data-out bus DO will reflect the value of the FIFO memory location pointed by the read-address counter 404.

Three counters are present in the write clock domain 20.

The write-address counter 204 is a simple binary counter, which counts from 0 to N−1 and then wraps again to zero each time the write-enable signal WE is active on a write clock W_CLK rising edge.

The second counter is a write Gray-code counter 202 and the last counter is a shifted write Gray-code counter 208. The write Gray-code counter 202 is initialized to the first Gray-coded symbol selected as Gray-code starting point (i.e. J), while the shifted write Gray-code counter 208 is initialized to the symbol at distance N (i.e. symbol at position J+N).

Both counters 202 and 208 are incremented each time a new value is written, i.e. each time the write-enable signal WE is active on a write clock W_CLK rising edge.

In the read clock domain 40 two counters are present. The read address counter 404 is a simple binary counter, which counts from 0 to N−1 and then wraps again to zero each time the read-enable signal RE is active on a read-clock R_CLK rising edge.

The second counter is a read Gray-code counter 402 initialized to the first Gray-coded symbol selected as Gray-code starting point (i.e. symbol J). The counter will be incremented each time a new value is read, i.e. each time the read-enable signal RE is active on a read clock R_CLK rising edge.

In order to generate the “EMPTY” flag the write Gray-code counter 202 is synchronized through a synchronization logic 406 that can be implemented in manner known per se e.g. by using a cascade of two or more flip-flops depending on the read clock R_CLK frequency and on the physical characteristic of the devices.

The synchronized value is then compared at 410 against the value of the read Gray-code counter 402. If the two values are equal then the “EMPTY” flag FE is asserted.

In order to generate the “FULL” flag FF the read Gray-code counter 402 is synchronized by using a synchronization logic 206. Typically, this is implemented using e.g. a cascade of two or more flip-flops depending on the write clock W_CLK frequency and on the physical characteristic of the devices used.

The synchronized value is then compared at 210 against the value of the shifted write Gray-code counter.

An alternative circuit for generating the FIFO “FULL” flag FF is shown in FIG. 5. In this embodiment the shifted Gray-code counter 408 is placed in the read clock domain 40 and is incremented each time data is read from the FIFO, i.e. when the read enable signal RE is active on a read clock R_CLK rising edge.

In this case, the value of the shifted read Gray-code counter 408 is synchronized at 206 as explained in the foregoing and compared at 210 with the value of the write Gray-code counter 202. The “FULL” flag FE is asserted if the two values match.

FIG. 5 shows an implementation of the shifter write Gray-code counter 208 of FIG. 4 wherein the shifted read Gray-code counter 408 is in the read clock domain 40.

It will be recalled that throughout the figures annexed and relating to different embodiments, the same references are used to indicate elements that are identical or equivalent: as a consequence, the description of these elements is not repeated for each embodiment.

FIGS. 6 and 7 show alternative embodiments that are preferred for soft FIFO memories. In these implementations the hardware has been optimized by dispensing with the two binary counters 204, 404 used in the previous embodiments to address the FIFO memory location.

In FIGS. 6 and 7, the read and write addresses are generated directly by decoding the read and write Gray-code counters 202, 402 by taking into account that symbols at position J and J+N will point to the same FIFO address location.

This solution is preferred for small FIFO memories as it may increase the number of symbols to be decoded and thus become more complex than an embodiment with two independent read and write address counters 204, 404.

Specifically, in FIGS. 6 and 7, a set of registers 30 driven by the write clock W_CLK plays the role of the FIFO memory 10.

In these embodiments, the write and read address pointers are Gray-coded, and they are preferably converted into binary signals. This can be achieved e.g. by using two Gray-code decoders.

A first Gray-code decoder 218 is used to decode the value of the write Gray-code counter 202 into the write address of the soft FIFO memory. Accordingly the second Gray-code decoder 418 is used to decode the value of the read Gray-code counter 402 into the read address of the soft FIFO memory.

In order to decode the write address into the memory location of a write operation, an address decoder 32 is used. This address decoder preferably lies in the write clock domain 20 and can be realized e.g. by a simple demultiplexer.

In order to decode the read-address into the memory location of a read operation, a second address decoder 34 is used. This address decoder preferably lies in the read clock domain 40 and can be realized e.g. by a simple multiplexer.

Those of skill in the art will appreciate that this Gray-code decoder 218, 418 and the address decoder 32, 34 may take the form of a single decoder, which decodes the respective Gray-coded values directly into the related memory locations.

In the embodiment of FIG. 6, the “FULL” status of the FIFO memory is generated by comparing at 210 the value of the shifted write Gray-code counter 208 with the value of a synchronizer 206 that reads the contents of the Gray-code counter 402.

FIG. 7 shows an alternative embodiment where the “FULL” status of the FIFO memory is generated by comparing at 210 the value of the write Gray-code counter 202 with the value of the synchronizer 206, i.e. the shifted read Gray-code counter 408.

A further possible embodiment is shown in FIG. 8. In this case, the third Gray-code counter 208, 408 used to detect the “FULL” status of the FIFO memory has been removed and the symbol at distance N is obtained by using a 1-hot encoder 212 and a shifter 214.

The 2*N Gray-coded symbols are encoded with the 1-hot encoding technique.

The first Gray-coded symbol of the given set of 2*N symbols will be mapped to the 2*N bit vector having the bit at position 0 set to ‘1’.

The subsequent Gray-coded symbols will be mapped to the vectors obtained by shifting to the left by one bit the previous 1-hot encoded vector.

Accordingly, the 1-hot encoded value of a Gray-coded symbol at distance N from a given Gray-coded symbol can be detected by shifting the 1-hot encoded value of the given Gray-coded symbol by N bit to the left.

With these premises, the “FULL” flag of the FIFO memory can be obtained by comparing at 210 the 1-hot encoded 212 value of the write Gray-code counter 202 shifted by N bit to the left 214 with the 1-hot encoded 216 value of the synchronizer 206 representative of the value of the read Gray-code counter 402.

Those of skill in the art will appreciate that this type of control can be applied also in the read-clock domain 40 following the same principles of the previous described alternative embodiments.

Of course, without prejudice to the underlying principles of the invention, the details and the embodiments may vary, even significantly, with respect to what has been described and illustrated, just by way of example, without departing from the scope of the invention as defined in the annexed claims.

Claims

1. A method of detecting the status of a FIFO memory during write/read operations, said FIFO memory having N memory locations, the method comprising: providing first and second Gray-code counts each configured to take values out of 2*N possible values;initializing said first and second Gray-code counts to a value J;incrementing said first Gray-code count on each said write operation, and setting said first count to the value 0 if the value of said first count reaches 2*N;incrementing said second Gray-code count on each said read operation, and setting said second count to the value 0 if the value of said second counter reaches 2*N;monitoring the distance of the value of said first count to the value of said second count; anddetecting the full status of said FIFO memory if said distance of the value of said first count to the value of said second count is equal to N.

2. The method of claim 1, further comprising detecting the empty status of said FIFO memory if said distance between the values of said first counter to the value of said second counter is equal to 0.

3. The method of claim 1, further comprising: providing a third Gray-code count configured to take values out of 2*N possible values;initializing said third Gray-code count to the value N+J;incrementing said third Gray-code count on each said write operation, and setting the content of said third count to the value 0 if the value of said third count reaches 2*N;monitoring the distance of the value of said third count to the value of said second count; anddetecting the full status of said FIFO memory if said distance between the value of said third count to the value of said second count is equal to 0.

4. The method of claim 1, further comprising: providing a third Gray-code count configured to take values out of 2*N possible values;initializing said third Gray-code count to the value N+J;incrementing said third Gray-code count on each said read operation, and setting the content of said third count to the value 0 if the value of said third count reaches 2*N;monitoring the distance of the value of said first count to the value of said third count; anddetecting the full status of said FIFO memory if said distance between the value of said first count to the value of said third count is equal to 0.

5. The method of claim 1, further comprising: 1-hot encoding said first Gray-code count and said second Gray-code count,shifting to the left by N-bit said 1-hot encoded value of said first Gray-code count;monitoring the difference between said encoded and shifted value of said first count and said encoded value of said second count; anddetecting the full status of said FIFO memory if said encoded and shifted value of said first count and said encoded value of said second count are equal.

6. The method of claim 4, further comprising synchronizing at least one of said first, second or third Gray-code count.

7. The method of claim 1, further comprising: providing a first and a second binary counts each configured to take values out of N possible values;initializing said first and second binary counts to the same value;incrementing said first binary count on each said write operation, and setting said first binary count to the value 0 if the value of said first binary count reaches N;incrementing said second binary count on each said read operation, and setting said second binary count to the value 0 if the value of said second binary count reaches N;determining a write address for said write operation to said FIFO memory from said value of said first binary count; anddetermining a read address for said read operation from said FIFO memory from said value of said second binary count.

8. The method of claim 1, further comprising: determining a write address for said write operation to said FIFO memory from said value of said first Gray-code count; anddetermining a read address for said read operation from said FIFO memory from said value of said second Gray-code count.

9. A system for detecting the status of a FIFO memory during write/read operations, said FIFO memory having N memory locations, the system comprising: a first and a second Gray-code counter each configured to take values out of 2*N possible values, wherein said first and second Gray-code counters are configured to be initialized to a value J, and incremented on each said write operation and each said read operation, respectively, and wherein each of said first and second Gray-code counters are configured to be set to the value 0 if their count values reach 2*N; anda comparator block for monitoring the distance of the value of said first counter to the value of said second counter and detecting the full status of said FIFO memory if said distance of the value of said first counter to the value of said second counter is equal to N.

10. The system of claim 9, further comprising a comparator block for monitoring the distance of the value of said first counter to the value of said second counter and detecting the empty status of said FIFO memory if said distance of the value of said first counter to the value of said second counter is equal to 0.

11. The system of claim 9, further comprising: a third Gray-code counter configured to take values out of 2*N possible values, wherein said third Gray-code counter is configured to be initialized to a value J+N, and incremented on each said write operation, and wherein said third Gray-code counter is configured to be set to the value 0 if its count value reaches 2*N; anda comparator block for monitoring the distance of the value of said third counter to the value of said second counter and detecting the full status of said FIFO memory if said distance of the value of said third counter to the value of said second counter is equal to 0.

12. The system of claim 9, further comprising: a third Gray-code counter configured to take values out of 2*N possible values, wherein said third Gray-code counter is configured to be initialized to a value J+N, and incremented on each said read operation, and wherein said third Gray-code counter is configured to be set to the value 0 if its count value reaches 2*N; anda comparator block for monitoring the distance of the value of said first counter to the value of said third counter and detecting the full status of said FIFO memory if said distance of the value of said first counter to the value of said second counter is equal to 0.

13. The system of claim 9, further comprising: first and a second 1-hot encoders configured to encode the value of said first Gray-code counter and said second Gray-code counter;a shifter configured to shift by N-bit to the left said 1-hot encoded value of said first Gray-code counter; anda comparator block for monitoring the difference between said shifted and encoded value of said first counter and said encoded value of said second counter and detecting the full status of said FIFO memory if said encoded and shifted value of said first count and said encoded value of said second count are equal.

14. The system of claim 11 further comprising at least one synchronizer configured for synchronizing at least one of said first, second or third Gray-code counter.

15. The system of claim 9 further comprising a first and a second binary counter configured to take values out of N possible values, wherein said first and said second binary counter are configured to be initialized to the same value, and incremented on each said write operation and each said read operation, respectively, and wherein each of said first and second binary counters are configured to be set to the value 0 if their count values reach N, and wherein said first and said second binary counters are configured to provide the write address for said write operation, and the read address for said read operation, respectively.

16. The system of claim 9 further comprising: a first converter block for converting said value of said first Gray-code counter into the write address for said write operation to said FIFO memory; anda second converter block for converting said value of said second binary counter into the read address for said read operation from said FIFO memory.

17. The system of claim 9 in combination with said FIFO memory.

18. The system of claim 17, wherein said FIFO memory comprises a RAM memory.

19. The system of claim 18, wherein said FIFO memory comprises a dual port RAM memory.

20. The system of claim 17, wherein said FIFO memory is emulated by a write address decoder, a read address decoder, and a set of registers.

21. The system of claim 9, further comprising data synchronization between two clock domains.

22. A method of detecting the status of a FIFO memory, the method comprising: providing first and second Gray-code counts each;initializing said first and second Gray-code counts;incrementing said first Gray-code count on a write operation;incrementing said second Gray-code count on a read operation;monitoring the distance of the value of said first count to the value of said second count; anddetecting the full status of said FIFO memory if said distance of the value of said first count to the value of said second count is equal to N, wherein N is the number of memory locations in the FIFO memory.