Patent Application
20080088388
The foregoing features and other features of the present invention now are described with reference to the drawings. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures:
Although the circuit configurations illustrated in
The present invention provides an iterative technique in which a set of goals are defined and the circuit is modified until the deviation from the goals is minimized. Iterative techniques are used because a mathematical solution in closed form is not available. When continuously variable internal input and output impedances are present between stages, a closed form solution might not exist.
To better understand and appreciate the invention the operation of a simplified version of a shunt PIN diode antenna T/R switch is discussed below.
There is a class of switches used in transceiver applications whose function is to connect an antenna to a transmitter (exciter) in the transmit state and to the receiver during the receive state. PIN diodes are often used as active elements in these switches.
When diode 126 in the path to receiver port 134 is turned on, diode 126 shorts out the signals in this path and presents an inductor 124, shorted to ground through diode 126 in antenna 122. The values of inductor 108 and capacitor 106 can be adjusted to match out inductor 124 and result in matched signal flow to transmitter port 102.
Alternatively, if diode 110 in the path to transmitter port 102 is turned on, diode 110 shorts the inductor 112 to ground. Inductor 128 and capacitor 130 values then allow matched power to flow from antenna 122 to receiver port 134.
In addition to providing impedance match, proper selection and adjustment of the inductor and capacitor values can be used to lower impedance at node 109 and node 125. Lower impedance at these nodes lowers the RF/microwave voltage amplitude, resulting in improved performance.
Choke 138 and choke 149 are connected between voltage sources 136 and 142 respectively, to provide DC returns to the bias currents and open circuit for the RF signal.
Capacitor 114, connected between inductor 112 and capacitor 116, and capacitor 118, connected between inductor 124 and capacitor 116, function as DC blocking capacitors that contribute little to the matching tasks, although they can be used for matching if needed.
Capacitors 106 and 130, in addition to being used for matching functions, also function as DC blocking capacitors. Wires 104 and 132 on the input and output ports are bond wires, that have an important effect on matching, but wires 104 and 132 are parasitic components in general and exist by necessity only.
In this embodiment, simulation environment 350 includes Advanced Design System (ADS) 352 available from Agilent Technology, Inc. ADS is a multiengine simulation system that includes a harmonic balance simulator 356 that calculates and optimizes voltages at the internal circuit nodes. The ADS 352 also includes a simulation control means 354, a simulation result presentation means 360, and a simulation model library 358.
In one embodiment, the methodology of the present invention incorporates a number of simulators and simulation steps to arrive at a desired solution. The stated goal is the optimization of a PIN diodes performance in the circuit. It is accomplished by controlling the local RF impedance in the region of the diodes by impedance matching, over a range of frequencies, modifying source and load impedances, which are different at each frequency.
Referring again to
lumped elements, capacitors 224, 252, 264 and 322 and resistors 234, 274, 308318, 320 and 232;
PIN diode models 236, 254, 260, 262, 268 and 278 including resistors and capacitors, where the resistors are set to either a high or a low value corresponding to the ON and OFF states;
PAD sub circuit blocks 258, 302, 304 and 280;
microstrip transmission line models, MLIN 202, 204, 206, 208, 212, 216, 226, 228, 238, 234, 240, 244, 246248, 250, 266, 270 and 272;
wire models, 284 and 314;
a rectangular microstrip inductor model, MRIND 282 discontinuity models, MCROSS 220 and 222;
data blocks 210, 214, 220, 286, 290, 292, 294298, 300, 310 and 312; and
a port 296.
Transmission line model MLIN, MRIND MCROSS WIRE used in the simulation are part of the simulator model library 358 and the represent the element's physical structures by effective lumped element inductors and capacitors whose value is automatically adjusted.
The data blocks 366 represent other discontinuities that are characterized by calculating microwave scattering, or S parameters using a Lull-wave numerical electromagnetic field solver.
To exemplify the operation of the invention, with no intent to limit the invention, a simulation and optimization are performed using simulation model 200 as applied to the circuit 100.
In this example, the first run of the simulation using small signal S parameter provides transfer function to each external port terminated in the normalizing impedance required for S parameters.
Having the required transfer function allows the complete characterization of the circuit by a harmonic balance simulator.
Harmonic balance simulation facilitates the time domain characterization of the circuit and provides information on voltage amplitude at both internal nodes and external ports directly.
Time series waveform in
Time series waveform in
The RF/microwave signal voltage on the diodes, for a given 0.5-Watt transmitter power level, was reduced from the peak value of 9V over a 2:1 Voltage Standing Wave Ratio (VSWR) condition to less than 6.5V, allowing an existing 7V power supply to be used for the control bias voltage
Table 1 shows the relative values of the variables both prior to and after the optimization.
No changes to the circuit were necessary in this case, only a coordinated optimization of component values throughout the circuit. No compromise in the desired small signal performance is experienced.
Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and are not limiting. Many other applications and embodimnents of the present invention will be apparent in light of this disclosure and the following claims
