Patent Application
20080065834
The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings.
In the current computing environment it is very common for the data to be kept in a data format that is portable between different software and different hardware platforms. It is often kept in some industry standard format. This format is not the format that the machine is designed to operate on natively. In
In a multiprocessor computer system, 200, there is a main memory, 210, where the data in both the common interchange format and the local machine format will reside. These data objects will be brought into and out of the local cache on each microprocessor, 230, 240, and 250. In our system there is a layer of shared cache, 220. It is often the case that more than one thread or processor may wish to access this operand data, and thus a benefit if the data is held in the common cache structure.
In the microprocessor, 300, there are many components. In particular there is a data cache, 310, an instruction unit, 320, and execution unit(s), 330. When the instruction unit decodes instructions it makes operand requests, 350, to the data cache. These operand requests, 350, have attribute information, 351, that data the data cache, 300, about the request type and other information about the request. It also forwards information on to the execution unit(s), 330, on the instruction execution information link, 352. When the operand was a fetch request data flows from the data cache, 310, to the execution unit(s), 330, via the data fetch bus, 353. When the operand request was a store the execution unit(s), 330, sends the updated data on the store data bus, 354.
Inside the data cache, 400, there are multiple elements. In this case the data cache has a set associativity of M where M is greater than 1. In this cache there are data arrays, 410, 411, and 412 where the data for each set is stored. There are directory arrays, 420, 421, and 422 that indicate what data is present in the arrays. In order to determine a line replacement target for when new data is brought into the cache there MRU (most recently used)/LRU (least recently used) bits for each set, 430, 431, and 432, that are kept for each set and that are updated based on access patterns and original installation values.
Inside the Instruction unit, 500, there are several blocks. There is the instruction decode unit, 510, which determines the characteristics of the instruction that is decoded and send those characteristics, 540, to the instruction queue, 520, and the operand fetch logic, 530. The instruction queue, 520, will forward information about the instruction to execute to the execution units(s), 330. The operand fetch logic, 530, will use this information to send operand requests, 350, and request attributes, 351, to the data cache, 310.
In our invention the instruction decode unit, 510, recognizes when the instruction that is about to execute is an instruction from an application thread that is designed to convert the common interchange format to a local machine format or local machine format to common interchange format. It informs the operand fetch logic, 530, of this fact. When the operand fetch logic, 530, sends the operand request, 350, to the data cache, 310, it will also for this operand set a bit in the attribute information, 351, that indicates to modify the MRU/LRU information. Then inside the data cache, 400, the bit that was sent with the operand request, 350, in the attribute information, 351, that said to modify the MRU/LRU information will alter how the MRU/LRU bits are set in 430, 431, or 432 when either the common interchange format data or the local machine is first installed in the cache. This is done such that when these very large data operands which are larger than the size of the microprocessor data cache are brought into the data cache they will be installed over and over again into the same set and not into multiple sets. In this way that data that will be converted will installed in the same given set as each line that hits the same congruence class s installed in the data cache. This allows data that will be used when the conversion completes to remain active in the cache.
The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof.
As one example, one or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable application program code for providing and facilitating the capabilities of the present invention. The application code may be an article of manufacture which can be included as a part of a computer system or sold separately.
The diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified so long as the claimed result is accomplished. All of these variations are considered a part of the claimed invention.
While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.
