Power regulation for a microelectronic device such as a microprocessor must include a steady voltage and an ability to respond to dynamic current demands of the processor.
For example, as a microprocessor executes instructions, particularly at faster rates, severe power transients are likely to occur. These severe current transients, if not properly regulated, can cause noise on the power supply that can induce errors in the microprocessor.
Typical power regulation systems include a collection of decoupling capacitors that are placed across the load between the power supply and ground, in combination with a voltage regulator. On-chip decoupling techniques, e.g., decoupling capacitors integrated on the die, generally require a relatively large chip area, store a relatively small charge compared to the transient load demands of the microprocessor, and tend to reduce reliability of the microprocessor.
Typical off-chip decoupling generally has limited effectiveness because of the parasitic inductance in the power supply leads. In addition, off-chip as well as on-chip active voltage regulation employing conventional circuit design approaches generally lack the bandwidth to respond to fast load transients. Further, typical off-chip regulation approaches generally have limited bandwidth and effectiveness in responding to the transients because of the parasitic inductance between the regulation source and the load.
Methods and apparatus for regulating a power supply according to various aspects of the present invention operate in conjunction with an electronic system configured to interface with a primary voltage regulator. The electronic system comprises a load configured to receive supply current from the primary voltage regulator and a secondary voltage regulator. The secondary voltage regulator includes at least one current source coupled to the load and is configured to provide current to the load. The secondary voltage regulator further comprises a control circuit coupled to the current source and the load, which determines a current demand for the load exceeding the supply current received from the primary voltage regulator, and adjusts the current provided to the load by the current source according to the current demand.
A more complete understanding of the present invention may be derived by referring to the detailed description and claims when considered in connection with the figures, where like reference numbers refer to similar elements throughout the figures, and:
Referring now to
The load 20 receives a supply current from the primary voltage regulator 22 and secondary voltage regulator 10, and may comprise any system that consumes electrical current, such as a microprocessor-based device or an integrated circuit device. The load 20 may comprise a dynamic load, which varies its power consumption over time.
The load 20 is configured for receiving a regulated supply current via an output voltage Vcc, as regulated and provided from the primary voltage regulator 22 and the secondary voltage regulator 10. In the present embodiment, the load 20 comprises internal circuitry, with an activity level that varies depending on the function the internal circuitry is performing at any given time, resulting in increases and decreases in load current demanded.
The primary voltage regulator 22 provides a regulated output voltage to the load 20. The primary voltage regulator 22 may comprise any appropriate supply, such as a conventional regulated voltage supply. In the present embodiment, the primary voltage regulator 22 comprises a voltage regulator configured within a linear loop to facilitate a well-controlled, regulated output voltage Vcc approximating a target voltage, such as 1.5 or 1.8 volts. In particular, the present primary voltage regulator 22 may comprise a switching regulator for high efficiency or a non-switching regulator with less efficiency, and is configured to operate from a supply voltage V1, such as a 12-volt supply. The primary voltage regulator 22 may interface with the load 20 in any manner, such as via conventional connections that may generate parasitic inductances (not shown).
The primary voltage regulator 22 may be configured to drive the output voltage Vcc to the target voltage VREF. The difference between output voltage Vcc, and the target voltage comprises an error voltage VERROR, i.e., Vcc−VREF=VERROR. The primary voltage regulator 22 may be configured to regulate the error voltage VERROR to approximately zero volts in a linear manner, such that the response of primary voltage regulator 22 is proportional to the error voltage VERROR. The primary voltage regulator 22 may exhibit a slow response, such as about 100 ns to 10 microseconds.
In addition, the bandwidth of the primary voltage regulator 22 may be limited, such as to maintain stable operation of the linear loop in the presence of the parasitic inductances. In the present embodiment, the bandwidth of the primary voltage regulator 22 is limited to approximately 100 kHz to 2 MHz, though the range of values may be selected according to the configuration of the electronic system or any other suitable criteria. The primary voltage regulator 22 may be configured for normal regulation within the linear loop, i.e., for addressing small changes in the output voltage, such as smaller error voltages VERROR within selected undervoltage and/or overvoltage threshold levels.
The supplementary supply provides additional current to the load 20 when needed, for example to sustain the output voltage Vcc required by the load 20 and provide additional time for the primary voltage regulator 22 to accommodate the power demand changes at the dynamic load 20 during normal regulation. The supplementary supply may also be configured to filter dynamic switching currents, such as currents caused by parasitic inductances. The supplementary supply may comprise any suitable supply, such as one or more batteries or capacitors. In the present embodiment, the supplementary supply comprises a passive supply, such as a first bypass capacitor C1 and a second bypass capacitor C2 coupled across the load 20. The bypass capacitors C1, C2 provide decoupling capacitances across the load 20. The bypass capacitors C1, C2 may be configured to filter dynamic switching currents of the primary regulator 22 and provide dynamic charge to the load 20 with a response time of approximately I microsecond.
The secondary voltage regulator 10 provides improved regulation of the supply current for the dynamic load 20 by adjusting the current provided to the load 20, for example by providing a positive current (i.e., providing additional current) or a negative current (i.e., draining excess current). The secondary voltage regulator 10 may be configured in any manner to adjust the voltage applied to the load 20 according to the demand of the load 20 and/or the current provided by other sources. In the present embodiment, the secondary voltage regulator 10 is configured for regulating dynamic undervoltage and/or overvoltage conditions at the load 20 that are beyond the regulation capability of the primary voltage regulator 22 and the bypass capacitors C1, C2. For example, the secondary voltage regulator 10 may be configured within a wideband, non-linear loop for determining undervoltage and/or overvoltage conditions at the dynamic load 20. The secondary voltage regulator 10 may monitor changes in the output voltage Vcc to determine when the error voltage VERROR exceeds predetermined undervoltage and/or overvoltage threshold values, and adjust the current, positively or negatively, provided to the load 20 accordingly. The secondary voltage regulator 10 may include a plurality of secondary voltage regulator circuits, with each secondary voltage regulator circuit configured to identify undervoltage and/or overvoltage conditions and provide current to and/or sink current from the load 20 accordingly.
The response of the secondary voltage regulator 10 may be configured to control the magnitude of the error voltage VERROR. The secondary voltage regulator 10 may be configured with a nonlinear response, however, such that the response to the change in current demand is not linearly proportional to the error voltage VERROR. The nonlinear response tends to inhibit conflicting control efforts exerted by the primary voltage regulator 22 and the secondary voltage regulator 10. In addition, the secondary voltage regulator 10 may be configured with a fast response time to generate corrective action before the primary voltage regulator 22 reacts to the error voltage VERROR. For example, in the present embodiment, the secondary voltage regulator 10 is configured to have a wideband control loop with a response time between about 100 ps to 10 ns.
The secondary voltage regulator 10 may be configured in any appropriate manner to provide the secondary voltage regulation. For example, a secondary voltage regulator 10 according to various aspects of the present invention comprises a current-controlled transient regulator (CCTR) operating as a supplemental voltage regulator. The present CCTR is configured to determine the current demand of the load 20 by monitoring the output voltage Vcc and adjust the voltage towards the target voltage VREF based on a nonlinear response. The present CCTR is also configured to provide a fast response to provide more immediate regulation than is available from the primary voltage regulator 22. In one exemplary embodiment, the CCTR comprises a control circuit 12 and at least one current source 11, 12. The current source provides a positive and/or negative current to the load 20. The control circuit 12 determines the current demanded by the load 20 that exceeds the supply current received from the primary voltage regulator t1 and/or other sources, and adjusts the current provided to the load 20 by the current source 11, 12 according to the current demand.
The CCTR may be configured to exhibit a selected frequency response, for example to complement the frequency response of the primary voltage regulator 22. Referring to
The control circuit 12 monitors the dynamic demand of the load 20 and adjusts the current provided to the load 20 by the current source 11, 12 according to the demand, such as the magnitude of the change in the demand. The control circuit 12 may be configured in appropriate manner to monitor the load 20 demand. For example, the control circuit 12 may be configured to compare the current demand as indicated by the output voltage Vcc to one or more threshold voltages. In the present embodiment, at least one comparator device can be configured for comparing changes in the output voltage Vcc to a predetermined undervoltage threshold or an overvoltage threshold. The control circuit 12 may then control the current source 11, 12 to provide a positive current to the load 20 for undervoltage conditions or a negative current for overvoltage conditions. In one embodiment, the CCTR may be configured with a single comparator device and a single current source for determining undervoltage or overvoltage conditions, and for sourcing current to or sinking current from the load 20.
For example, the present control circuit 12 comprises at least one comparator, such as a high speed device configured to compare at least two voltages and generate a corresponding output signal. In the present embodiment, the control circuit 12 comprises one or more comparator devices configured to compare the voltage provided to the load to threshold voltages. More particularly, the present control circuit 12 comprises an upper threshold comparator 15 and a lower threshold comparator 13. The lower threshold comparator 13 is configured to detect undervoltage conditions, i.e., the load voltage Vcc is less than the difference between the reference voltage VREF and an undervoltage threshold Δb1. In one embodiment, the lower threshold comparator 13 has a positive input terminal coupled to an undervoltage condition signal, VREF−Δb1, and a negative input terminal coupled to the load 20 in a voltage feedback arrangement to measure or sense the load voltage Vcc . The comparator connections may be coupled directly to other circuit elements by conductive material or indirectly coupled via other electronic components.
Likewise, the upper threshold comparator 15 is configured to detect overvoltage conditions, i.e., the load voltage Vcc is greater than the sum of the reference voltage VREF and an overvoltage threshold Δt1. In one embodiment, the upper threshold comparator 15 has a positive input terminal coupled to an overvoltage condition signal, VREF−Δt1, and a negative input terminal coupled to the load 20 in a voltage feedback arrangement to measure or sense load voltage Vcc.
The reference voltage VREF may be generated in any appropriate manner, such as fixed at a voltage level, for example approximately 1.8 volts. In addition, the reference voltage VREF can be provided as a readily configurable voltage derived from another voltage or current references. For example, reference voltage VREF can comprise a filtered or representative voltage based on the average load current or average load voltage Vcc over some fixed or variable period of time.
The thresholds may be selected according to any suitable criteria, and may be symmetrical with respect to the reference voltage VREF. The undervoltage threshold Δb1 and the overvoltage threshold Δt1, can suitably be configured at various predetermined levels, such as between approximately 1 mV and hundreds of millivolts, depending on the desired operation of secondary voltage regulator 10. In addition, the undervoltage threshold Δb1 may be selected to inhibit low voltage failures, such as logic failures, while the overvoltage threshold Δb1, me be selected to reduce power dissipation that can stress integrated circuitry within dynamic load 20. Thus, referring to
The current source 11, 12 is coupled to the load 20, directly or indirectly, and provides positive or negative current to the load 20. The current source 11, 12 may be controlled by the control circuit 12. The current source 11, 12 may comprise any appropriate system for providing or drawing current to or from the load 20. In one embodiment, the current source 11, 12 regulates the output voltage Vcc The current delivered by the current source 11, 12 to the load 20 may be controlled in magnitude and/or duration and may approximately match the current demands of the load 20. Further, the current source 11, 12 may be configured to inhibit effects upon the impedance of the power delivery network at Vcc as well as to minimize or eliminate production of transient noise at the load 20.
For example, the present secondary voltage regulator 10 comprises at least two current sources 11, 12, such as a supply current source 11 and a drain current source 12. Each current source 11, 12 may be controlled by a comparator 13, 15, and may have a relatively high impedance, such as in the range of 10-100 ohms. In the present embodiment, the output of the lower threshold comparator 13 is coupled to the supply current source 11 to identify undervoltage conditions and provide additional current to the load 20. Likewise, the output of the upper threshold comparator 15 is coupled to the drain current source 12 to identify overvoltage conditions and drain excess current from the load 20. The supply current source 11 may be supplied current by a supply voltage V2, and the drain current source 12 may be coupled to ground. The current sources 11, 12 may be directly or indirectly coupled to the load 20 in any appropriate manner, such as via connection from a die pad or other connection mechanism, to allow a positive or negative current 13 to flow to or from the load 20 during the sourcing and sinking of current.
The load 20 and the secondary voltage regulator 10 may be configured to optimize voltage regulation. For example, the secondary voltage regulator 10 and the second bypass capacitor C2 may be physically located on the same package as the load 20, such as on the microprocessor package, and may be coupled to the load 20. Referring to
The secondary voltage regulator 10 is configured to respond to dynamic changes in the load 20 current to minimize power supply voltage transients. For example, in one embodiment, the load 20 comprises a microprocessor, which operates in a range of 0.5V to 2V to and draws current in the range of 10 A to 100 A. As the current of the microprocessor load 20 increases, such as a ramp up or step up or other increase in current, for example from 1 A to 10 A, or from 10 A to 100 A, over a relatively short time period, for example from 1 ns to 100 ns, the sense and control circuit 12 identifies whether the output voltage drops below the lower threshold and controls the supply current source 11 connected between V2 and Vcc to minimize the transient voltage change on Vcc at the microprocessor load 20.
Likewise, as the current demand of the microprocessor load 20 decreases, such as a ramp down or step down or other decrease in current, by example from 10 A to 1 A, or from 100 A to 10 A, over a relatively short time period, for example from 1 ns to 100 ns, the sense and control circuit 12 identifies whether the output voltage exceeds the upper threshold and controls the drain current source 12 connected between Vcc and ground to minimize the transient voltage change on Vcc at the microprocessor load 20. Referring to
Thus, in the event of a predetermined change in the error voltage in the negative direction, the secondary voltage regulator 10 provides a positive current output. Similarly, upon a predetermined change in the error voltage in the positive direction (a change that is larger than the change in the negative direction in the present embodiment), the secondary voltage regulator 10 drains current from the load 20.
While the load voltage Vcc remains between the threshold voltages, the secondary voltage regulator 10 provides neither a positive nor a negative current to the load 20.
Further, the secondary voltage regulator 10 controlled current response approximately equals the dynamic current demands of the microprocessor load 20 that are beyond the response of the primary voltage regulator 22 and/or bypass capacitors Cl, C2. The secondary voltage regulator 10 reduces the dynamic charge required by the primary regulator 22 and capacitors C1, C2.
Referring to
Referring to
The present invention has been described above with reference to various exemplary embodiments. However, changes and modifications may be made to the exemplary embodiments without departing from the scope of the present invention. For example, the various components may be implemented in alternate ways, such as, for example, by providing other configurations of current sources and comparators. These alternatives can be suitably selected depending upon the particular application or in consideration of any number of factors associated with the operation of the system. These and other changes or modifications are intended to be included within the scope of the present invention.
The present application claims the benefit of U.S. Provisional Patent Application 60/723,370, filed Oct. 3, 2005, entitled “Current Controlled Transient Regulator and Method of Using”, and is a continuation in part of U.S. Nonprovisional Application Serial No. 09/945,187, entitled, “Apparatus and System for Providing Transient Suppression Power Regulation”, filed on Aug. 31, 2001, and assigned to the assignee of the present application.
Number | Date | Country | |
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60723370 | Oct 2005 | US |
Number | Date | Country | |
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Parent | 09945187 | Aug 2001 | US |
Child | 11538218 | Oct 2006 | US |