METHODS AND APPARATUS FOR DECODING VIDEO SIGNALS USING MOTION COMPENSATED EXAMPLE-BASED SUPER-RESOLUTION FOR VIDEO COMPRESSION

Abstract

Methods and apparatus are provided for decoding video signals using motion compensated example-based super-resolution for video compression. An apparatus includes an example-based super-resolution processor for receiving one or more high resolution replacement patch pictures generated from a static version of an input video sequence having motion, and performing example-based super-resolution to generate a reconstructed version of the static version of the input video sequence from the one or more high resolution replacement patch pictures. The reconstructed version of the static version of the input video sequence includes a plurality of pictures. The apparatus further includes an inverse image warper for receiving motion parameters for the input video sequence, and performing an inverse picture warping process based on the motion parameters to transform one or more of the plurality of pictures to generate a reconstruction of the input video sequence having the motion.

Description

These and other aspects, features and advantages of the present principles will become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.

The present principles may be better understood in accordance with the following exemplary figures, in which:

FIG. 1 is a high-level block diagram showing encoder-side processing for example-based super resolution, in accordance with the previous approach;

FIG. 2 is a high-level block diagram showing decoder-side processing for example-based super resolution, in accordance with the previous approach;

FIG. 3 is a diagram showing a clustering process used for example-based super-resolution, in accordance with the previous approach;

FIG. 4 is a diagram showing an exemplary transformation of a video with object motion to a static video, in accordance with an embodiment of the present principles;

FIG. 5 is a block diagram showing an exemplary apparatus for motion compensated example-based super-resolution processing with frame warping for use in an encoder, in accordance with an embodiment of the present principles;

FIG. 6 is a block diagram showing an exemplary video encoder to which the present principles may be applied, in accordance with an embodiment of the present principles;

FIG. 7 is a flow diagram showing an exemplary method for motion compensated exampled-based super-resolution at an encoder, in accordance with an embodiment of the present principles;

FIG. 8 is a block diagram showing an exemplary apparatus for motion compensated example-based super-resolution processing with inverse frame warping in a decoder, in accordance with an embodiment of the present principles;

FIG. 9 is a block diagram showing an exemplary video decoder to which the present principles may be applied, in accordance with an embodiment of the present principles; and

FIG. 10 is a flow diagram showing an exemplary method for motion compensated exampled-based super-resolution at a decoder, in accordance with an embodiment of the present principles.

The present principles are directed to methods and apparatus for motion compensated example-based super-resolution for video compression.

The present description illustrates the present principles. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the present principles and are included within its spirit and scope.

All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the present principles and the concepts contributed by the inventor(s) to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions.

Moreover, all statements herein reciting principles, aspects, and embodiments of the present principles, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

Thus, for example, it will be appreciated by those skilled in the art that the block diagrams presented herein represent conceptual views of illustrative circuitry embodying the present principles. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudocode, and the like represent various processes which may be substantially represented in computer readable media and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.

The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term “processor” or “controller” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (“DSP”) hardware, read-only memory (“ROM”) for storing software, random access memory (“RAM”), and non-volatile storage.

Other hardware, conventional and/or custom, may also be included. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context.

In the claims hereof, any element expressed as a means for performing a specified function is intended to encompass any way of performing that function including, for example, a) a combination of circuit elements that performs that function or b) software in any form, including, therefore, firmware, microcode or the like, combined with appropriate circuitry for executing that software to perform the function. The present principles as defined by such claims reside in the fact that the functionalities provided by the various recited means are combined and brought together in the manner which the claims call for. It is thus regarded that any means that can provide those functionalities are equivalent to those shown herein.

Reference in the specification to “one embodiment” or “an embodiment” of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.

Also, as used herein, the words “picture” and “image” are used interchangeably and refer to a still image or a picture from a video sequence. As is known, a picture may be a frame or a field.

As noted above, the present principles are directed to methods and apparatus for motion compensated exampled-based super-resolution video compression. Advantageously, the present principles provide a way to reduce the number of redundant representative patches and increase the compression efficiency.

In accordance with the present principles, this application discloses a concept of transforming a video segment with significant background and object motion to a relatively static video segment. More specifically, in FIG. 4, an exemplary transformation of a video with object motion to a static video is indicated generally by the reference numeral 400. The transformation 400 involves a frame warping transformation that is applied to Frame 1, Frame 2, and Frame 3 of the video with object motion 410 to obtain Frame 1, Frame 2, and Frame 3 of the static video 420. The transformation 400 is performed before the clustering process (i.e., the encoder-side processing component of the example-based super-resolution method) and the encoding process. The transformation parameters are then sent to the decoder side for recovery. Since the example-based super-resolution method would result in higher compression efficiency for static videos, and the size of the transformation parameter data is usually very small, by transforming the videos with motion to static videos, it is possible to potentially gain compression efficiency for videos with motion.

Turning to FIG. 5, an exemplary apparatus for motion compensated example-based super-resolution processing with frame warping for use in an encoder is indicated generally by the reference numeral 500. The apparatus 500 includes a motion parameter estimator 510 having a first output in signal communication with an input of an image warper 520. An output of the image warper 520 is connected in signal communication with an input of an example-based super-resolution encoder-side processor 530. A first output of the example-based super-resolution encoder-side processor 530 is connected in signal communication with an input of an encoder 540, and provides downsized frames thereto. A second output of the example-based super-resolution encoder-side processor 530 is connected in signal communication with the input of the encoder 540, and provides patch frames thereto. A second output of the motion parameter estimator 510 is available as an output of the apparatus 500, for providing motion parameters. An input of the motion parameter estimator 510 is available as an input to the apparatus 500, for receiving an input video. An output (not shown) of the encoder 540 is available as a second output of the apparatus 500, for outputting a bitstream. The bitstream may include, for example, encoded downsized frames, encoder patch frames, and motion parameters.

It is to be appreciated that the functions performed by the encoder 540, namely encoding, may be omitted, with the downsized frames, the patch frames, and the motion parameters being sent to the decoder side without any compression. However, to save bit rates, the downsized frames and the patch frames are preferably compressed (by the encoder 540) before being sent to the decoder side. Moreover, in another embodiment, the motion parameter estimator 510, the image warper 520, and the example-based super-resolution encoder-side processor 530 may be included in, and part of, a video encoder.

Thus, at the encoder side, before the clustering process is performed, motion estimation is carried out (by the motion parameter estimator 510) and a frame warping process is applied (by the image warper 520) to transform frames with moving objects or background to a relatively static video. The parameters extracted from the motion estimation process are sent to the decoder side through a separate channel.

Turning to FIG. 6, an exemplary video encoder to which the present principles may be applied is indicated generally by the reference numeral 600. The video encoder 600 includes a frame-ordering buffer 610 having an output in signal communication with a non-inverting input of a combiner 685. An output of the combiner 685 is connected in signal communication with a first input of a transformer and quantizer 625. An output of the transformer and quantizer 625 is connected in signal communication with a first input of an entropy coder 645 and a first input of an inverse transformer and inverse quantizer 650. An output of the entropy coder 645 is connected in signal communication with a first non-inverting input of a combiner 690. An output of the combiner 690 is connected in signal communication with a first input of an output buffer 635.

A first output of an encoder controller 605 is connected in signal communication with a second input of the frame ordering buffer 610, a second input of the inverse transformer and inverse quantizer 650, an input of a picture-type decision module 615, a first input of a macroblock-type (MB-type) decision module 620, a second input of an intra prediction module 660, a second input of a deblocking filter 665, a first input of a motion compensator 670, a first input of a motion estimator 675, and a second input of a reference picture buffer 680.

A second output of the encoder controller 605 is connected in signal communication with a first input of a Supplemental Enhancement Information (SEI) inserter 630, a second input of the transformer and quantizer 625, a second input of the entropy coder 645, a second input of the output buffer 635, and an input of the Sequence Parameter Set (SPS) and Picture Parameter Set (PPS) inserter 640.

An output of the SEI inserter 630 is connected in signal communication with a second non-inverting input of the combiner 690.

A first output of the picture-type decision module 615 is connected in signal communication with a third input of the frame ordering buffer 610. A second output of the picture-type decision module 615 is connected in signal communication with a second input of a macroblock-type decision module 620.

An output of the Sequence Parameter Set (SPS) and Picture Parameter Set (PPS) inserter 640 is connected in signal communication with a third non-inverting input of the combiner 690.

An output of the inverse quantizer and inverse transformer 650 is connected in signal communication with a first non-inverting input of a combiner 619. An output of the combiner 619 is connected in signal communication with a first input of the intra prediction module 660 and a first input of the deblocking filter 665. An output of the deblocking filter 665 is connected in signal communication with a first input of a reference picture buffer 680. An output of the reference picture buffer 680 is connected in signal communication with a second input of the motion estimator 675 and a third input of the motion compensator 670. A first output of the motion estimator 675 is connected in signal communication with a second input of the motion compensator 670. A second output of the motion estimator 675 is connected in signal communication with a third input of the entropy coder 645.

An output of the motion compensator 670 is connected in signal communication with a first input of a switch 697. An output of the intra prediction module 660 is connected in signal communication with a second input of the switch 697. An output of the macroblock-type decision module 620 is connected in signal communication with a third input of the switch 697. The third input of the switch 697 determines whether or not the “data” input of the switch (as compared to the control input, i.e., the third input) is to be provided by the motion compensator 670 or the intra prediction module 660. The output of the switch 697 is connected in signal communication with a second non-inverting input of the combiner 619 and an inverting input of the combiner 685.

A first input of the frame ordering buffer 610 and an input of the encoder controller 605 are available as inputs of the encoder 600, for receiving an input picture. Moreover, a second input of the Supplemental Enhancement Information (SEI) inserter 630 is available as an input of the encoder 600, for receiving metadata. An output of the output buffer 635 is available as an output of the encoder 100, for outputting a bitstream.

It is to be appreciated that encoder 540 from FIG. 5 may be implemented as encoder 600.

Turning to FIG. 7, an exemplary method for motion compensated example-based super-resolution at an encoder is indicated generally by the reference numeral 700. The method 700 includes a start block 705 that passes control to a function block 710. The function block 710 inputs a video with object motion, and passes control to a function block 715. The function block 715 estimates and saves motion parameters for the input video with object motion, and passes control to a loop limit block 720. The loop limit block 720 performs a loop for each frame, and passes control to a function block 725. The function block 725 warps the current frame using the estimated motion parameters, and passes control to a decision block 730. The decision block 730 determines whether or not processing of all frames is finished. If the processing of all frames is finished, then control is passed to a function block 735. Otherwise, control is returned to the function block 720. The function block 735 performs example-based super-resolution encoder-side processing, and passes control to a function block 740. The function block 740 outputs downsized frames, patch frames, and motion parameters, and passes control to an end block 799.

Turning to FIG. 8, an exemplary apparatus for motion compensated example-based super-resolution processing with inverse frame warping in a decoder is indicated generally by the reference numeral 800. The apparatus 800, including decoder 810, processes the signals generated by the apparatus 500, including encoder 540, described above. The apparatus 800 includes a decoder 810 having an output in signal communication with a first input and a second input of an example-based super-resolution decoder-side processor 820, and respectively provides (decoded) downsized frames and patch frames thereto. An output of the example-based super-resolution decoder-side processor 820 is also connected in signal communication with the input of the inverse frame warper 830, for providing super-resolved video thereto. An output of the inverse frame warper 830 is available as an output of the apparatus 800, for outputting video. An input of the inverse frame warper 830 is available for receiving the motion parameters.

It is to be appreciated that the functions performed by the decoder 810, namely decoding, may be omitted, with the downsized frames and the patch frames being received by the decoder side without any compression. However, to save bit rates, the downsized frames and the patch frames are preferably compressed at the encoder side before being sent to the decoder side. Moreover, in another embodiment, the example-based super-resolution decoder-side processor 820 and inverse frame warper may be included in, and part of, a video decoder.

Thus, at the decoder side, after the frames are recovered by example-based super-resolution, a reverse warping process is conducted to transform the recovered video segment to the coordinate systems of the original video. The reverse warping process uses the motion parameters estimated at and sent from the encoder side.

Turning to FIG. 9, an exemplary video decoder to which the present principles may be applied is indicated generally by the reference numeral 900. The video decoder 900 includes an input buffer 910 having an output connected in signal communication with a first input of an entropy decoder 945. A first output of the entropy decoder 945 is connected in signal communication with a first input of an inverse transformer and inverse quantizer 950. An output of the inverse transformer and inverse quantizer 950 is connected in signal communication with a second non-inverting input of a combiner 925. An output of the combiner 925 is connected in signal communication with a second input of a deblocking filter 965 and a first input of an intra prediction module 960. A second output of the deblocking filter 965 is connected in signal communication with a first input of a reference picture buffer 980. An output of the reference picture buffer 980 is connected in signal communication with a second input of a motion compensator 970.

A second output of the entropy decoder 945 is connected in signal communication with a third input of the motion compensator 970, a first input of the deblocking filter 965, and a third input of the intra predictor 960. A third output of the entropy decoder 945 is connected in signal communication with an input of a decoder controller 905. A first output of the decoder controller 905 is connected in signal communication with a second input of the entropy decoder 945. A second output of the decoder controller 905 is connected in signal communication with a second input of the inverse transformer and inverse quantizer 950. A third output of the decoder controller 905 is connected in signal communication with a third input of the deblocking filter 965. A fourth output of the decoder controller 905 is connected in signal communication with a second input of the intra prediction module 960, a first input of the motion compensator 970, and a second input of the reference picture buffer 980.

An output of the motion compensator 970 is connected in signal communication with a first input of a switch 997. An output of the intra prediction module 960 is connected in signal communication with a second input of the switch 997. An output of the switch 997 is connected in signal communication with a first non-inverting input of the combiner 925.

An input of the input buffer 910 is available as an input of the decoder 900, for receiving an input bitstream. A first output of the deblocking filter 965 is available as an output of the decoder 900, for outputting an output picture.

It is to be appreciated that decoder 810 from FIG. 8 may be implemented as decoder 900.

Turning to FIG. 10, an exemplary method for motion compensated example-based super-resolution at a decoder is indicated generally by the reference numeral 1000. The method 1000 includes a start block 1005 that passes control to a function block 1010. The function block 1010 inputs downsized frames, patch frames, and motion parameters, and passes control to a function block 1015. The function block 1015 performs example-based super-resolution decoder-side processing, and passes control to a loop limit block 1020. The loop limit block 1020 performs a loop for each frame, and passes control to a function block 1025. The function block 1025 performs inverse frame warping using the received motion parameters, and passes control to a decision block 1030. The decision block 1030 determines whether or not processing of all frames is finished. If the processing of all frames is finished, then control is passed to a function block 1035. Otherwise, control is returned to the function block 1020. The function block 1035 outputs recovered video, and passes control to an end block 1099.

The input video is divided into Groups of Frames (GOF). Each GOF is a basic unit for motion estimation, frame warping and example-based super-resolution. One of the frames (e.g., the frame in the middle or beginning) in a GOF is chosen as a reference frame for motion estimation). The GOFs can have either fixed or variable lengths.

Motion Estimation

Motion estimation is used to estimate the displacement of the pixels in a frame relative to a reference frame. Since the motion parameters have to be sent to the decoder side, the number of motion parameters should be as small as possible. Therefore, it is preferable to choose a certain parametric motion model that is governed by a small number of parameters. For example, in the current system disclosed herein, a planar motion model that can be characterized by 8 parameters is employed. Such a parametric motion model is able to model the global motion between frames, such as translation, rotation, affine warp, projective transformation, and so forth, which is common in many different types of videos. For example, when the camera pans, the camera panning results in translational motion. Foreground object motion may not be very well captured by this model, but if the foreground objects are small and the background motion is significant, then the transformed video would remain mostly static. Of course, the use of a parametric motion model capable of being characterized by 8 parameters is merely illustrative and, thus, other parametric motion models capable of being characterized by more than 8 parameters, less than 8 parameters, or even with 8 parameters where one or more are different than the aforementioned model, may also be used in accordance with the teachings of the present principles, while maintaining the spirit of the present principles.

Without loss of generality, it is presumed that the reference frame is H₁, and the rest of the frames in a GOF are H_i (i=2, 3, . . . , N). The global motion between two frames H_i and frame H_j actually can be characterized by transformations that move the pixels in H_i to the positions of their corresponding pixels in H_j, or vice versa. The transformation from H_i to H_j is denoted by Θ_ij, and its parameters are denoted by θ_ij. The transformation Θ_ij can then be used to align (or warp) H_i to H_j (or vice versa using the inverse model Θ_ji=Θ_ij⁻¹).

Global motion can be estimated using a variety of models and methods and, hence, the present principles are not limited to any particular method and/or model of estimating global motion. As an example, one commonly used model (the model used in the current system referring to herein) is the projective transformation given by:

$\begin{array}{cc}{x}^{\prime }=\frac{a_1x+a_2y+a_3}{c_1x+c_2y+1},y^{\prime }=\frac{b_1x+b_2y+b_3}{c_1x+c_2y+1}& \left(1\right)\end{array}$

The above equations give the new position (x′, y′) in H_j to which the pixel at (x, y) in H_i has moved. Thus, the eight model parameters Θ_ij={a₁, a₂, a₃, b₁, b₂, b₃, c₁, c₂} describe the motion from H_i to H_j. The parameters are usually estimated by first determining a set of point correspondences between the two frames and then using a robust estimation framework, such as RANdom SAmple Consensus (RANSAC) or its variants—for example, the one described in M. A. Fischler and R. C. Bolles, “Random Sample Consensus: A Paradigm for Model Fitting with Applications to Image Analysis and Automated Cartography,” Communications of the ACM, vol. 24, 1981, pp. 381-395 and P. H. S. Torr and A. Zisserman, “MLESAC: A New Robust Estimator with Application to Estimating Image Geometry,” Journal of Computer Vision and Image Understanding, vol. 78, no. 1, 2000, pp. 138-156. Point correspondences between frames can be determined by a number of methods, e.g., extracting and matching SIFT (Scale-Invariant Feature Transform) features—such as the one described in D. G. Lowe, “Distinctive image features from scale-invariant keypoints,” International Journal of Computer Vision, vol. 2, no. 60, 2004, pp. 91-110—or using optical flow—such as the one described in M. J. Black and P. Anandan, “The robust estimation of multiple motions: Parametric and piecewise-smooth flow fields,” Computer Vision and Image Understanding, vol. 63, no. 1, 1996, pp. 75-104.

The global motion parameters are used to warp the frames (excluding the reference frame) in a GOF to align with the reference frame. Therefore, the motion parameters between each frame H_i (i=2, 3, . . . , N) to the reference frame (H₁) have to be estimated. The transformation is invertible and the inverse transformation Θ_ji=Θ_ij⁻¹ describes the motion from H_j to H_i. The inverse transformation is used to warp the resulted frames back to the original frame. The inverse transformation is used at the decoder side for recovering the original video segment. The transformation parameters are compressed and sent through a side channel to the decoder side to facilitate the video recovery process.

Apart from the global motion model, other motion estimation methods such as block-based methods can be used in accordance with the present principles to achieve more accuracy. The block-based methods divide a frame into blocks, and estimate motion models for each block. However, it takes significantly more bits to describe motion using a block-based model.

Frame Warping and Inverse Frame Warping

After the motion parameters are estimated, at the encoder side, a frame warping process is performed to align the non-reference frames to the reference frame. However, it is possible that some areas in a video frame do not obey the global motion model described above. By applying frame warping, these areas will be transformed along with the rest of the areas in the frame. However, this does not create a major problem if these areas are small, because warping of these areas only creates artificial motions of these areas in the warped frame. As long as these areas with artificial motion are small, it would not result in a significant increase of representative patches therefore, overall, the warping process would still be able to reduce the total number of representative patches. Also, the artificial motion of the small areas will be reversed by the inverse warping process.

The inverse frame warping process is conducted at the decoder side to warp the recovered frame from the example-based super-resolution component back to the original coordinate system.

These and other features and advantages of the present principles may be readily ascertained by one of ordinary skill in the pertinent art based on the teachings herein. It is to be understood that the teachings of the present principles may be implemented in various forms of hardware, software, firmware, special purpose processors, or combinations thereof.

Most preferably, the teachings of the present principles are implemented as a combination of hardware and software. Moreover, the software may be implemented as an application program tangibly embodied on a program storage unit. The application program may be uploaded to, and executed by, a machine comprising any suitable architecture. Preferably, the machine is implemented on a computer platform having hardware such as one or more central processing units (“CPU”), a random access memory (“RAM”), and input/output (“I/O”) interfaces. The computer platform may also include an operating system and microinstruction code. The various processes and functions described herein may be either part of the microinstruction code or part of the application program, or any combination thereof, which may be executed by a CPU. In addition, various other peripheral units may be connected to the computer platform such as an additional data storage unit and a printing unit.

It is to be further understood that, because some of the constituent system components and methods depicted in the accompanying drawings are preferably implemented in software, the actual connections between the system components or the process function blocks may differ depending upon the manner in which the present principles are programmed. Given the teachings herein, one of ordinary skill in the pertinent art will be able to contemplate these and similar implementations or configurations of the present principles.

Although the illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the present principles is not limited to those precise embodiments, and that various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present principles. All such changes and modifications are intended to be included within the scope of the present principles as set forth in the appended claims.

Claims

1. An apparatus, comprising: an example-based super-resolution processor for receiving one or more high resolution replacement patch pictures generated from a static version of an input video sequence having motion, and performing example-based super-resolution to generate a reconstructed version of said static version of said input video sequence from said one or more high resolution replacement patch pictures, said reconstructed version of said static version of said input video sequence including a plurality of pictures; andan inverse image warper for receiving motion parameters for said input video sequence, and performing an inverse picture warping process based on said motion parameters to transform one or more of said plurality of pictures to generate a reconstruction of said input video sequence having said motion.

2. The apparatus of claim 1, wherein said example-based super-resolution processor is further for receiving one or more downsized pictures from said input video sequence, said one or more downsized pictures for use in generating said reconstruction of said input video sequence having said motion.

3. The apparatus of claim 1, further comprising a decoder for decoding said motion parameters and said one or more high resolution replacement patch pictures from a bitstream.

4. The apparatus of claim 1, wherein said apparatus is included in a video decoder module.

5. The apparatus of claim 1, wherein said inverse picture warping process aligns a reference picture from among a group of pictures comprised in said plurality of pictures with non-reference pictures from among said group of pictures.

6. A method, comprising: receiving motion parameters for an input video sequence having motion, and one or more high resolution replacement patch pictures generated from a static version of said input video sequence;performing example-based super-resolution to generate a reconstructed version of said static version of said input video sequence from said one or more high resolution replacement patch pictures, said reconstructed version of said static version of said input video sequence comprising a plurality of pictures; andperforming an inverse picture warping process based on said motion parameters to transform one or more of said plurality of pictures to generate a reconstruction of said input video sequence having said motion.

7. The method of claim 6, wherein performing said example-based super-resolution comprises receiving one or more downsized pictures generated from said input video sequence, said one or more downsized pictures for use in generating said reconstruction of said input video sequence having said motion.

8. The method of claim 6, further comprising decoding said motion parameters and said one or more high resolution replacement patch pictures from a bitstream.

9. The method of claim 6, wherein said method is performed in a video decoder.

10. The method of claim 6, wherein said inverse picture warping process aligns a reference picture from among a group of pictures comprised in said plurality of pictures with non-reference pictures from among said group of pictures.

11. An apparatus, comprising: means for receiving motion parameters for an input video sequence having motion, and one or more high resolution replacement patch pictures generated from a static version of said input video sequence;means for performing example-based super-resolution to generate a reconstructed version of said static version of said input video sequence from said one or more high resolution replacement patch pictures, said reconstructed version of said static version of said input video sequence comprising a plurality of pictures; andmeans for performing an inverse picture warping process based on said motion parameters to transform one or more of said plurality of pictures to generate a reconstruction of said input video sequence having said motion.

12. The apparatus of claim 11, wherein said means for performing said example-based super-resolution is further for receiving one or more downsized pictures generated from said input video sequence, said one or more downsized pictures for use in generating said reconstruction of said input video sequence having said motion.

13. The apparatus of claim 11, further comprising means for decoding said motion parameters and said one or more high-resolution replacement patch pictures from a bitstream.

14. The apparatus of claim 11, wherein said inverse picture warping process aligns a reference picture from among a group of pictures comprised in aid plurality of pictures with non-reference pictures from among said group of pictures.