Patent Application
20100245138
The present invention is related to delta-sigma modulators and, more particularly, to techniques to reduce the correlation between the quantization noise and the input signal in such delta-sigma modulators.
Delta-sigma (Δ-Σ) modulators, sometimes referred to as sigma-delta (Σ-Δ) modulators, encode higher resolution signals into lower resolution signals. Delta-sigma modulators have found increasing use in a range of modern electronic components, such as digital-to-analog converters (DACs), analog-to-digital converters (ADCs) and frequency synthesizers. For example, delta-sigma modulators have been proposed or suggested for directly synthesizing RF signals from information carrying digital base band signals.
Delta-sigma modulators typically quantize an input signal and determine a quantization error by comparing the input signal to the quantized output value. The quantization error is often assumed to be uncorrelated to the input signal. More typically, however, the error signal is correlated to the input. Thus, the delta-sigma modulator may suffer from noise coloration due to the correlation of the quantization noise with the input signal, particularly for low resolution quantizers.
A need therefore exists for techniques to reduce the correlation between the quantization noise and the input signal, without significantly degrading the signal to noise ratio.
Generally, methods and apparatus are provided for decorrelating quantization noise in a delta-sigma modulator. According to one aspect of the invention, an input signal is quantized using a predictive delta-sigma modulator, by quantizing the input signal using a quantizer; determining a quantization error associated with the quantizer by subtracting an input to the quantizer from an output of the quantizer: measuring a correlation coefficient between the quantization error and an input to the quantizer; reducing the measured correlation by subtracting a multiple of the input to the quantizer from the quantization error, wherein the multiple is based on the correlation coefficient; generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal.
The correlation coefficient, β, can be obtained, for example, using an IMS algorithm. In a further variation, a tap adaptation of the correlation coefficient, β, employs tap leakage. In yet another variation, a tap adaptation of the correlation coefficient, β, employs a variable step size.
A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings.
The present invention provides improved techniques for reducing the correlation between the quantization noise and the input signal in a delta-sigma modulator.
The quantization error, e(n), is often assumed to be uncorrelated to the input r(n). See, e.g., United States Patent Application entitled “Methods and Apparatus for Direct Synthesis of RF Signals Using Delta-Sigma Modulator,” filed contemporaneously herewith and incorporated by reference herein. More typically, however, the error signal may be correlated to the input. Thus, the delta-sigma modulator 100 may suffer from noise coloration due to the correlation of the quantization noise with the input of the quantizer 110, particularly for low resolution quantizers, such as the one bit quantizers described herein. In order to reduce the effects of the correlation between the quantization noise and the input, a dithering configuration or a decorrelating configuration (or both) can be employed to reduce the noise correlation without significantly degrading the signal to noise ratio. For a more detailed discussion of a dithering configuration, see United States Patent Application entitled “Methods and Apparatus for Whitening Quantization Noise in a Delta-Sigma Modulator Using Dither Signal,” filed contemporaneously herewith and incorporated by reference herein.
Typically, the one bit quantization performed by the quantizer 210 would require a high oversampling ratio. For example, audio encoding techniques that employ one bit quantization of audio signals that are on the order of 100 KHz typically oversample the audio signal at a rate of 20 MHz. Such oversampling is not practical in the wireless communication context of the present invention, where the signals are typically on the order of multiple GHz. The desired low oversampling rates of the present invention, however, would typically lead to an unstable encoder. As discussed hereinafter, aspects of the present invention provide techniques for providing a stable encoder based on one bit quantization.
According to one aspect of the invention, well-known decorrelating techniques are employed to reduce noise correlation to the quantizer 110 of the exemplary delta-sigma modulator 100 by reducing the correlation between the quantization error signal, e, and the input, r. As discussed hereinafter, a leakage path 210 is added to the conventional delta-sigma modulator 100 of
As shown in
βk=βk−1−μ·ek·uk (1)
where is μ is the LMS step size.
In a further variation, a more stable implementation of tap adaptation can employ tap leakage:
βk=(1−η)·βk−1−μ·ek·uk (2)
where η is a leakage coefficient and μ is the step size.
In yet another variation, generally for faster convergence, a variable step size, μ can be employed:
βk=(1−η)·βk−1−(μ·ek4)·ek·uk (3)
Generally, equation (3) links the step size with the quantization error, e, whereby the step size is reduced as the error decreases. It is noted that the step size, μ, in equation (2) is replaced by μ·ek4 in equation (3). Thus, if the loop becomes unstable, e increases rapidly (clipped quantizer state) and μ increases quadratically with e, accelerating convergence speed of β.
While exemplary embodiments of the present invention have been described with respect to digital logic blocks, as would be apparent to one skilled in the art, various unctions may be implemented in the digital domain as processing steps in a software program, in hardware by circuit elements or state machines, or in combination of both software and hardware. Such software may be employed in, for example, a digital signal processor, application specific integrated circuit or micro-controller. Such hardware and software may be embodied within circuits implemented within an integrated circuit.
Thus, the functions of the present invention can be embodied in the form of methods and apparatuses for practicing those methods. One or more aspects of the present invention can be embodied in the form of program code, for example, whether stored in a storage medium, loaded into and/or executed by a machine, wherein, when the program code is loaded into and executed by a machine, such as a processor, the machine becomes an apparatus for practicing the invention. When implemented on a general-purpose processor, the program code segments combine with the processor to provide a device that operates analogously to specific logic circuits. The invention can also be implemented in one or more of an integrated circuit, a digital signal processor, a microprocessor, and a micro-controller.
It is to be understood that the embodiments and variations shown and described herein are merely illustrative of the principles of this invention and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the invention.
