Patent Application
20090168936
The present invention is related to techniques for clock and data recovery in a communication system and, more particularly, to techniques for detecting a loss of lock condition in a clock and data recovery system.
Digital communication receivers typically must sample an incoming waveform and then reliably detect the sampled data. Typically, a receiver includes a Clock and Data Recovery (CDR) system to recover the clock and data from an incoming data stream. The CDR system generates a clock signal having the same frequency and varying phase as the incoming signal, which is then used to sample the received signal and detect the transmitted data.
CDR systems often employ well-known multiple stage proportional-integral (PI) digital loop filters, typically having multiple integrators in series. In a second order filter, for example, the first integrator includes a proportional register (PREG), and the second integrator includes an integral register (IREG), in a known manner. The CDR system recovers or locks to an initially unknown phase offset and frequency offset present in the incoming signal The integral state of the loop is directly related to the frequency offset The integral register is typically initialized to a value of zero (0) and the integral register value will eventually converge to a value that is proportional to the frequency of offset.
When a CDR is in a locked state, the sampling latches see a time stationary NRZ signal As a result, the Decision Feedback Equalization (DFE) eye opening can be calculated by comparing (for example, using an exclusive-or operation (XOR)) the decision latch output with the output of a vertical roaming latch, constrained with N-previous bits. See, fox example, U.S. patent application Ser. No. 11/540,946, filed Sep. 29, 2006, entitled “Method And Apparatus For Determining Latch Position For Decision-Feedback Equalization Using Single-Sided Eye,” for a discussion of DFE eyes. If the CDR loses the locked state, however, the NRZ signal is not time stationary. The CDR will start to diverge from the sampling clocks. When a CDR is out of lock, the CDR loop may build up the wrong values for the integral and proportional registers (IREG and PREG) Conventional techniques have used integral register (IREG) or proportional register (PREG) variability as an indication of CDR loss detection. Such conventional techniques, however, may confuse integral or proportional register variability with actual parts-pet-million (ppm) deviation
A need exists for methods and apparatus for detecting a loss of lock condition in a clock and data recovery system A further need exists for methods and apparatus that take corrective action to restore a locked condition in a clock and data recovery system.
Generally, methods and apparatus are provided for detecting a loss of lock condition in a clock and data recovery system. According to one aspect of the invention, a loss of lock condition is detected in a clock and data recovery system that generates a recovered clock signal from a received signal by sampling the received signal for a plurality of different phases using one or more latches clocked by the recovered clock; evaluating the samples to monitor a data eye associated with the received signal; and detecting the loss of lock condition if the data eye does not satisfy one or more predefined conditions
For example, the one or more predefined conditions can ensure that the recovered clock phase has a deterministic sampling phase on a unit interval (UI) of the received signal when the clock and data recovery system is in a locked condition Thus, the one or more predefined conditions detect when the recovered clock phase has a non-deterministic sampling phase on a unit interval (UI) of the received signal due to a loss of lock condition. More generally, the one or more predefined conditions identify a loss of the data eye (e g, when the data eye cannot be substantially detected), for example, based on a degree of opening of the data eye. The clock and data recovery system can optionally be restarted if the loss of lock condition is detected.
A mole complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings.
The present invention provides methods and apparatus for detecting a loss of lock condition in a clock and data recovery system.
As previously indicated, a received, such as the receiver 130, typically includes a Clock and Data Recovery (CDR) system 138 to recover the clock and data from the incoming data stream (received signal) The CDR system 138 generates a clock signal having the same frequency and varying phase as the received signal, which is then used to sample the received signal and detect the transmitted data. In this situation, the recovered clock at the output of the CDR 138 and the received data at the input of the CDR 138 will be synchronized with each other. As a result, the recovered clock phase will maintain a deterministic sampling phase on a unit interval (UI) of the incoming data.
A CDR, such as the CDR 138, can lose lock for various reasons, e.g., (1) in the presence of spectrally poor incoming data, or (2) in a threshold-based phase detector, where the phase detector (PD) threshold is raised above the signal. When a CDR loses lock, the recovered clock frequency will not have the same frequency as the incoming data. As a result, the recovered clock phase will not be deterministic over a UI of the incoming data.
According to one aspect of the invention, the receiver 130 includes a loss of lock detector 160, to automatically determine if the CDR 138 loses the locked condition. As shown in
A small data eye is typically the result of channel distortions that tend to close the data eye. Generally, a DFE eye, also referred to as a single-sided eye, provides an improved mechanism for monitoring the data eye by containing only transitions from one binary value (i e, only 1→x or 0→x transitions). The DEE eye techniques recognize that a DFE eye can be more easily observed by constraining the data to only contain signal transitions from, for example, a binary value 1 to a binary value of 0 or 1 (referred to as 1→x), and inhibiting any signal transitions from a binary value of 0.
As previously indicated, if a CDR loses a locked state, the NRZ signal is not time stationary and the recovered clock will start to diverge from the UI sampling phase from one sample to the next sample. The time varying unrecovered clock will sample the UI of the incoming data at different phases on the data UI. Since the unrecovered clock and input data phase are no longer stationary, the statistics from the data eye monitor that were designed to be collected at a given phase, will rather be collected for a walking phase The data eye monitor thus provides average eye data across every phase The present invention thus recognizes that the DEE eye will cease to exist when there is a loss of lock. A loss of DFE eye can be detected, for example, when the eye opening fails to meet one or more predefined criteria, such as a minimum height or a minimum width The present invention further recognizes that the DFE eye information can be used to detect a loss of lock in a clock and data recovery system If a loss of lock is detected, another aspect of the invention restarts the CDR to restore proper operation
As the signal amplitude degrades and an un-equalized signal reaches the CDR sampling latches, the CDR operation becomes challenging. Fox a small amplitude signal, the DFE eye 300 is small, as shown in
As part of the equalization process, the loss of lock detector 160 calculates the height of the DFE eye, such as the height 210 of the DFE eye 200 of
While exemplary embodiments of the present invention have been described with respect to digital logic blocks, as would be apparent to one skilled in the art, various functions may be implemented in the digital domain as processing steps in a software program, in hardware by circuit elements or state machines, or in combination of both software and hardware. Such software may be employed in, for example, a digital signal processor, micro-controller, or general-purpose computer. Such hardware and software may be embodied within circuits implemented within an integrated circuit.
Thus, the functions of the present invention can be embodied in the form of methods and apparatuses fox practicing those methods. One or mote aspects of the present invention can be embodied in the form of program code, for example, whether stored in a storage medium, loaded into and/or executed by a machine, or transmitted over some transmission medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention When implemented on a general-purpose processor; the program code segments combine with the processor to provide a device that operates analogously to specific logic circuits.
It is to be understood that the embodiments and variations shown and described herein are merely illustrative of the principles of this invention and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the invention
