Methods and apparatus for dynamically reconfiguring a charge pump during output transients

Abstract

Methods and apparatus are described for dynamically controlling a charge pump system including a plurality of charge pump stages, with each charge pump stage coupled between an input voltage VIN at an input voltage node and an output voltage VOUT at an output voltage node. In particular, the configuration of the charge pump stages may be dynamically controlled during a transition on VOUT from a first voltage to a second voltage to improve the circuit's transient response.

Description

BACKGROUND

Many integrated circuits require multiple power supply voltage levels for normal device operation. For example, an integrated circuit may contain certain types of semiconductor memories that require a “write voltage” of about 8 volts, yet other operations of the memory circuits, including “read” operations, require a voltage of only about 3 volts. In the past, two different power supplies often would be used to operate such a device. Today, however, such integrated circuits typically require only a single power supply voltage, and include on-chip circuitry to generate a “boosted” voltage having a magnitude greater than the power supply voltage. For example, many modern integrated circuits use a single power supply voltage V_DD of about 2.5-3.3 volts to power most of the device, including the normal read operation circuits, and also include an on-chip voltage generator that provides a boosted voltage V_PP of about 8 volts for write operations. Such on-chip voltage generators are often implemented as capacitive voltage multiplier circuits commonly called “charge pumps.”

Referring now to FIG. 1, an exemplary previously known multi-stage charge pump is described. Charge pump 10 includes charge pump stages 12a-12d coupled in series between input voltage V_IN and output voltage V_OUT. Charge pump stages 12a-12d each include a charge transfer device, such as diodes 14a-14d, respectively, and a pump capacitor, such as capacitors C_A-C_D, respectively. A complementary pair of non-overlapping clock signals CLK and {overscore (CLK)} are provided to drive the various pump capacitors. In particular, charge pump stages 12a and 12c are driven by the CLK signal, whereas pump stages 12b and 12d are driven by the CLK signal. Isolation diode 16 couples the output of the final charge pump stage 12d to output node V_OUT, which is shown with a capacitive load C_LOAD coupled to GROUND. If clock signals CLK and CLK are driven by signals that swing between a high level of V_IN and a low level of GROUND, charge pump circuit 10 generates an output voltage V_OUT that is boosted above V_IN. The price paid for achieving an increased output voltage, however, is higher input current requirements.

For some circuit applications, such as in memory devices, the transient response of the charge pump is one of the factors that limit how fast the memory can be read or written. To provide faster read and write times, therefore, it often is desirable to reduce the charge pump's transient response time. The transient response time of charge pump 10 may be reduced by increasing output current I_OUT. As mentioned above, however, increasing the output current further increases input current I_IN. For some circuit applications, input current is limited, which thus limits the amount by which the charge pump's output current can be increased to improve the circuit's transient response.

One previously known technique for overcoming this limitation is to taper the capacitors used in each charge pump stage. That is, referring again to FIG. 1, the size of pump capacitors C_A-C_D may be tapered so that C_A>C_B>C_C>C_D. In steady-state, however, the current in stages 12a-12d are equal, and are limited by the current-capacity of the smallest stage. Thus, if C_D=C, the steady-state output current of charge pump 10 with tapered pump capacitors is approximately equal to the circuit with non-tapered capacitors. Therefore, although increasing the size of pump capacitor C_A helps improve the transient response of charge pump 10, this large capacitor does not add any additional steady-state current capacity, and merely consumes a large amount of area on the integrated circuit.

In view of the foregoing, it would be desirable to provide methods and apparatus that improve the transient response of a charge pump circuit without increasing capacitor size.

It further would be desirable to provide methods and apparatus that improve the transient response of a charge pump circuit without exceeding input current limits.

SUMMARY

Methods and apparatus in accordance with this invention control a charge pump system comprising a plurality of charge pump stages, with each charge pump stage coupled between an input voltage V_IN at an input voltage node and an output voltage V_OUT at an output voltage node. In one exemplary embodiment, the configuration of the charge pump circuits are changed during a transition on V_OUT from a first voltage to a second voltage to improve the circuit's transient response.

In particular, the number of charge pump stages coupled to the input voltage node and the output voltage node may be dynamically changed during the transition on V_OUT from the first voltage to the second voltage. A first plurality of charge pump stages may be coupled to the input voltage node and the output voltage node to increase V_OUT to a first intermediate voltage between the first and second voltages, and then a second plurality of charge pump stages may be coupled to the input voltage node and the output voltage node to increase V_OUT to a second intermediate voltage between the first and second voltages. Alternatively, a first plurality of charge pump stages may be coupled to the input voltage node and the output voltage node to increase V_OUT to a first intermediate voltage between the first and second voltages, and then a second plurality of charge pump stages may be coupled to the input voltage node and the output voltage node to increase V_OUT to the second voltage.

In an alternative exemplary embodiment, the frequency of the clock signals supplied to the charge pump stages may be dynamically changed during the transition on V_OUT from the first voltage to the second voltage. In particular, clock signals at a first frequency are provided to the charge pump stages to increase V_OUT to a first intermediate voltage between the first and second voltages, and then clock signals at a second frequency may be provided to the charge pump stages to increase V_OUT to a second intermediate voltage between the first and second voltages.

In another exemplary embodiment, the pump capacitor values in the charge pump stages may be dynamically changed during the transition on V_OUT from the first voltage to the second voltage. In particular, a first plurality of charge pump stages having a first set of pump capacitor values may be coupled to the input voltage node and the output voltage node to increase V_OUT to a first intermediate voltage between the first and second voltages, and then a second plurality of charge pump stages having a second set of pump capacitor values may be coupled to the input voltage node and the output voltage node to increase V_OUT to the second voltage. The first or second set of pump capacitor values may be tapered values.

BRIEF DESCRIPTION OF THE DRAWINGS

The above-mentioned objects and features of the present invention can be more clearly understood from the following detailed description considered in conjunction with the following drawings, in which the same reference numerals denote the same elements throughout, and in which:

FIG. 1 is a diagram of a previously known charge pump;

FIG. 2 is a diagram of an exemplary dynamically reconfigurable charge pump in accordance with this invention;

FIG. 3 is a diagram of exemplary output current versus output voltage response curves for various exemplary charge pump configurations;

FIG. 4A is a diagram of an exemplary configuration of the circuit of FIG. 2 during a first exemplary time interval;

FIG. 4B is a diagram of an exemplary configuration of the circuit of FIG. 2 during a second exemplary time interval;

FIG. 4C is a diagram of an exemplary configuration of the circuit of FIG. 2 during a third exemplary time interval;

FIG. 4D is a diagram of an exemplary configuration of the circuit of FIG. 2 during a fourth exemplary time interval; and

FIG. 5 is a diagram of an exemplary control system for use with dynamically reconfigurable charge pumps in accordance with this invention.

DETAILED DESCRIPTION

Referring again to FIG. 1, if pump capacitors C_A-C_D all have the same value C, if second-order effects are ignored, and assuming ideal diodes having a threshold voltage of 0V, the output voltage and output current of charge pump 10 may be expressed as: V_OUT(t)=(n+1)V_IN−n(ΔV(t))  (1) I_OUT(t)=C(ΔV(t))f_clk  (2) where n is the number of series-coupled charge pump stages 12a-12d, ΔV(t) is the voltage change per charge pump stage 12a-12d, and f_clk is the clock frequency of clock signals CLK and {overscore (CLK)}.

The price paid for achieving an increased output voltage, however, is higher input current requirements. In particular, if second-order effects are ignored, the input current of charge pump 10 may be expressed as: I_IN(t)=(n+1)I_OUT(t)  (3)

The transient response time of charge pump 10 may be reduced by increasing output current I_OUT. As indicated by equation (3), however, each 1-unit increase in output current I_OUT requires an (n+1)-unit increase in input current I_IN. For some circuit applications, input current is limited, which thus limits the amount by which the charge pump's output current can be increased to improve the circuit's transient response.

One previously known technique for overcoming this limitation is to taper the capacitors used in each charge pump stage. That is, referring again to FIG. 1, the size of pump capacitors C_A-C_D may be tapered so that C_A>C_B>C_C>C_D. In steady-state, however, the current in stages 12a-12d are equal, and are limited by the current-capacity of the smallest stage: I_OUT(t)=C_DΔV(t)f_clk  (4)

Thus, if C_D=C, the steady-state output current of charge pump 10 with tapered pump capacitors is approximately equal to the circuit with non-tapered capacitors. Therefore, although increasing the size of pump capacitor C_A helps improve the transient response of charge pump 10, this large capacitor does not add any additional steady-state current capacity, and merely consumes a large amount of area on the integrated circuit.

Methods and apparatus in accordance with this invention change the configuration of the charge pump during a transition on V_OUT from a first voltage to a second voltage to improve the circuit's transient response. Referring now to FIG. 2, an exemplary dynamically configurable charge pump in accordance with this invention is described. In particular, charge pump 20 includes k charge pump stages 12₁, 12₂, . . . , 12_k, and clock generator 22. Each charge pump stage 12₁, 12₂, . . . , 12_k is coupled to input node V_IN via a corresponding input switch Si₁, Si₂, . . . , Si_k, respectively, and to output node V_OUT via a corresponding output switch So₁, So₂, . . . , So_k, respectively. Further, each of charge pump stages 12₂, 12₃, . . . , 12_k is coupled to the immediately preceding stage by a corresponding coupling switch Sc₁, Sc₂, . . . , Sc_k, respectively. Although not shown in FIG. 2, each charge pump stage 12₁, 12₂, . . . , 12_k includes corresponding pump capacitor C₁, C₂, . . . , C_k, respectively. Clock generator 22 generates non-overlapping clock signals CLK and {overscore (CLK)} at a frequency f_clk0, and that are alternately applied to charge pump stage 12₁, 12₂, . . . , 12_k.

Input switches Si₁, Si₂, . . . , Si_k, output switches So₁, So₂, . . . , So_k, and coupling switches Sc₁, Sc₂, . . . , Sc_k may be used to modify the configuration of charge pump stages 12₁, 12₂, . . . , 12_k. For example, if input switches Si₁, Si₂, . . . , Si_k are all CLOSED, output switches So₁, So₂, . . . , So_k are all CLOSED and coupling switches Sc₁, Sc₂, . . . , Sc_k are all OPEN, charge pump stages 12₁, 12₂, . . . , 12_k are all coupled in parallel between input node V_IN and output node V_OUT. Alternatively, if input switch Si₁, coupling switches Sc₂, Sc₃, . . . , Sc_k, and output switch So_k are all CLOSED, and all other switches are OPEN, charge pump stages 12₁, 12₂, . . . , 12_k are all coupled in series between input node V_IN and output node V_OUT.

Further, input switches Si₁, Si₂, . . . , Si_k, output switches So₁, So₂, . . . , So_k, and coupling switches Sc₁, Sc₂, . . . , Sc_k may be independently programmed to couple any number of charge pump stages 12₁, 12₂, . . . , 12_k in series or parallel. Thus, if switches Si₁, Sc₂ and So₂ are CLOSED, and all other switches are OPEN, charge pump stages 12₁ and 12₂ are coupled in series between input node V_IN and output node V_OUT, and all other charge pump stages 12₃, . . . , 12_k are disconnected. Alternatively, if switches Si₁, Si₂, Si₃, So₁, So₂ and So₃ are OPEN, and all other switches are closed, charge pump stages 12₁, 12₂ and 12₃ are coupled in parallel between input node V_IN and output node V_OUT, and all other charge pump stages 12₄, . . . , 12_k are disconnected.

As used herein, i charge pump stages 12₁, 12₂, . . . , 12_i coupled in series are referred to as an ith-order charge pump, with n=i. Thus, a first-order charge pump includes a single charge pump stage 12₁, with n=1. In contrast, a fourth-order charge pump includes four series-coupled charge pump stages 12₁, 12₂, 12₃, 12₄, with n=4.

In accordance with an embodiment of this invention, input switches Si₁, Si₂, . . . , Si_k, output switches So₁, So₂, . . . , So_k, and coupling switches Sc₁, Sc₂, . . . , Sc_k may be dynamically controlled to change the configuration of charge pump stages 12₁, 12₂, . . . and 12_k during a transition on V_OUT to improve the transient response of charge pump 20. In general, during a transition on V_OUT from a first voltage V_A to a second voltage V_B, the series/parallel configuration of m charge pump stages 12₁, 12₂, . . . , 12_m may be dynamically reconfigured as follows:

TABLE 1
Time	Configuration	n	ΔVOUT
0 ≦ t < t1	m first-order charge pumps	1	VA to V1
	coupled in parallel
t1 ≦ t < t2	m/2 second-order charge pumps	2	V1 to V2
	coupled in parallel
t2 ≦ t < t3	m/3 third-order charge pumps	3	V2 to V3
	coupled in parallel
t3 ≦ t < t4	m/4 fourth-order charge pumps	4	V3 to V4
	coupled in parallel
. . .	. . .	. . .	. . .
tj−1 ≦ t < tj	1 mth-order charge pump	m	Vj−1 to VB

That is, during a first time interval 0≦t<t₁, m first-order charge pumps may be coupled in parallel to increase V_OUT from V_A to V₁; during a second time interval t₁≦t<t₂, m/2 second-order charge pumps may be coupled in parallel to increase V_OUT from V₁ to V₂; during a third time interval t₂≦t<t₃, m/3 third-order charge pumps may be coupled in parallel to increase V_OUT from V₂ to V₃, and so on until during a jth time interval t_j-1≦t<t_j, a single mth-order charge pump may be used to increase V_OUT from V_j-1 to V_B. Persons of ordinary skill in the art will understand that the number m of charge pump stages and the number j of time intervals may be the same, or may be different.

In contrast to previously known techniques that use a single mth-order charge pump to increase V_OUT from V_A to V_B, methods and apparatus in accordance with this embodiment of the invention dynamically reconfigure charge pump 20 from lower-order configurations to higher-order configurations during a transition on V_OUT. In this regard, during the initial period of the voltage transient, multiple lower-order charge pumps are coupled in parallel to boost the output current, while maintaining relatively modest input current requirements.

Various techniques may be used to determine when and how charge pump 20 should be reconfigured. For example, charge pump 20 may be dynamically reconfigured to maximize output current I_OUT. In particular, FIG. 3 illustrates exemplary output current I_OUT versus output voltage V_OUT response curves 24a-24d for ith-order, jth-order, kth-order and lth-order charge pump configurations, respectively, where i<j<k<1. As the diagram illustrates, for V_OUT less than Vx₁, the ith-order charge pump provides the maximum output current I_OUT. For Vx₁<V_OUT≦Vx₂, the jth-order charge pump provides the maximum output current I_OUT. For Vx₂≦V_OUT<Vx₃, the kth-order charge pump provides the maximum output current I_OUT. And for V_OUT≧Vx₃, the lth-order charge pump provides the maximum output current I_OUT. Thus, to maximize output current during a transition on V_OUT, charge pump 20 may be switched from a lower-order configuration to a higher-order configuration when the higher-order configuration provides greater output current I_OUT. The value of V_OUT at which the circuit reconfiguration occurs is referred to herein as the “crossover voltage.”

Thus, from Table 1, above, charge pump 20 may be switched from the first-order configuration to the second-order configuration at crossover voltage V₁, at which point the output current I_OUT of the second-order configuration exceeds the output current of the first-order configuration. Similarly, charge pump 20 may be switched from the second-order configuration to the third-order configuration when V_OUT reaches crossover voltage V₂, at which point the output current I_OUT of the third-order configuration exceeds the output current of the second-order configuration. Because the dynamically reconfigured charge pump 20 maintains high output current I_OUT, the circuit can achieve a shorter transient response time than a comparable previously known static charge pump.

Persons of ordinary skill in the art will understand that all configurations need not be used. For example, if m=8, the first-order configuration may be used until V_OUT reaches a first crossover voltage, the second-order configuration may be used until V_OUT reaches a second crossover voltage, the fourth-order configuration may be used until V_OUT reaches a third crossover voltage, and the eighth-order configuration may be used until V_OUT reaches the final desired output voltage.

The crossover voltage at which m/b, bth-order charge pump stages provide greater output current I_OUT than m/a, ath-order charge pump stages (b>a) may be determined using the following equation: $\begin{array}{cc}{V}_{\mathrm{xover}}=V_{\mathrm{IN}}\left[\frac{R_b\left(n_a+1\right)-R_a\left(n_b+1\right)}{R_b-R_a}\right]& \left(5\right)\end{array}$ where V_IN is the input voltage to charge pump 20, n_a is the number of charge pump stages n for the ath-order configuration, n_b is the number of charge pump stages n for the bth-order configuration, and R_a and R_b are given by: $\begin{array}{cc}{R}_x=\frac{n_x}{\left(\frac{m}{x}\right)\times C_x\times f_{{\mathrm{clk}}_x}}& \left(6\right)\end{array}$ where C_x is the pump capacitor and f_clkx is the clock frequency of clock signals CLK and {overscore (CLK)} of the xth-order configuration.

If second-order effects are ignored, and assuming ideal diodes having a threshold voltage of zero volts, the output voltage V_OUT(t) of an ath-order configuration is given by: $\begin{array}{cc}{V}_{\mathrm{OUT}}\left(t\right)=\left(n_a+1\right)V_{\mathrm{IN}}\left(1-e^{-\frac{t}{\tau }}\right)\left(\frac{R_{\mathrm{LOAD}}}{R_a+R_{\mathrm{LOAD}}}\right)+V_{\mathrm{INIT}}{e}^{-\frac{t}{\tau }}& \left(7\right)\end{array}$ where V_INIT is the initial value of V_OUT, R_LOAD is the load resistance at node V_OUT, and τ is a time constant given by: $\begin{array}{cc}\tau =R_a{C}_{\mathrm{LOAD}}\left(\frac{R_{\mathrm{LOAD}}}{R_a+R_{\mathrm{LOAD}}}\right)& \left(8\right)\end{array}$ Thus, the time required for an ath-order configuration to increase V_OUT from a first voltage V_a1 to a second voltage V_a2 is given by: $\begin{array}{cc}{T}_{\mathrm{Va}1-\mathrm{Va}2}={\mathrm{RC}}_{\mathrm{LOAD}}\left(\frac{R_{\mathrm{LOAD}}}{R_a+R_{\mathrm{LOAD}}}\right)\ln \left[\frac{\left(n_a+1\right)V_{\mathrm{IN}}-V_{a1}\left(\frac{R_a+R_{\mathrm{LOAD}}}{R_{\mathrm{LOAD}}}\right)}{\left(n_a+1\right)V_{\mathrm{IN}}-V_{a2}\left(\frac{\mathrm{Ra}+R_{\mathrm{LOAD}}}{R_{\mathrm{LOAD}}}\right)}\right]& \left(9\right)\end{array}$ where C_LOAD is the load capacitance at node V_OUT.

To illustrate these techniques, an exemplary operation of charge pump 20 is described, under the following conditions:

	TABLE 2
	Parameter	Value
	VIN	3	V
	VOUT	15	V
	C1 = C2 = . . . = Cn = C	1	pF
	fclk	2	GHz
	ROUT	50	kΩ
	COUT	10	nF

First, the number of required charge pump stages m may be determined from the following formula: $\begin{array}{cc}m=\left[\frac{\left(V_{\mathrm{OUT}}-V_{\mathrm{IN}}\right)}{V_{\mathrm{IN}}-\left(\frac{V_{\mathrm{OUT}}}{R_{\mathrm{LOAD}}{C}_{\mathrm{stage}}{f}_{\mathrm{clk}}}\right)}\right]& \left(10\right)\end{array}$ Where C_stage is the value of pump capacitor C. Solving equation (10) using the values in Table 2, we determine that m=8 charge pump stages 12₁, 12₂, . . . , 12₈ are required to generate an output voltage V_OUT=15V from an input voltage V_IN=3V.

The m charge pump stages may be dynamically configured in any one of multiple ways. For example, charge pump stages 12₁, 12₂, . . . , 12₈ may be dynamically configured using first-order, second-order, fourth-order and eighth-order configurations. From equations (5) and (6), above, the crossover voltages for each of these configurations are:

	TABLE 3
	Configuration	n	Vxover (volts)
	first-order	1	5
	second-order	2	7
	fourth-order	4	11
	eighth-order	8	15

Referring now to Table 3 and FIG. 4, an exemplary technique for dynamically reconfiguring charge pump 20 is described. In particular, as illustrated in FIG. 4A, assuming that V_OUT has an initial value of 3V, during a first time interval T₁, 8 first-order charge pumps are coupled in parallel to increase V_OUT from 3 to 5V. Next, as illustrated in FIG. 4B, during a second time interval T₂, 4 second-order charge pumps are coupled in parallel to increase V_OUT from 5 to 7V. Next, as illustrated in FIG. 4C, during a third time interval T₃, 2 fourth-order charge pumps are coupled in parallel to increase V_OUT from 7 to 11V. Finally, as illustrated in FIG. 4D, during a fourth time interval T₄, 1 eighth-order charge pump is used to increase V_OUT from 11 to 15V. From equation (9), above, the four time intervals may be determined to be: T₁=0.69 μsec, T₂=1.75 μsec, T₃=7.18 μsec and T₄=12.46 μsec, for a total transient response time of approximately 22.08 μsec. In contrast, if a single eighth-order charge pump were used to increase V_OUT from 3V to 15V, the corresponding transient response time would be approximately 29.20 μsec, or approximately 32% longer than the exemplary dynamically-reconfigured charge pump.

Persons of ordinary skill in the art will understand that other techniques may be used to determine when and how charge pump 20 should be reconfigured. For example, charge pump 20 may be dynamically reconfigured to increase output current I_OUT, while simultaneously limiting input current requirements. Thus, in the example described above for m=8, to meet input current limits, charge pump 20 may be configured using six, first-order charge pumps during a first time interval, four, second-order charge pumps during a second time interval, two, third-order charge pumps for a third time interval, and so on. Alternatively, if m=6, charge pump 20 may be configured using 1 third-order charge pump during a first time interval, and 1 sixth-order charge pump during a second time interval. This latter technique may be used to avoid a high input current demand during the first time interval.

In addition, persons of ordinary skill in the art will understand that other techniques may be used to dynamically reconfigure charge pump circuit 20 during a transition on V_OUT. In particular, referring again to FIG. 2, if clock generator 22 has a variable clock frequency f_clk, the clock frequency may be modified along with the configuration of charge pump stages 12₁, 12₂, . . . , 12_k to improve the transient response of charge pump circuit 20. For example, if the output current of each charge pump stage 12₁, 12₂, . . . , 12_k is I_OUT0 for f_clk=2 GHZ, from equation (2), above, if f_clk is increased to p×f_clk, then output current I_OUT=p×I_OUT0.

Thus, using the values from Table 2, above, with m=8, to increase V_OUT from 3 to 15V, charge pump 20 may be dynamically modified during the transient interval as follows: During a first during a first time interval T₁′, a single charge pump stage 12₁ may be clocked at 8×f_clk to increase V_OUT from 3 to 5V. During a second interval T₂′, a single second-order charge pump may be clocked at 4×f_clk to increase V_OUT from 5 to 7V. During a third interval T₃′, a single fourth-order charge pump may be clocked at 2×f_clk to increase V_OUT from 7 to 11V. Finally, during a fourth interval T₃′, a single eighth-order charge pump may be clocked at f_clk to increase V_OUT from 11 to 15V.

Persons of ordinary skill in the art will also understand that still other techniques may be used to dynamically reconfigure charge pump circuit 20 during a transition on V_OUT. For example, referring again to FIG. 2, if charge pump stages 12₁, 12₂, . . . , 12_k each include an array of switchable unit pump capacitors C, the size of pump capacitors C₁, C₂, C₃, . . . , C_k may be dynamically modified along with the configuration of the charge pump stages to improve the transient response of charge pump circuit 20. For example, with m=4, during a first time interval T₁″, a fourth-order charge pump may be configured with C₁=8 units, C₂=4 units, C₂=2 units and C₄=1 unit to increase V_OUT from a first voltage to an intermediate voltage. During a second time interval, T₂″, the fourth-order charge pump may be configured with C₁=1 unit, C₂=1 unit, C₂₌₁ units and C₄=1 unit to increase V_OUT from the intermediate voltage to a second voltage. In this regard, charge pump circuit 20 may be a dynamically-taperable charge pump.

Persons of ordinary skill in the art will understand that various techniques may be used to control the reconfiguration of charge pump circuit 20. For example, as illustrated in FIGS. 2 and 5, charge pump circuit 20 may include a multi-bit input signal node SWITCH that may be used to control input switches Si₁, Si₂, . . . , Si_k, output switches So₁, So₂, . . . , So_k, and coupling switches Sc₁, Sc₂, . . . , Sc_k. Additionally, clock generator 22 may include a multi-bit input signal node FREQ that may be used to control the frequency of clock signals CLK and {overscore (CLK)}. A control circuit 26 may be coupled to input signal V_IN, output signal V_OUT and a control signal V_DES, and may be used to generate control signals FREQ and/or SWITCH for controlling the output voltage and/or output current of charge pump circuit 20. V_DES may be a control signal that specifies a desired output voltage V_OUT. For example, V_DES may have a first value corresponding to a memory READ mode (e.g., V_OUT=4 V), and a second value that corresponds to a memory WRITE mode (e.g., V_OUT=8V). Control circuit 26 may include any well-known control circuitry that may provide closed-loop and/or open-loop control of charge pump circuit 20 and/or clock generator 22.

For example, control circuit 26 may provide closed-loop feedback control. In particular, if V_OUT is at a first voltage V_A, and control signal V_DES specifies that the output voltage should be a second voltage V_B, control circuit 26 may sense the output voltage (or current), and generate control signals FREQ and/or SWITCH to reconfigure charge pump 20 during the transition on V_OUT. Alternatively, control circuit 26 may provide open-loop control. In particular, during a transition on V_OUT from a first voltage V_A to a second voltage V_B, control circuit 26 may generate control signals FREQ and/or SWITCH to configure charge pump 20 in a first configuration for a first predetermined time period, a second configuration for a second predetermined time period, a third configuration for a third predetermined time period, and so on. This control technique may be useful at startup to reduce initial current spikes. In addition, control circuit 26 may sense the voltage (or current) at input node V_IN, compare the sensed voltage (or current) to a reference voltage (or current), and generate control signals FREQ and/or SWITCH to reconfigure charge pump 20 based on the deviation between the sensed value and the reference value. Persons of ordinary skill in the art will understand that this technique may be combined with other control techniques.

The foregoing merely illustrates the principles of this invention, and various modifications can be made by persons of ordinary skill in the art without departing from the scope and spirit of this invention.

Claims

1. A method for controlling a charge pump system comprising a plurality of charge pump stages, each charge pump stage coupled between an input voltage VIN at an input voltage node and an output voltage VOUT at an output voltage node, the method comprising: changing a configuration of the charge pump stages during a transition on VOUT from a first voltage to a second voltage.

2. The method of claim 1, wherein changing the configuration comprises coupling one of the charge pump stages to the input voltage node and the output voltage node to increase VOUT to a first intermediate voltage between the first and second voltages.

3. The method of claim 1, wherein changing the configuration comprises coupling a first plurality of the charge pump stages to the input voltage node and the output voltage node to increase VOUT to a first intermediate voltage between the first and second voltages.

4. The method of claim 3, wherein changing the configuration further comprises coupling a second plurality of the charge pump stages to the input voltage node and the output voltage node to increase VOUT to a second intermediate voltage between the first and second voltages.

5. The method of claim 1, wherein changing the configuration comprises coupling one of the charge pump stages to the input voltage node and the output voltage node during a first time interval during the transition on VOUT from the first voltage to the second voltage.

6. The method of claim 1, wherein changing the configuration comprises coupling a first plurality of the charge pump stages to the input voltage node and the output voltage node during a first time interval during the transition on VOUT from the first voltage to the second voltage.

7. The method of claim 6, wherein changing the configuration further comprises coupling a second plurality of the charge pump stages to the input voltage node and the output voltage node during a second time interval during the transition on VOUT from the first voltage to the second voltage.

8. The method of claim 1, wherein changing the configuration comprises controlling a number of the charge pump stages coupled to the input voltage node and the output voltage node during the transition on VOUT from the first voltage to the second voltage.

9. The method of claim 1, wherein changing the configuration comprises controlling a frequency of a clock signal supplied to the charge pump stages during the transition on VOUT from the first voltage to the second voltage.

10. The method of claim 9, wherein controlling the clock frequency comprises providing a first clock signal at a first frequency to the charge pump stages to increase VOUT to a first intermediate voltage between the first and second voltages.

11. The method of claim 10, wherein controlling the clock frequency further comprises providing a second clock signal at a second frequency to the charge pump stages to increase VOUT to a second intermediate voltage between the first and second voltages.

12. The method of claim 9, wherein controlling the clock frequency comprises providing a first clock signal at a first frequency to the charge pump stages during a first time interval during the transition on VOUT from the first voltage to the second voltage.

13. The method of claim 9, wherein controlling the clock frequency further comprises providing a second clock signal at a second frequency to the charge pump stages during a second time interval during the transition on VOUT from the first voltage to the second voltage.

14. The method of claim 1, wherein: the charge pump system supplies an output current IOUT at the output voltage node; and changing the configuration maximizes the output current IOUT during a transition on VOUT from a first voltage to a second voltage.

15. The method of claim 1, wherein the charge pump system receives an input current IIN at the input node, and supplies an output current IOUT at the output voltage node; and changing the configuration limits input current IIN requirements.

16. The method of claim 1, wherein changing the configuration comprises: coupling a first plurality of the charge pump stages in series during a first time interval during the transition on VOUT from the first voltage to the second voltage; and coupling a second plurality of the charge pump stages in series during a second time interval during the transition on VOUT from the first voltage to the second voltage.

17. A charge pump system comprising a plurality of charge pump stages, each charge pump stage coupled between an input voltage VIN at an input voltage node and an output voltage VOUT at an output voltage node, the charge pump system comprising: means for dynamically controlling a configuration of the charge pump stages during a transition on VOUT from a first voltage to a second voltage.

18. The system of claim 17, wherein the means for dynamically controlling comprises means for coupling one of the charge pump stages to the input voltage node and the output voltage node to increase VOUT to a first intermediate voltage between the first and second voltages.

19. The system of claim 17, wherein the means for dynamically controlling comprises means for coupling a first plurality of the charge pump stages to the input voltage node and the output voltage node to increase VOUT to a first intermediate voltage between the first and second voltages.

20. The system of claim 19, wherein the means for dynamically controlling further comprises means for coupling a second plurality of the charge pump stages to the input voltage node and the output voltage node to increase VOUT to a second intermediate voltage between the first and second voltages.

21. The system of claim 17, wherein the means for dynamically controlling comprises means for coupling one of the charge pump stages to the input voltage node and the output voltage node during a first time interval during the transition on VOUT from the first voltage to the second voltage.

22. The system of claim 17, wherein the means for dynamically controlling comprises means for coupling a first plurality of the charge pump stages to the input voltage node and the output voltage node during a first time interval during the transition on VOUT from the first voltage to the second voltage.

23. The system of claim 22, wherein the means for dynamically controlling further comprises means for coupling a second plurality of the charge pump stages to the input voltage node and the output voltage node during a second time interval during the transition on VOUT from the first voltage to the second voltage.

24. The system of claim 17, wherein the means for dynamically controlling comprises means for controlling a number of the charge pump stages coupled to the input voltage node and the output voltage node during the transition on VOUT from the first voltage to the second voltage.

25. The system of claim 17, wherein the means for dynamically controlling comprises means for controlling a frequency of a clock signal supplied to the charge pump stages during the transition on VOUT from the first voltage to the second voltage.

26. The system of claim 25, wherein the means controlling the clock frequency comprises means for providing a first clock signal at a first frequency to the charge pump stages to increase VOUT to a first intermediate voltage between the first and second voltages.

27. The system of claim 25, wherein the means for controlling the clock frequency further comprises means for providing a second clock signal at a second frequency to the charge pump stages to increase VOUT to a second intermediate voltage between the first and second voltages.

28. The system of claim 25, wherein the means for controlling the clock frequency comprises means for providing a first clock signal at a first frequency to the charge pump stages during a first time interval during the transition on VOUT from the first voltage to the second voltage.

29. The system of claim 25, wherein the means for controlling the clock frequency further comprises means for providing a second clock signal at a second frequency to the charge pump stages during a second time interval during the transition on VOUT from the first voltage to the second voltage.

30. The system of claim 17, wherein: the charge pump system supplies an output current IOUT at the output voltage node; and the means for dynamically controlling maximizes the output current IOUT during a transition on VOUT from a first voltage to a second voltage.

31. The system of claim 17, wherein the charge pump system receives an input current IIN at the input node, and supplies an output current IOUT at the output voltage node; and the means for dynamically controlling limits input current IIN requirements.

32. The system of claim 17, wherein the means for changing the configuration comprises: means for coupling a first plurality of the charge pump stages in series during a first time interval during the transition on VOUT from the first voltage to the second voltage; and means for coupling a second plurality of the charge pump stages in series during a second time interval during the transition on VOUT from the first voltage to the second voltage.