Methods and apparatus for efficient vocoder implementations

Abstract

Techniques for implementing vocoders in parallel digital signal processors are described. A preferred approach is implemented in conjunction with the BOPS® Manifold Array (ManArray™) processing architecture so that in an array of N parallel processing elements, N channels of voice communication are processed in parallel. Techniques for forcing vocoder processing of one data-frame to take the same number of cycles are described. Improved throughput and lower clock rates can be achieved.

Description

FIELD OF THE INVENTION

[0002] The present invention relates generally to improvements in parallel processing. More particularly, the present invention addresses methods and apparatus for efficient implementation of vocoders in parallel DSPs. In a presently preferred embodiment, these techniques are employed in conjunction with the BOPS® Manifold Array (ManArray™) processing architecture.

BACKGROUND OF THE INVENTION

[0003] In the present world, the telephone is a ubiquitous way to communicate. Besides the original telephone configuration now there are cellular phones, satellite phones, and the like. In order to increase throughput of the telephone communication network, vocoders are typically used. A vocoder compresses the voice using some model for a voice producing mechanism. A compressed or encoded voice is transmitted over a communication system and needs to be decompressed or decoded on the other end. The nature of most voice communication applications requires the encoding and decoding of voice to be done in real time, which is usually performed by digital signal processors (DSPs) running a vocoder.

[0004] A family of vocoders, such as vocoders for use in connection with G.723, G.726/727, G.729 standards, as well as others, have been designed and standardized for telephone communication in accordance with the International Telecommunications Union (ITU) Recommendations. See, for example, R. Salami, C. Laflamme, B. Besette, and J-P. Adoul, ITU-T G.729Annex A: Reduced Complexity 8 kb/s CS-ACELP Codec for Digital Simultaneous Voice and Data, IEEE Communications Magazine, September 1997, pp. 56-63 which is incorporated by reference herein in its entirety. These vocoders process a continuous stream of digitized audio information by frames, where a frame typically contains 10 to 20 ms of audio samples. See, for example, the reference cited above, as well as, J. Du, G. Warner, E. Vallow, and T. Hollenbach, Using DSP16000 for GSM EFR Speech Coding, IEEE Signal Processing Magazine, March 2000, pp. 16-26 which is incorporated by reference in its entirety. These vocoders employ very sophisticated DSP algorithms involving computation of correlations, filters, polynomial roots and so on. A block diagram of a G.729a encoder 10 is shown in FIG. 1 as exemplary of the complexity and internal links between different parts of a typical prior art vocoder.

[0005] The G.729a vocoder is based on the code-excited linear-prediction (CELP) coding model described in the Salami et al. publication cited above. The encoder operates on speech frames of 10 ms corresponding to 80 samples at a sampling rate of 8000 samples per second. For every 10 ms frame, with a look-ahead of 5 ms, the speech signal is analyzed to extract the parameters of the CELP model such as linear-prediction filter coefficients, adaptive and fixed-codebook indices and gains. Then, the parameters, which take up only 80 bits compared to the original voice samples which take up 80*16 bits, are transmitted. At the decoder, these parameters are used to retrieve the excitation and synthesis filter parameters. The original speech is reconstructed by filtering this excitation through the short-term synthesis filter based on a 10th order linear prediction (LP) filter. A long-term, or pitch synthesis filter is implemented using the so-called adaptive-codebook approach. After computing the reconstructed speech, it is further enhanced by a post-filter.

[0006] A well known implementation of a G.729a vocoder, for example, takes on average about 50,000 cycles per channel per frame. See for example, S. Berger, Implement a Single Chip, Multichannel VoIP DSP Engine, Electronic Design, May 15, 2000, pp. 101-106. As a result, processing multiple voice channels at the same time, which is usually necessary at communication switches, requires great computational power. The traditional way to meet this requirement are by increasing the DSP clock frequency or the number of DSPs with multiple DSPs operating in parallel, each DSP has to be able to operate independently to handle conditional jumps, data dependency, and the like. As the DSB do not operate in synchronism, there is a high overhead for multiple clocks, control circuitry and the like. In both cases, increased power, higher manufacturing costs, and the like result.

[0007] It will be shown in the present invention that a high performance vocoder implementation can be designed for parallel DSPs such as BOPS® ManArray™ family with many advantages over the typical prior art approaches discussed above. Among its other advantages, the parallelization of vocoders using the BOPS® ManArray™ architecture results in an increase in the number of communication channels per DSP.

SUMMARY OF THE INVENTION

[0008] The ManArray™ DSP architecture as programmed herein provides a unique possibility to process the voice communication channels in parallel instead of in sequence. Details of the ManArray™ 2×2 architecture are shown in FIGS. 2 and 3, and are discussed further below. An important aspect of this architecture as utilized in the present invention is that it has multiple parallel processing elements (PEs) and one sequential processor (SP). Together, these processors operate as a single instruction multiple data (SIMD) parallel processor array. An instruction executed on the array performs the same function on each of the PEs. Processing elements can communicate with each other and with the SP through a cluster switch (CS). It is possible to distribute input data across the PEs, as well as exchange computed results between PEs or between PEs and the SP. Thus, individual PEs can either perform on different parts of input data to reduce the total execution time or on independent data sets.

[0009] Thus, if a DSP in accordance with this invention has N parallel PEs, it is capable of processing N channels of voice communication at a time in parallel. To achieve this end, according to one aspect of the present invention, the following steps have been taken:

[0010] the C code has been adapted to permit implementation of a function without using conditional jumps from one part of the function to another and/or conditional returns from a function

[0011] individual functions are implemented in a non-data dependent way so that they always take the same number of cycles regardless of what data are processed

[0012] control code to be run on the SP is separated from data processing code to be run on the PEs.

[0013] These and other advantages and aspects of the present invention will be apparent from the drawings and the Detailed Description including the Tables which follow below.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1 shows a block diagram of a prior art G.729a encoder;

[0015] FIG. 2 illustrates a simplified block diagram of a Manta™ 2×2 architecture in accordance with the present invention;

[0016] FIG. 3 illustrates further details of a 2×2 ManArray™ architecture suitable for use in accordance with the present invention;

[0017] FIG. 4 shows a block diagram of a prior art G.729a decoder;

[0018] FIG. 5 illustrates a processing element data memory set up in accordance with the present invention; and

[0019] FIG. 6 is a table comparing Manta 1×1 sequential processing and an iVLIW implementation.

DETAILED DESCRIPTION

[0020] Further details of a presently preferred ManArray core, architecture, and instructions for use in conjunction with the present invention are found in U.S. patent application Ser. No. 08/885,310 filed Jun. 30, 1997, now U.S. Pat. No. 6,023,753, U.S. patent application Ser. No. 08/949,122 filed Oct. 10, 1997, now U.S. Pat. No. 6,167,502, U.S. patent application Ser. No. 09/169,255 filed Oct. 9, 1998, U.S. patent application Ser. No. 09/169,256 filed Oct. 9, 1998, now U.S. Pat. No. 6,167,501, U.S. patent application Ser. No. 09/169,072 filed Oct. 9, 1998, U.S. patent application Ser. No. 09/187,539 filed Nov. 6, 1998, now U.S. Pat. No. 6,151,668, U.S. patent application Ser. No. 09/205,558 filed Dec. 4, 1998, now U.S. Pat. No. 6,173,389, U.S. patent application Ser. No. 09/215,081 filed Dec. 18, 1998, now U.S. Pat. No. 6,101,592, U.S. patent application Ser. No. 09/228,374 filed Jan. 12, 1999 now U.S. Pat. No. 6,216,223, U.S. patent application Ser. No. 09/238,446 filed Jan. 28, 1999, U.S. patent application Ser. No. 09/267,570 filed Mar. 12, 1999, U.S. patent application Ser. No. 09/337,839 filed Jun. 22, 1999, U.S. patent application Ser. No. 09/350,191 filed Jul. 9, 1999, U.S. patent application Ser. No. 09/422,015 filed Oct. 21, 1999 entitled “Methods and Apparatus for Abbreviated Instruction and Configurable Processor Architecture”, U.S. patent application Ser. No. 09/432,705 filed Nov. 2, 1999 entitled “Methods and Apparatus for Improved Motion Estimation for Video Encoding”, U.S. patent application Ser. No. 09/471,217 filed Dec. 23, 1999 entitled “Methods and Apparatus for Providing Data Transfer Control”, U.S. patent application Ser. No. 09/472,372 filed Dec. 23, 1999 entitled “Methods and Apparatus for Providing A Direct Memory Access Control”, U.S. patent application Ser. No. 09/596,103 entitled “Methods and Apparatus for Data Dependent Address Operations and Efficient Variable Length Code Decoding in a VLIW Processor” filed Jun. 16, 2000, U.S. patent application Ser. No. 09/598,567 entitled “Methods and Apparatus for Improved Efficiency in Pipeline Simulation and Emulation” filed Jun. 21, 2000, U.S. patent application Ser. No. 09/598,564 entitled “Methods and Apparatus for Initiating and Resynchronizing Multi-Cycle SIMD Instructions” filed Jun. 21, 2000, U.S. patent application Ser. No. 09/598,566 entitled “Methods and Apparatus for Generalized Event Detection and Action Specification in a Processor” filed Jun. 21, 2000, and U.S. patent application Ser. No. 09/598,084 entitled “Methods and Apparatus for Establishing Port Priority Functions in a VLIW Processor” filed Jun. 21, 2000, U.S. patent application Ser. No. 09/599,980 entitled “Methods and Apparatus for Parallel Processing Utilizing a Manifold Array (ManArray) Architecture and Instruction Syntax” filed Jun. 22, 2000, U.S. patent application Ser. No. 09/791,940 entitled “Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller” filed Feb. 23, 2001, U.S. patent application Ser. No. 09/792,819 entitled “Methods and Apparatus for Flexible Strength Coprocessing Interface” filed Feb. 23, 2001, U.S. patent application Ser. No. 09/792,256 entitled “Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response” filed Feb. 23, 2001, as well as, Provisional Application Serial No. 60/113,637 entitled “Methods and Apparatus for Providing Direct Memory Access (DMA) Engine” filed Dec. 23, 1998, Provisional Application Serial No. 60/113,555 entitled “Methods and Apparatus Providing Transfer Control” filed Dec. 23, 1998, Provisional Application Serial No. 60/139,946 entitled “Methods and Apparatus for Data Dependent Address Operations and Efficient Variable Length Code Decoding in a VLIW Processor” filed Jun. 18, 1999, Provisional Application Serial No. 60/140,245 entitled “Methods and Apparatus for Generalized Event Detection and Action Specification in a Processor” filed Jun. 21, 1999, Provisional Application Serial No. 60/140,163 entitled “Methods and Apparatus for Improved Efficiency in Pipeline Simulation and Emulation” filed Jun. 21, 1999, Provisional Application Serial No. 60/140,162 entitled “Methods and Apparatus for Initiating and Re-Synchronizing Multi-Cycle SIMD Instructions” filed Jun. 21, 1999, Provisional Application Serial No. 60/140,244 entitled “Methods and Apparatus for Providing One-By-One Manifold Array (1×1 ManArray) Program Context Control” filed Jun. 21, 1999, Provisional Application Serial No. 60/140,325 entitled “Methods and Apparatus for Establishing Port Priority Function in a VLIW Processor” filed Jun. 21, 1999, Provisional Application Serial No. 60/140,425 entitled “Methods and Apparatus for Parallel Processing Utilizing a Manifold Array (ManArray) Architecture and Instruction Syntax” filed Jun. 22, 1999, Provisional Application Serial No. 60/165,337 entitled “Efficient Cosine Transform Implementations on the ManArray Architecture” filed Nov. 12, 1999, and Provisional Application Serial No. 60/171,911 entitled “Methods and Apparatus for DMA Loading of Very Long Instruction Word Memory” filed Dec. 23, 1999, Provisional Application Serial No. 60/184,668 entitled “Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller” filed Feb. 24, 2000, Provisional Application Serial No. 60/184,529 entitled “Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response” filed Feb. 24, 2000, Provisional Application Serial No. 60/184,560 entitled “Methods and Apparatus for Flexible Strength Coprocessing Interface” filed Feb. 24, 2000, Provisional Application Serial No. 60/203,629 entitled “Methods and Apparatus for Power Control in a Scalable Array of Processor Elements” filed May 12, 2000, Provisional Application Serial No. 60/241,940 entitled “Methods and Apparatus for Efficient Vocoder Implementations” filed Oct. 20, 2000, Provisional Application Serial No. 60/251,072 entitled “Methods and Apparatus for Providing Improved Physical Designs and Routing with Reduced Capacitive Power Dissipation” filed Dec. 4, 2000, Provisional Application Serial No. 60/281,523 entitled “Methods and Apparatus for Generating Functional Test Programs by Traversing a Finite State Model of Instruction Set Architecture” filed Apr. 4, 2001, Provisional Application Serial No. 60/283,582 entitled “Methods and Apparatus for Automated Generation of Abbreviated Instruction Set and Configurable Processor Architecture” filed Apr. 27, 2001, Provisional Application Serial No. 60/288,965 entitled “Methods and Apparatus for Removing Compression Artifacts in Video Sequences” filed May 4, 2001, Provisional Application Serial No. 60/298,696 entitled “Methods and Apparatus for Generalized Event Detection and Action Specification in a Processor for Providing Embedded Exception Handling” filed Jun. 15, 2001, and Provisional Application Serial No. 60/298,695 entitled “Methods and Apparatus for Self Tracking Read Delay Write for Low Power Memory” filed Jun. 15, 2001, and Provisional Application Serial No. 60/298,624 entitled “Modified Single Ended Write Approach for Multiple Write-Port Register Files filed Jun. 15, 2001, all of which are assigned to the assignee of the present invention and incorporated by reference herein in their entirety.

[0021] Turning to specific aspects of the present invention, FIG. 2 illustrates a simplified block diagram of a ManArray 2×2 processor 20 for processing four voice conversations or channels 22, 24, 26, 28 in parallel utilizing PE031, PE134, PE236, PE338 and SP 40 connected by a cluster switch CS 42. The advantages of this approach and exemplary code are addressed further below following a more detailed discussion of the ManArray™ processor.

[0022] In a presently preferred embodiment of the present invention, a ManArray™ 2×2 iVLIW single instruction multiple data stream (SIMD) processor 100 shown in FIG. 3 contains a controller sequence processor (SP) combined with processing element-0 (PE0) SP/PE0101, as described in further detail in U.S. patent application Ser. No. 09/169,072 entitled “Methods and Apparatus for Dynamically Merging an Array Controller with an Array Processing Element”. Three additional PEs 151, 153, and 155 are also utilized to demonstrate improved parallel array processing with a simple programming model in accordance with the present invention. It is noted that the PEs can be also labeled with their matrix positions as shown in parentheses for PE0 (PE00) 101, PE1 (PE01) 151, PE2 (PE10) 153, and PE3 (PE11) 155. The SP/PE0101 contains a fetch controller 103 to allow the fetching of short instruction words (SIWs) from a 32-bit instruction memory 105. The fetch controller 103 provides the typical functions needed in a programmable processor such as a program counter (PC), branch capability, digital signal processing loop operations, support for interrupts, and also provides the instruction memory management control which could include an instruction cache if needed by an application. In addition, the SIW I-Fetch controller 103 dispatches 32-bit SIWs to the other PEs in the system by means of a 32-bit instruction bus 102.

[0023] In this exemplary system, common elements are used throughout to simplify the explanation, though actual implementations are not so limited. For example, the execution units 131 in the combined SP/PE0101 can be separated into a set of execution units optimized for the control function, for example, fixed point execution units, and the PE0 as well as the other PEs 151, 153 and 155 can be optimized for a floating point application. For the purposes of this description, it is assumed that the execution units 131 are of the same type in the SP/PE0 and the other PEs. In a similar manner, SP/PE0 and the other PEs use a five instruction slot iVLIW architecture which contains a very long instruction word memory (VIM) memory 109 and an instruction decode and VIM controller function unit 107 which receives instructions as dispatched from the SP/PE0's I-Fetch unit 103 and generates the VIM addresses-and-control signals 108 required to access the iVLIWs stored in the VIM. These iVLIWs are identified by the letters SLAMD in VIM 109. The loading of the iVLIWs is described in further detail in U.S. patent application Ser. No. 09/187,539 entitled “Methods and Apparatus for Efficient Synchronous MIMD Operations with iVLIW PE-to-PE Communication”. Also contained in the SP/PE0 and the other PEs is a common PE configurable register file 127 which is described in further detail in U.S. patent application Ser. No. 09/169,255 entitled “Methods and Apparatus for Dynamic Instruction Controlled Reconfiguration Register File with Extended Precision”.

[0024] Due to the combined nature of the SP/PE0, the data memory interface controller 125 must handle the data processing needs of both the SP controller, with SP data in memory 121, and PE0, with PE0 data in memory 123. The SP/PE0 controller 125 also is the source of the data that is sent over the 32-bit broadcast data bus 126. The other PEs 151, 153, and 155 contain common physical data memory units 123′, 123″, and 123′″ though the data stored in them is generally different as required by the local processing done on each PE. The interface to these PE data memories is also a common design in PEs 1, 2, and 3 and indicated by PE local memory and data bus interface logic 157, 157′ and 157″. Interconnecting the PEs for data transfer communications is the cluster switch 171 more completely described in U.S. patent application Ser. No. 08/885,310 entitled “Manifold Array Processor”, U.S. patent application Ser. No. 09/949,122 entitled “Methods and Apparatus for Manifold Array Processing”, and U.S. patent application Ser. No. 09/169,256 entitled “Methods and Apparatus for ManArray PE-to-PE Switch Control”. The interface to a host processor, other peripheral devices, and/or external memory can be done in many ways. The primary mechanism shown for completeness is contained in a direct memory access (DMA) control unit 181 that provides a scalable ManArray data bus 183 that connects to devices and interface units external to the ManArray core. The DMA control unit 181 provides the data flow and bus arbitration mechanisms needed for these external devices to interface to the ManArray core memories via the multiplexed bus interface represented by line 185. A high level view of a ManArray Control Bus (MCB) 191 is also shown.

[0025] Turning now to specific details of the ManArray™ architecture and instruction syntax as adapted by the present invention, this approach advantageously provides a variety of benefits. Specialized ManArray™ instructions and the capability of this architecture and syntax to use an extended precision representation of numbers (up to 64 bits) make it possible to design a vocoder so that the processing of one data-frame always takes the same number of cycles.

[0026] The adaptive nature of vocoders makes the voice processing data dependent in prior art vocoder processing. For example, in the Autocorr function, there is a processing block that shifts down input data and repeats computation of the zeroeth correlation coefficient until the correlation coefficient stops overflow the 32-bit format. Thus, the number of repetitions is dependent on the input data. In the ACELP_Code_A function, the number of filter coefficients to be updated equals either (T0-L_SUBFR) if the computed value of T0<L_SUBFR or 0 otherwise. Thus processing is data dependent varying depending upon the value of T0. In the Pitch_fr3_fast function, the fractional pitch search −⅓ and +⅓ is not performed if the computed value of T0>84 for the first sub-frame in the frame, Again, processing is clearly data dependent. Therefore, processing of a particular frame of speech requires a different number of arithmetical operations depending on the frame data which determine what kind of conditions have been or have not been triggered in the current and, generally, the previous sub-frame.

[0027] The following example taken from the function Az_lsp (which is part of LP analysis, quantization, interpolation in FIG. 1) illustrates how the present invention (1) changes the standard C code to permit implementation of a function without using conditional jumps from one part of the function to another and/or conditional returns from a function, and (2) individual functions are implemented in a non data dependent way (so that they always take the same number of cycles regardless of what data are processed).

ITU Standard Code
while ((nf<M) && (j<GRID_POINTS))
{
j++;
{
do_something:
}
}

[0028] is changed under the present invention to the following:

for( j=0; j<GRID_POINTS;j++)
{
if ( nf<M)
{
do_something;
}
else
{
do_nothing; /* takes the same number of
operations as do_something
/* with no effect on data and variables,
“idle” processing
}
}

[0029] Usage of the for-loop makes the process free of conditional parts, and usage of the if-else structure synchronizes execution of this code for different input data.

[0030] The following example taken from the function Autocorr (part of LP analysis, quantization, interpolation in FIG. 1) illustrates another technique, according to the present invention which is suitable for eliminating data dependency.

     ITU Standard Code
do { /* Compute r[0] and test for overflow */
     Overflow = 0;
     sum = 1;          /* Avoid case of all zeros */
     for(i=0; i<L_WINDOW; i++)
     sum = L_mac(sum, y[i], y[i]);
     if(Overflow != 0) /* If overflow divide y[] by 4 */
     {
     for(i=0; i<L_WINDOW; i++)
     {
     y[i] = shr(y[i], 2);
     }
     }
}while (Overflow != 0);

[0031] may be advantageously implemented in the following way in a ManArray™ DSP:

(Word64)sum = 1;         /* Avoid case of all zeros */
for(i=0; i<L_WINDOW; i++)
                         (Word64)sum = (Word64)L_mac((Word64)sum, y[i], y[i]);
N =  norm((Word64)sum);  /* Determine number of
N =  ceil(shr(N-30, 2)); bits in sum */
if (N < 0) N = O;
for(i=0; i<L_WINDOW; i++)
{
                         y[i] = shr(y[i], 2N);
}

[0032] In the latter implementation, two ManArray™ features are highly advantageous. The first one is the capability to use 64-bit representations of numbers (Word64) both for storage and computation. The other one is the availability of specialized instructions such as a bit-level instruction to determine the highest bit that is on in a binary representation of a number (N=norm((Word64)sum)). Utilizing and adapting these features, the above implementation always requires the same number of cycles. Incidentally, this approach is more efficient because it makes possible the elimination of an exhaustive and non-deterministic do { . . . } while (Overflow !=0) loop.

[0033] Thus, implementation of the first two changes makes it possible to create a control code common for all PEs. In other words, all loops start and end at the same time, a new function is called synchronously for all PEs, etc. Redesigned vocoder control structure and the availability of multiple processing elements (PEs) in the ManArray™ DSP architecture make possible the processing of several different voice channels in parallel.

[0034] Parallelization of vocoder processing for a DSP having N processing elements has several advantages, namely:

[0035] It increases the number of channels per DSP or total system throughput.

[0036] The clock rate can be lower than is typically used in voice processing chips thereby lowering overall power usage.

[0037] Additional power savings can be achieved by turning a PE off when it has finished processing but some other PEs are still processing data.

[0038] An implementation of the G729a vocoder takes about 86,000 cycles utilizing a ManArray 1×2 configuration for processing two voice channels in parallel. Thus, the effective number of cycles needed for processing of one channel is 43,000, which is a highly efficient implementation. The implementation is easily scalable for a larger number of PEs, and in the 2×2 ManArray configuration the effective number of cycles per channel would be about 21,500.

[0039] Further details of a presently preferred implementation of a G.729A reduced complexity of 8 kbit/s CS-ACELP Speech Codec follow below. Sequential code follows as Table I and iVLIW code follows as Table II.

[0040] In one embodiment of the present invention, the ANSI-c Source Code, Version 1.1, September 1996 of Annex A to ITU-T Recommendation G.729, G.729A, was implemented on the BOPS, Inc. Manta co-processor core. G.729A is a reduced complexity 8 kilobits per second (kbps) speech coder that uses conjugate structure algebraic-code-exited linear-prediction (CS-ACELP) developed for multimedia simultaneous voice and data applications. The coder assumes 16-bit linear PCM input.

[0041] The Manta co-processor core combines four high-performance 32-bit processing elements (PE0, 1,2,3) with a high performance 32-bit sequence processor (SP). A high-performance DMA, buses and scalable memory bandwidth also complement the core. Each PE has five execution units: a MAU, an ALU, a DSU, and LU and an SU. The ALU, MAU and DSU on each PE support both fixed-point and single-precision floating-point operations. The SP, which is merged with PE0, has it's own five execution units: an MAU, an ALU, a DSU, an LU, and an SU. The SP also includes a program flow control unit (PCFU), which performs instruction address generation and fetching, provides branch control, and handles interrupt processing.

[0042] Each SP and each PE on the Manta use an indirect very long instruction word (iVLIW™) architecture. The iVLIW design allows the programmer to create optimized instructions for specific applications. Using simple 32-bit instruction paths, the programmer can crate a cache of application-optimized VLIWs in each PE. Using the same 32-bit paths, these iVLIWs are triggered for execution by a single instruction, issued across the array. Each iVLIW is composed by loading and concatenating five 32-bit simplex instructions in each PE's iVLIW instruction memory (VIM). Each of the five individual instruction slots can be enabled and disabled independently. The ManArray programmer can selectively mask PEs in order to maximize the usage of available parallelism. PE masking allows a programmer to selectively operate any PE. A PE is masked when its corresponding PE mask bit in SP SCR1 is set. When a PE is masked, it still receives instructions, but it does not change its internal register state. All instructions check the PE mask bits during the decode phase of the pipeline.

[0043] The prior art CS-ACELP coder is based on code excited linear-prediction (CELP) coding model discussed in greater detail above. A block diagram for an exemplary G.729A encoder 10 is shown in FIG. 1 and discussed above. A corresponding prior art decoder 400 is shown in FIG. 4.

[0044] The overall Manta program set-up in accordance with one embodiment of the present invention is summarized as follows.

[0045] The calculations and any conditional program flow are done entirely on the PE for scalability.

[0046] eploopi3 is used in the main loops of the functions coder and decoder. eploopi2 is used in the main loops of the functions Coder—1d8a and Decod—1d8a.2.

[0047] SP A0-A1 and PE A0-A1 are used for pointing to input and output of coder.s or decoder.s.

[0048] PE A2 points to the address of encoded parameters, PRM[ ] in the encoder or parm[ ] in the decoder.

[0049] PE R0-R9 are used for debug and most often used constants or variables defined as follows:

PE R0, R1, R2 = DMA or debut or system
PE R3         = +332768 or 0x000080000
PE R4 and R5  = 0
PE R6         = +2147483647 or 0x7FFFFFFF
PE R7         = −2147483648 or 0x800000000
PE R8         = frame
PE R9         = i_subfr

[0050] SP/PE R10-R31, PE A3-A7 and SP A2-A6 are available for use by any function as needed for input or as scratch registers.

[0051] Sp A7 is used for pushing/popping the address to return to after a call on a stack defined in SP memory by the symbol ADDR_ULR_Stack in the file globalMem.s. The current stack pointer is saved in the SP memory location defined by the symbol ADDR_ULR_STACK_TOP_PTR in the file globalMem.s. The macros Push_ULR spar and Pop_ULR spar, which are defined in 1d8A_h.s, are to be used at the beginning and end of each function for pushing/popping the address to return to after a call.

[0052] The macros PEx_ON Pemask and PEs_OFF Pemask, which are defined in 1d8a_h.s, are used to mask on/off Pes are required.

[0053] If two 16-bit variables were used for a 32-bit variable in the ITU C-code (i.e., r_h and r_l), 32-bit memory stores, loads and calculations were used in Manta instead (i.e., r).

[0054] The sequential and iVLIW code are rigorously tested with the test vectors obtained from the ITU and VoiceAge to ensure that given the same input as for the ITU C source code, the assembly code provides the same bit-exact output.

[0055] The file 1d—8ah.s contains all constants and macros defined in the ITU C source code file 1d8A.h. It also controls how many frames are processed using the constant NUM-FRAMES.

[0056] The file 1d—8Ah.s contains all constants and macros defined in the ITU C source code file 1d8a.h. It also controls how many frames are processed using the constant NUM-FRAMES.

[0057] The file globalMem.s contains all global tables and global data memory defined. Most of the tables are in SP memory, but some were moved to PE memory as needed to reduce the number of cycles. A lot of the functions use temporary memory that starts with the symbol temp_scratch_pad. The assumption is that after a particular function uses that temporary memory, it is available to any function after it. If a variable or table needs to be aligned on a word or double word boundary, it is explicitly defined that way by using the align instruction.

[0058] The PE data memory, defined in globalMem.s, is set up as shown in the table 500 of FIG. 5 in order to DMA the encoder and decoder variables that need to be saved for the next frame in contiguous blocks.

[0059] Table 600 of FIG. 6 shows a comparison of a Manta 1×1 sequential processing embodiment in column 610 and an iVLIW implementation in column 620 of G.729A. Both versions were about 80% optimized and could yield another 10-20% less cycles if optimized further. iVLIW memory is re-usable and loaded as needed by each function from the first VIM slot. Through the use of PE masking, the code can be run in a 1×1 or 1×2 or 2×2 configuration as long as the channel data is present in each PE. The number of PEs in a 1×2 or a 2×2 should be used to divide the cycles per frame numbers in table 600, which are for a 1×1 implementation. All PEs use the same instructions and tables from the SP but would save the channel specific information in the variables in their own PE data memory.

[0060] While the present invention has been disclosed in a presently preferred context, it will be recognized that the present invention may be variously embodied consistent with the disclosure and the claims which follow below.

Claims

1. A digital signal processor having: N parallel processing elements; a cluster switch mechanism connecting the N parallel processing elements; a sequence processor for controlling the N parallel processing elements to operate as a single instruction multiple data parallel processor array; and N channels of voice communication data, data from one of said channels provided to each one of said parallel processing elements, whereby the data for the voice communication channels are processed in parallel.

2. The digital signal processor of claim 1 further comprising C code to control said parallel processing which has been adapted to permit implementation of a function without using conditional jumps from one part of the function to another.

3. The digital signal processor of claim 1 further comprising C code to control said parallel processing whereby individual functions are implemented in a non-data dependent way so that they always take the same number of cycles regardless of what data are processed.

4. The digital signal processor of claim 1 further comprising C code to control said parallel processing in which control code to be run on the sequence processor is separated from the data processing code to be run on the processing elements.

5. The digital signal processor of claim 1 wherein power savings are achieved by turning a processing element off when it has finished processing but some other processing elements are still processing.

6. The digital signal processor of claim 1 wherein N equals four and the processor array is a 2×2 ManArray configuration implementing a G729a vocoder which takes about 21,500 cycles per channel or less.

7. A method for efficiently implementing a vocoder in a digital signal processor comprising the steps of: providing N channels of voice communication; connecting one of said channels to one of N parallel processing elements; communicating between the N parallel processing elements utilizing a cluster switch mechanism connecting the N parallel processing elements; and utilizing a sequence processor to control the N parallel processing elements to operate as a single instruction multiple data parallel processor array and process the voice communication channels in parallel.

8. The method of claim 7 further comprising the step of utilizing C code to control said parallel processing, said code having been adapted to permit implementation of a function without using conditional jumps from one part of the function to another.

9. The method of claim 7 further comprising the step of utilizing C code to control said parallel processing whereby individual functions are implemented in a non-data dependent way so that they always take the same number of cycles regardless of what data are processed.

10. The method of claim 7 further comprising the step of utilizing C code to control said parallel processing in which control code to be run on the sequence processor is separated from the data processing code to be run on the processing elements.

11. The method of claim 7 wherein power savings are achieved by turning a processing element off when it has finished processing but some other processing elements are still processing.

12. The method of claim 7 wherein N equals four and the processor array is a 2×2 ManArray configuration implementing a G729a vocoder which takes about 21,500 cycles-per channel or less.

13. A digital signal processor supporting conditional execution and having: N parallel processing elements; a sequence processor for distributing the same conditional instructions to each of the N parallel processing elements; and N channels of voice communication data, one of said channels connected to each one of said parallel processing elements, whereby the voice communication data is processed in parallel in response to said conditional instructions.

14. The digital processor of claim 1 further comprising code to control said parallel processing which has been adapted to permit implementation of a function without using conditional jumps from one part of the function to another.

15. The digital process of claim 1 further comprising code to control said parallel processing whereby individual functions are implemented in a non-data dependent way so that said functions always take the same number of cycles regardless of what data are processed.