Claims
- 1. A host controller for enabling communication between a host computer and a device over a serial link, comprising:a bus interface circuit connected to a system bus of the host computer; host controller registers to enable code configuration of the host controller for operation, initialize the device, and send commands to the device; a packet generator/decoder circuit for polling and for sending and receiving packets to or from the device, wherein the polling controls a data flow and prevents buffers from being underrun and overrun; and a serializer/deserializer for converting parallel data containing ATA/ATAPI commands received from the bus interface circuit and to be sent over the serial link to the device into serial data and converting serial data received from the serial link to parallel data to be sent to the bus interface circuit and to the host computer.
- 2. A host controller for enabling communication between a host computer and a device over a serial link as recited in claim 1, further comprising:an encoder/decoder for converting bit streams of serial data received from the serializer/deserializer into encoded data, and decoding data received from the serial link into bit streams of serial data.
- 3. A host controller for enabling communication between a host computer and a device over a serial link as recited in claim 2, further comprising:a set of transceivers being coupled to the encoder/decoder, one of the transceivers being configured to communicate with the device over the serial link.
- 4. A host controller for enabling communication between a host computer and a device over a serial link as recited in claim 3, further comprising:storage area for storing communication parameters, including, ATA/ATAPI commands and status for the device and for other devices connected to selected ones of the set of transceivers; and interrupt status FIFOs that are in communication with an interrupt status of the host controller registers.
- 5. A host controller for enabling communication between a host computer and a device over a serial link as recited in claim 1, wherein the host controller is in communication with a host controller driver of the host computer.
- 6. A host controller for enabling communication between a host computer and a device over a serial link as recited in claim 1, further comprising:a BIOS expansion ROM to enable the device to be a bootable device.
- 7. A host controller for enabling communication between a host computer and a device over a serial link as recited in claim 1, wherein a host controller driver (HCD) provides an operating system of the host computer with capabilities for detecting an attachment, a removal, and an initialization of the device, the HCD is also configured to perform command generation, data transfers, and status retrieval.
- 8. A host controller for enabling communication between a host computer and a device over a serial link as recited in claim 1, wherein the bus interface circuit is a PCI bus interface.
- 9. A host controller for enabling communication between a host computer and a device over a serial link as recited in claim 1, wherein the device is a block oriented device capable of attaining link speeds of one of 320 Mbps, 640 Mbps, and 960 Mbps.
- 10. A host controller chip integrated into a host adapter, the host controller chip being configured to enable communication between a host computer that has the host adapter connected thereto and a peripheral device, comprising:a serial cable being configured to interconnect the host adapter to the peripheral device, the serial cable including, a first differential pair for data; a second differential pair for strobe; and a pair for ground; a PCI bus interface circuit for connecting the host adapter to the host computer; host controller registers integrated into the host controller chip to enable configuration of the host adapter for operation, initialize the peripheral device, and enable command transmission to the peripheral device over the serial cable; a packet generator/decoder circuit integrated into the host controller chip for polling the peripheral device and for sending and receiving packets to and from the peripheral device, wherein the polling controls a data flow and prevents buffers from being underrun and overrun; and a serializer/deserializer circuit integrated into the host controller chip for converting parallel data containing ATA/ATAPI commands received from the PCI bus interface circuit and to be sent over the serial cable to the peripheral device into serial data and converting serial data received from the serial cable into parallel data to be sent to the PCI bus interface circuit and to the host computer.
- 11. A host controller chip integrated into a host adapter as recited in claim 10, wherein the peripheral device is a block oriented device.
- 12. A host controller chip integrated into a host adapter as recited in claim 11, wherein the block oriented device is one of a hard disk drive, a floppy disk drive, a tape drive, a CD-ROM drive, and an optical disk drive.
- 13. A host controller chip integrated into a host adapter as recited in claim 10, wherein the host controller chip is interfaced with an IDE controller chip.
- 14. A host controller chip integrated into a host adapter as recited in claim 10, wherein the host controller chip includes IDE circuitry.
- 15. A host controller chip integrated into a host adapter as recited in claim 10, wherein the packet is defined by packet types consisting of:an OUTDATA0/1 packet type; an INSTART packet type; an INSTOP packet type; an ACK packet type; a HEARTBEAT packet type; and a RESET packet type.
- 16. A host controller chip integrated into a host adapter as recited in claim 10, further comprising:an encoder/decoder circuit being integrated into the controller chip for converting bit streams of serial data received from the serializer/deserializer into encoded data and strobe signals to be communicated over the serial cable, and decoding data and strobe signals received from the serial cable into bit streams of serial data.
- 17. A host controller chip integrated into a host adapter as recited in claim 10, further comprising:a set of transceivers being integrated into the host controller chip, the set of transceivers being coupled to the encoder/decoder, and one of the transceivers being configured to communicate with the peripheral device over the serial cable.
- 18. A host controller chip integrated into a host adapter as recited in claim 17, further comprising:a storage area integrated into the host controller chip for storing communication parameters, including, ATA/ATAPI commands and status for the peripheral device and for other peripheral devices connected to selected ones of the set of transceivers; and interrupt status FIFO buffers that are in communication with an interrupt status of the host controller registers.
- 19. A host controller chip integrated into a host adapter as recited in claim 10, wherein the host controller chip is in communication with a host controller driver (HCD) of the host computer.
- 20. A host controller chip integrated into a host adapter as recited in claim 19, wherein the host controller driver (HCD) provides an operating system of the host computer with capabilities for detecting an attachment, a removal, and an initialization of the peripheral device, and the HCD is also configured to control command generation, data transfers, and status retrieval.
- 21. A host controller chip integrated into a host adapter as recited in claim 10, further comprising:a BIOS expansion ROM integrated into the host controller chip to enable the peripheral device or other peripheral devices connected to the host adapter to be bootable devices.
- 22. A host controller chip integrated into a host adapter as recited in claim 10, wherein the peripheral device is capable of attaining link speeds of one of 320 Mbps, 640 Mbps, and 960 Mbps.
- 23. A system for executing data transfers between a host computer and a peripheral device over a serial link, comprising:a CPU for setting up a command descriptor block (CDB) with an ATA/ATAPI command and a scatter/gather list in a system memory; a pointer register resident in a host controller chip, the CPU being configured to write an address of the CDB into the pointer register; a DMA controller for instructing a transfer of the CDB to RAM memory of the host controller chip; the host controller chip being configured to send the CDB to a peripheral device over a serial physical cable, the host controller chip further being configured to poll the peripheral device for data packets; the device being configured to respond to the poll by sending data packets to the RAM of the host controller chip; a data buffer being configured to receive the data packets at the direction of the DMA controller, the data buffer being pointed to the scatter/gather list in the system memory; and the host controller chip being configured to set up an interrupt status to interrupt the CPU indicative of the receipt of the data packets from the peripheral device.
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority from U.S. Provisional Patent Application No. 60/124,813, filed Mar. 17, 1999, and entitled “CHEX SERIAL BUS PROTOCOL ADVANCED SERIAL BUS.” This provisional application is herein incorporated by reference. This application is also related to: (1) U.S. patent application Ser. No. 09/526,028, filed on the same day as the instant application and entitled “METHODS AND APPARATUS FOR IMPLEMENTING A DEVICE SIDE ADVANCED SERIAL PROTOCOL,” and (2) U.S. patent application Ser. No. 09/526,030, filed on the same day as the instant application and entitled “HOST AND DEVICE SERIAL COMMUNICATION PROTOCOLS AND COMMUNICATION PACKET FORMATS.” These application are hereby incorporated by reference.
US Referenced Citations (7)
Non-Patent Literature Citations (1)
Entry |
IBM Technical Disclosure Bulletin, Feb. 1, 1987, US vol. No. 29, Issue No. 9, p. No. 3784-3785. |
Provisional Applications (1)
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Number |
Date |
Country |
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60/124813 |
Mar 1999 |
US |