Patent Application
20060294345
This invention relates generally to processor architectures, and more specifically, to methods and apparatus for implementing branching instructions within processors.
Embedded processors are often configured with limited space for code and a limited time to accomplish the assigned processing tasks. As an example of such limitations, prior approaches regarding processors generally involve the incorporation of branch instructions following every comparison that is executed within a program. The incorporation of multiple branch instructions generally lead to additional program space (e.g., memory) requirements and more program code is involved in the execution of such instructions. The additional program code may also lead to increases in execution times, which can sometimes present problems in real time applications.
To illustrate further, the following pseudo-code represents a high level function:
The following is the above high level function reduced to processor operational codes:
In this specific example, each operational code takes one clock cycle to execute. Also specific to this example, branch operational codes take three clock cycles to execute when the branch is taken, and one clock cycle when the branch is not taken. The number of clock cycles for particular instructions varies will each processor implementation. However, such timing differences in branching instruction execution is typical of pipelined processors because if a branch is to be taken, an instruction pipeline, or instruction queue must be emptied (sometimes referred to as being flushed) and refilled with the operational codes relating to the branch to be next executed by the processor.
In an exemplary embodiment, a processor comprising a plurality of registers configured as a status stack is provided. The processor is configured to sequentially store results from status producing instruction executions in said status stack and implement a branching instruction that operates based on at least one of the stored results.
In another exemplary embodiment, a method for implementing branching instructions within a processor is provided. The method comprises executing a plurality of operational codes, each of which provides a status result, sequentially storing the status results, and utilizing one or more of the status results to determine whether a branching operation is to be executed.
In still another exemplary embodiment, a logic circuit for incorporation within a processing unit is provided. The logic circuit comprises a comparator configured to output a status result from an instruction executed by the processing unit, a plurality of registers configured as a stack, and a branching circuit. The comparator is configured to provide the status result to a first of the registers within the stack. The branching circuit is configured to receive a status opcode relating to status results stored in the registers, and further configured to apply a logical combination, based on the status opcode, to a number of the status results.
Referring specifically to
The result is that the processor incorporating ALU 21 is able to provide desired functional results while incorporating only one branch instruction that acts on the results (e.g., a logical combination) of the three comparisons. In other words, the branching instruction provides logical capabilities that allow the processor incorporating ALU 21 to execute a single branching instruction, without sequentially comparing, branching, comparing, branching, etc.
In order to push the result of the compare onto the stack, the comparator 40 is configured to activate a push the comparison result (push_cmp_result) signal, which enables the latest compare result to be shifted onto the first register of the status stack 42. The status stack 42 is constructed from a plurality of serial shift registers 46 in one embodiment, and referring to the specific embodiment of
The branch logic 44 logically combines a number of comparison results stored within the shift registers 46 of status stack 42 to determine whether a branch operation is to be performed. In the example of
To implement the above described method, certain features (comparator 40, status stack 42, and branch logic 44) may be implemented within the above described arithmetic logic unit 21. As described above, a status stack 42 is configured to sequentially store status of arithmetic operations. As such, whenever a new instruction executes that generates a status, its results are pushed onto a top of the status stack 42, and all previous results are pushed farther into the status stack 42. Typically however, the status stack 42 is a predetermined size and eventually results of such arithmetic and logical operations will be pushed off a bottom of the status stack 42. For example, consider the three compare operational instructions from the example above:
If it is assumed that the comparison operations (cmp) set a flag (one register of the status stack) to zero if the compared values are equal (a positive result) and one if the values are not equal (a negative result), and the results for the three compares are pushed onto the stack as follows:
The branching instruction illustrated above, “bne continue, 3;”, which generally means branch to the subroutine “continue” if the comparison results is not equal, also includes an instruction operand “3” that directly relates to the select opcode applied to the branch logic as defined above. The instruction operand in the code to be executed is logically applied as the select opcode to the branch logic and therefore instructs the processor 10 to select a predefined logical function to be applied to the stored results in the status stack 42 in order to make the branching decision. Referring again to the high level pseudo-code described above,
An example of the possible combinations for the three comparisons within the pseudo-code, identified by the stack locations A, B, and C follows:
In the example, there are seven possible logical combinations of A, B, and C, so the instruction operand would have to be at least a three bit field. In the example, the high level operation desired is similar to the function defined by the index of “3”. As such the instruction operand of the branching instruction is “3” (thus a select opcode of 3 is input into branch logic 44) and indicates to the processor 10 to apply the (A and B) or C function to the last three stored status results on the status stack. As the “A” and “B” registers both represent equal comparisons, the branch will not occur and the “dosomething” subroutine will be run.
The example herein utilized to illustrate the branching function uses a three deep status stack and provides seven instruction operand choices. However, other implementations which utilize other status stack sizes, and therefore another number of instruction operand choices, are contemplated and are limited only by the particular hardware limitations of each processor.
To further illustrate,
Applications for a processor incorporating a status stack to reduce the number of branching operations include, but are not limited to, applications relating to telecom switching, routers, multiplexers, and demultiplexers. Such a processor is further applicable to the processing of frames of telecom data, real time, and network termination devices where latencies cannot exceed a predetermined amount.
While the invention has been described in terms of various specific embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the claims.
