This patent document is directed generally to channel coding technique in communication systems.
Mobile telecommunication technologies are moving the world toward an increasingly connected and networked society. In comparison with the existing wireless networks, next generation systems and communication techniques will need to support a much wider range of use-case characteristics and provide a more complex and sophisticated range of access requirements and flexibilities.
Long-Term Evolution (LTE) is a standard for wireless communication for mobile devices and data terminals developed by 3rd Generation Partnership Project (3GPP). LTE Advanced (LTE-A) is a wireless communication standard that enhances the LTE standard. The 5th generation of wireless system, known as 5G, advances the LTE and LTE-A wireless standards and is committed to supporting higher data-rates, large number of connections, ultra-low latency, high reliability and other emerging business needs.
This patent document discloses techniques, among other things, rate matching design for polar coding, PAC coding and/or other pre-transformed polar coding schemes.
In one example aspect, a first digital communication method is disclosed. The method includes determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits, wherein the output bit sequence is determined by performing a polar transform with H components and a pre-transform; wherein the polar transform is based on H polar matrices G(N
In another example aspect, another method of wireless communication is disclosed. The method includes receiving, by a second node, a signal including an output bit sequence having E bits from a first node; and determining, by the second node, an input bit sequence having K bits based on the signal, wherein the output bit sequence is determined by performing a polar transform with H components and a pre-transform; wherein the polar transform is based on H polar matrices G(N
In yet another example aspect, a wireless communication device comprising a process that is configured or operable to perform the above-described methods is disclosed.
In yet another example aspect, a computer readable storage medium is disclosed. The computer-readable storage medium stores code that, upon execution by a processor, causes the processor to implement an above-described method.
Headings for the various sections below are used to facilitate the understanding of the disclosed subject matter and do not limit the scope of the claimed subject matter in any way. Accordingly, one or more features of one section can be combined with one or more features of another section. Furthermore, 5G terminology is used for the sake of clarity of explanation, but the techniques disclosed in the present document are not limited to 5G technology only and may be used in wireless systems that implemented other protocols.
This application proposes methods and apparatuses related to rate matching schemes for pre-transformed polar coding in wireless communication systems.
In the fifth generation (5G) mobile communications standard of the 3rd Generation Partnership Project (3GPP), low-density parity-check (LDPC) codes are used for data transmission. However, LDPC codes is worse than polar codes in short payload size (also called transport block size (TBS)). Also, LDPC codes have high error floors (at block error rate (BLER) of 0.0001). To fulfill the future ultra-reliable low latency communication (URLLC), we have to design more powerful channel codes.
Polarization-adjusted convolutional (PAC) codes can achieve finite-length bounds in moderate decoding complexity. PAC codes are a revolution of polar codes. As a result, PAC codes have code lengths with power of 2 (N=2n with positive integer n) as polar codes. However, to efficiently transmitting a payload (or transport block (TB)) in different wireless channel environments, it does not always have a code length of N=2n in time and frequency resources allocated by a base station (BS). As a result, rate matching schemes are needed for applying PAC codes in wireless communications. In this application, methods and apparatus for design in rate matching for polar coding, PAC coding, or other pre-transformed polar coding are proposed with good performance.
GF(2) denotes the Galois field of size 2 with two elements “0” and “1”.
br(i) is the bit-reversal function.
floor(x) denotes the largest integer not greater than x.
ceil(x) denotes the smallest integer not less than x.
round(x) is the round function such that round(x) is the integer closest to x, for example, round (3.2)=3, round (4.8)=5, round (2.5)=3, round (−1.9)=−2, round (−3.4)=−3.
max(x,y) denotes the maximum value between x and y, i.e.,
mod(x, y) denotes the remainder of x divided by y. For example, mod(5, 3)=2 and mod(3, 5)=3.
Xi, j denotes the element in the i-th row and j-th column of a matrix X, where a boldface capital letter is used to represent a matrix.
[x0, x1, . . . , xY−1] denotes a sequence (or a vector) of length Y containing elements x0, x1, . . . , xY−1. A boldface small letter x is used to represent a sequence (or a vector) [x0, x1, . . . , xY−1].
{x0, x1, . . . , xY−1} denotes a set with Y distinct elements x0, x1, . . . , xY−1, i.e., for any i≠j, xi≠xj.
<x0, x1, . . . , xY−1>denotes an ordered set with Y distinct elements x0, x1, . . . , xY−1, i.e., for any i≠j, xi≠xj. Let X=<x0, x1, . . . , xY−1>, X (i) denotes the i-th element x; in the ordered set X.
For a set X, |X| denotes the set size, i.e., the number of elements in the set X.
ZN={0, 1, . . . , N−2, N−1} denotes the integer set containing all non-negative integers smaller than N.
Indices for sequences, vectors, or matrices are starting from zero.
This section introduces some concepts of use of a polar matrix according to various embodiments.
We denote G(N) as a polar transform matrix (or simply, polar matrix) with N rows and N columns, where N is power of 2, i.e., N=2n and n is a positive integer. n is called the order of the polar matrix of G(N) and N is called the polar matrix size of G(N), i.e., G(N) is of size N.
G(N) can be one of the following:
Here, all the matrix operations are over GF(2), e.g.,
is the n-th Kronecker power of the matrix P(2), and B(N) is a bit-reversal permutation matrix with N rows and N columns, 0 is an all-zero matrix with N/2 rows and N/2 columns.
Let Bi,j (N) be the element at the i-th row and j-th column of the bit-reversal permutation matrix B(N). Then,
for 0≤i<N and 0≤j<N, where br(i) is the bit-reversal function defined as
and [bn−1, bn−2, . . . , b1, b0] is the n-bit binary expansion of the integer i, i.e.,
A sequence (or a vector) x of length N over GF(2) multiplying the polar matrix G(N) over GF(2) is called polar transform on the sequence (vector) x. Denote y=x·G(N), where the vector-matrix multiplication is over GF(2). Then, y is the polar transform of x.
Some example embodiments of use of polar coding according to 3GPP 5G standard are disclosed in this section.
In the 3GPP 5G standard, polar codes are used in control channel transmission. The diagram of 5G polar coding with rate matching is shown in
Denote Q a data bit index set of size K, i.e., |Q|=K, where Q is a subset of an integer set ZN={0, 1, . . . , N−2, N−1} containing all non-negative integers smaller than N. Then, the encoding of an input bit sequence c=[c0, c1, . . . , cK−2, cK−1] into an output bit sequence e=[e0, e1, . . . , eE−2, eE−1] for the 5G polar coding with a polar matrix G(N) includes the following operations, where K is the length of the input bit sequence, E is the length of the output bit sequence, K and E are positive integers, K<N, and K<E.
As shown in
(1) Adding frozen bits: The adding-frozen-bits operation combines N−K zero bits with the input bit sequence c to form a polar transform input sequence u=[u0, u1, . . . , uN−2, uN−1] of length N according to the data bit index set Q.
The polar transform input sequence u is determined by the input bit sequence c, the data bit index set Q, and the polar matrix size N as follows:
(2) Polar transform: The polar transform is converting a first length-N bit sequence into a second length-N bit sequence by multiplying the first length-N bit sequence and the polar matrix G(N) over GF(2). A polar transform output bit sequence d=[d0, d1, . . . , dN−2, dN−1] of length N is determined by the polar transform input sequence u and the polar matrix G(N) as d=u·G(N), where the vector-matrix multiplication is over GF(2).
(3) Rate matching: The rate matching of polar coding in 5G includes two operations: Sub-block interleaving and bit selection.
(3.1) Sub-block interleaving: An interleaving output bit sequence d′=[d′0, d′1, . . . , d′N−2, d′N−1] of length N is determined by a sub-block interleaver pattern π of length 32, the polar transform output bit sequence d, and the polar matrix size N as follows.
where π=[π0, π1, π2, π3, π4, π5, π6, π7, π8, π9, π10, π11, π12, π13, π14, π15, π16, π17, π18, π19, π20, π21, π22, π23, π24, π25, π26, π27, π28, π29, π30, π31, ]=[0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31], and J=[J0, J1, . . . , JN−2, JN−1] is an interleaver pattern of length N determined by the sub-block interleaver pattern π and the polar matrix size N. The interleaver pattern J is a permutation of the integer sequence [0, 1, 2, . . . , N−2, N−1].
(3.2) Bit selection: There are three types of bit selection named as repetition, puncturing and shortening. With the interleaving output bit sequence d′, the length of the input bit sequence K, the length of the output bit sequence E, and the polar matrix size N, the output bit sequence e is determined as follows:
Some example embodiments of PAC coding are disclosed in this section.
PAC codes is a class of pre-transformed polar codes. Specifically, PAC codes are polar codes using convolution transform.
The diagram of PAC coding is shown in
(1) Rate profiling: The rate profiling is an operation same as the adding-frozen-bits operation in the 5G polar coding. Thus, two terms “adding-frozen-bits” and “rate profiling” are used interchangeably to refer to the same operation in this document. The rate-profiling operation combines N−K zero bits with the input bit sequence c to form a rate-profiling output sequence v=[v0, v1, . . . , vN−2, vN−1] of length N according to the data bit index set Q. Specifically, the rate-profiling output bit sequence v is determined by the input bit sequence c, the data bit index set Q, and the polar matrix size N as follows.
(2) Convolution transform: the convolution transform is an operation converting a convolution input bit sequence of length N into a convolution output bit sequence of length N by performing convolution on the convolution input bit sequence and a generator bit sequence g=[g0, g1, . . . , gm−1, gm] of length-(m+1) defining a generator polynomial g(D)=g0+g1·D+ . . . +gm−1·Dm−1+gm·Dm over GF(2), where m is the memory length of the convolution transform or equivalently the generator polynomial degree of the generator polynomial g(D) and D is a dummy variable representing delay in a digital circuit.
The convolution transform with a generator polynomial g(D) is shown in
Polar transform: The polar transform is the same as in the 5G polar coding. A polar transform output bit sequence d=[d0, d1, . . . , dN−2, dN−1] of length N is determined according to the convolution transform output bit sequence u and the polar matrix G(N) as d=u·G(N), where the vector-matrix multiplication is over GF(2).
This section discloses multiple examples related to rate matching for polar coding, PAC coding, or other pre-transformed polar coding with good performance.
This section discloses an encoding method used in a wireless communication system.
In one example, a method of digital communication comprising obtaining, by a first node, an input bit sequence c=[c0, c1, . . . , cK−1]; and determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits, wherein the output bit sequence is determined by performing a polar transform with H components and a pre-transform; wherein the polar transform is based on H polar matrices G(N
Here, K is the input length of the input bit sequence c.
E is the output length of the output bit sequence e.
H is the number of component polar matrices.
K, E, and H are all positive integers. In one example, K, E, and H satisfy K<E and H<E.
H is an integer greater than one.
For h=0, 1, . . . , H−1, the h-th component polar transform is based on the h-th component polar matrix G(N
In one example, the summation of H component polar matrix sizes is equal to the output length E, i.e., N0+N1+ . . . +NH−1=E.
In another example, a method of digital communication may include obtaining, by a first node, an input bit sequence c=[c0, c1, . . . , cK−1]; and determining, by the first node, an output bit sequence e=[e0, e1, . . . , eE−1] by performing at least one of the following: a repetition, H component rate profiling, a first concatenation, a pre-transform, a segmentation, H component polar transform based on H polar matrices G(N
Here, K is the input length of the input bit sequence c; E is the output length of the output bit sequence e; H is the number of component polar matrices; W is the number of component interleaving.
In one example K, E, and H are positive integers and W is an integer not greater than H.
In another example, K, E, and H satisfy K<E and H<E.
H is an integer greater than one.
For h=0, 1, . . . , H−1, the h-th component polar transform is based on the h-th component polar matrix G(N
The summation of H component polar matrix sizes can be equal to the output length E, i.e., N0+N1+ . . . +NH−1=E.
This section discloses a decoding method used in a wireless communication system.
A method of digital communication, comprising receiving, by a second node, a signal including an output bit sequence e=[e0, e1, . . . , eE−1] sent by a first node; and determining, by the second node, an estimation of an input bit sequence c=[c0, c1, . . . , cK−1].
In one example, the output bit sequence e can be determined by determining by performing a polar transform with H components and a pre-transform; wherein the polar transform is based on H polar matrices G(N
In one example, the output bit sequence e can be determined by the first node by at least one of the following: a repetition, H component rate profiling, a first concatenation, a pre-transform, a segmentation, H component polar transform based on H polar matrices G(N
Here, K is the input length of the input bit sequence c; E is the output length of the output bit sequence e; H is the number of component polar matrices; W is the number of component interleaving; K, E, and H are positive integers; K<E and H<E; H is an integer greater than one; W is an integer not greater than H; for h=0, 1, . . . , H−1, the h-th component polar transform is based on the h-th component polar matrix G(N
This section discloses the parameters related in determining the output bit sequence e.
Embodiment 3 is based on the above embodiments.
The output bit sequence e is determined by the first node by at least one of the following:
For h=0, 1, . . . , H−1, the component polar matrix sizes Nh is the polar matrix size of the h-th component polar matrix G(N
In some embodiments, all H component polar matrix sizes N0, N1, . . . , NH−1 are the same, i.e., N0=N1= . . . =NH−1. A specific example with H=3 polar matrix sizes for an output length E=24 is N0=N1=N2=8.
In some embodiments, not all H component polar matrix sizes N0, N1, . . . , NH−1 are the same, i.e., there exists h≠k such that Nh≠Nk. A specific example with H=3 polar matrix sizes for an output length E=24 are N0=16, N1=4 and N2=4, wherein N0≠N1.
In some embodiments, all H component polar matrix sizes N0, N1, . . . , NH−1 are different, i.e., if h≠k, Nh≠Nk. A first specific example with H=2 polar matrix sizes for an output length E=24 are N0=16 and N1=8, wherein N0≠N1. A second specific example with H=3 polar matrix sizes for an output length E=26 is N0=16, N1=8, and N2=2, wherein N0≠N1, N0≠N2, and N1≠N2.
H Component Repetition Lengths K0, K1, . . . , KH−1
In some embodiments, at least one of the H component repetition lengths K0, K1, . . . , KH−1 is equal to the input length K. A first specific example with H=3 polar matrix sizes and K=6, there are K0=6, K1=3 and K2=1, wherein, K0=K=6. A second specific example with H=3 polar matrix sizes and K=6, there are K0=6, K1=6 and K2=1, wherein, K0=K1=K=6.
In some embodiments, all H component repetition lengths K0, K1, . . . , KH−1 are the same, i.e., K0=K1= . . . =KH−1. A specific example with H=3 polar matrix sizes, there are K0=K1=K2=2.
In some embodiments, not all H component repetition lengths K0, K1, . . . , KH−1 are the same, i.e., there exists h≠k such that Kh≠Kk. A specific example with H=3 polar matrix sizes, there are K0=6, K1=2 and K2=2, wherein K0≠K1.
In some embodiments, all H component repetition lengths K0, K1, . . . , KH−1 are different, i.e., if h≠k, Kh≠Kk. A specific example with H=3 polar matrix sizes, there are K0=6, K1=3 and K2=1, wherein K0≠K1, K0≠K2, and K1≠K2.
Component Repetition Index Sets R(0), R(1), . . . , R(H−1)
For h=0, 1, . . . , H−1, the h-th component repetition set R(h)={R0(h), R1(h), . . . , RK
In some embodiments, at least one of the H component repetition index sets R(0), R(1), . . . , R(H−1) is equal to a first-type integer set ZK={0, 1, 2, . . . , K−1}, wherein the first-type integer set ZK={0, 1, 2, . . . , K−1} comprises all non-negative integers smaller than K. In a specific example with K=6, E=24, H=2 polar matrix sizes N0=16 and N1=8, the H=2 component repetition index sets R(0) and R(1) are R(0)=Z6={0, 1, 2, 3, 4, 5} with K0=K=6 and R(1)={0, 1, 2} with K1=3, respectively.
In some embodiments, none of H component repetition index sets R(0), R(1), . . . , R(H−1) is equal to a first-type integer set ZK={0, 1, 2, . . . , K−1}, wherein the first-type integer set ZK={0, 1, 2, . . . , K−1} comprises all non-negative integers smaller than K.
In a specific example with K=6, E=24, H=3 polar matrix sizes N0=16, N1=4 and N2=4, the H=3 component repetition index sets are R(0)={0, 1, 2, 3, 4} with K0=5, R(1)={5, 0} with K1=2, and R(2)={1, 2} with K2=2, respectively, wherein R(0)≠Z6, R(1)≠Z6, and, R(2)≠Z6, wherein, Z6={0, 1, 2, 3, 4, 5}.
In some embodiments, for h=0, 1, . . . , H−2, the (h+1)-th component repetition index set R(h+1) is a subset of the h-th component repetition index set R(h)={R0(h), R1(h), . . . , RK
In some embodiments, for h, h′ being non-negative integers less than H and h not equal to h′, the intersection of the h-th component repetition index set R(h) and the h′-th component repetition index set R(h′) is an empty set, i.e., R(h)∩R(h′)=Φ={ }, wherein Φ denotes the empty set. In a specific example with K=6, E=24, H=3 polar matrix sizes N0=16, N1=4 and N2=4, the H=3 component repetition index sets are R(0)={0, 1} with K0=2, R(1)={2, 3} with K1=2, and R(2)={4, 5} with K1=2, respectively.
In some embodiments, there exists h and k being non-negative integers less than H and h not equal to k (h≠k) such that the intersection of the h-th component repetition index set R(h) and the k-th component repetition index set R(k) is not an empty set, i.e., R(h)∩(R(k)≠Φ, wherein, Φ={ } is the empty set.
In a first specific example with K=6, E=24, H=2 polar matrix sizes N0=16 and N1=8, the H=2 component repetition index sets R(0) and R(1) are R(0)=Z6={0, 1, 2, 3, 4, 5} with K0=K=6 and R(1)={0, 1, 2} with K1=3, respectively, wherein, R(0)∩(R(1)={0, 1, 2}≠{ }=Φ; wherein Φ denotes the empty set.
In a second specific example with K=6, E=24, H=3 polar matrix sizes N0=8, N1=8, and N2=8, the H=3 component repetition index sets R(0), R(1), R(2) are R(0)=Z6={0, 1, 2, 3, 4, 5} with K0=K=6, R(1)={0, 1, 2} with K1=3 and R(2)={4} with K2=1, respectively, wherein, R(0)∩R(1)={0, 1, 2}≠Φ and R(0)∩R(2)={4}≠Φ; wherein Φ denotes the empty set.
In a third specific example with K=6, E=26, H=3 polar matrix sizes N0=16, N1=8, and N2=2, the H=3 component repetition index sets R(0), R(1), R(2) are R(0)={0, 1, 2, 3, 4} with K0=5, R(1)={5, 0} with K1=2, and R(2)={4} with K2=1, respectively, wherein, R(0)∩R(1)={0}≠Φ and R(0)∩R(2)={4}≠Φ; wherein Φ denotes the empty set.
In some embodiments, all H component repetition index sets R(0), R(1), . . . , R(H−1) comprise an index k, wherein k is a non-negative integer. A specific example with H=3 component repetition index sets R(0), R(1), R(2) are R(0)={0, 1, 2, 3, 4} with K0=5, R(1)={5, 0, 2} with K1=2, and R(2)={4, 0} with K2=2, respectively, wherein H=3 component repetition index sets R(0), R(1), R(2) comprise an index k=0.
Component Data Bit Index Sets Q(0), Q(1), . . . , Q(H−1)
For h=0, 1, . . . , H−1, the h-th component data bit index set Q(h)={Q0(h), Q1(h), . . . , QK
In some embodiments, for some h, if k<k′, the k-th element Qk(h) in the h-th component data bit index set Q(h) is smaller than the k′-th element Qk′(h) in the h-th component data bit index set Q(h), i.e., the h-th component data bit index set Q(h) is sorted in ascending order according to index values with Q0<Q1< . . . <QK−2<QK−1. In some embodiments, for some h, if k<k′, the k-th element Qk(h) in the h-th component data bit index set Q(h) is greater than the k′-th element Qk′(h) in the h-th component data bit index set Q(h), i.e., the h-th component data bit index set Q(h) is sorted in descending order according to index values with Q0>Q1> . . . >QK−2>QK−1. In some embodiments, for some h, if k<k′, the reliability of the Qk(h)-th polarized sub-channel (denoted as W(Qk(h))) corresponding to the h-th component polar matrix G(N
In some embodiments, at least one of the H component data bit index set sizes K0, K1, . . . , KH−1 is equal to the input length K.
In a first specific example with K=6, E=24, H=2 polar matrix sizes N0=16 and N1=8, the H=2 component data bit index sets Q(0) and Q(1) are Q(0)={12, 7, 11, 13, 14, 15} with K0=K=6 and Q(1)={12, 7, 11} with K1=3, respectively, wherein, the 0-th component data bit index set Q(0)={12, 7, 11, 13, 14, 15} is corresponding to the 0-th component polar matrix G(N
In a second specific example with K=6, E=24, H=3 polar matrix sizes N0=8, N1=8, and N2=8, the H=3 component data bit index sets Q(0), Q(1), Q(2) are Q(0)={2, 4, 3, 5, 6, 7} with K0=K=6, Q(1)={2, 4, 5} with K1=3 and Q(2)={3} with K2=1, respectively. In a third specific example with K=6, E=26, H=3 polar matrix sizes N0=16, N1=8, and N2=2, the H=3 component repetition index sets Q(0), Q(1), Q(2) are Q(0)={7, 11, 13, 14, 15} with K0=5, Q(1)={6, 7} with K1=2, and Q(2)={1} with K2=1, respectively.
The first data bit index set Q={Q0, Q1, . . . , QK−1} has K elements, i.e., the size of the input data bit index set is |Q|=K, wherein K is the input length. The first data bit index set Q={Q0, Q1, . . . , QK−1} is a subset of a third-type integer set ZN
and the third-type integer set ZN
In a first specific example with K=6, Nm=16, and E=24, a first data bit index set is Q={12, 7, 11, 13, 14, 15}.
In a second specific example with K=6 and H=3 polar matrix sizes N0=8, N1=8 and N2=8, we have Nm=max(max(N0, N1), N2)=8, a data bit index set Q={2, 4, 3, 5, 6, 7}, and H=3 component data bit index set Q(0)={Q0(0), Q1(0), Q2(0), Q3(0), Q4(0), Q5(0)}=Q={2, 4, 3, 5, 6, 7}, Q(1)={Q0(1), Q1(1), Q2(1)}={2, 4, 3}, Q(2)={Q0(2)}={4}.
In a third specific example with K=6 and H=3 polar matrix sizes N0=16, N1=8 and N2=2, we have Nm=max(max(N0, N1), N2)=16, and a data bit index set Q={12, 7, 11, 13, 14, 15}.
In some embodiments, for k=0, 1, . . . , K−2, the element Qk in the first data bit index set Q is smaller than Qk+1, i.e., the first data bit index set Q is sorted in ascending order according to index values with Q0<Q1< . . . <QK−2<QK−1.
In some embodiments, for k=0, 1, . . . , K−2, the reliability of the Qk-th polarized sub-channel (denoted as W(Qk)) is smaller than the reliability of the Qk+1-th polarized sub-channel (denoted as W(Qk+1)), i.e., the first data bit index set Q is sorted in ascending order according to the polarized sub-channel reliability with W(Q0)<W(Q1)< . . . <W(QK−2)<W(QK−1).
In a first specific example with Nm=8 and K=4, a first data bit index set is Q={Q0, Q1, Q2, Q3}={3, 5, 6, 7} with Q0<Q1<Q2<Q3.
In a second specific example with Nm=32 and K=25, a first data bit index set is Q={Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24}={5, 9, 6, 17, 10, 18, 12, 20, 24, 7, 11, 19, 13, 14, 21, 26, 25, 22, 28, 15, 23, 31, 27, 29, 30} with polarized sub-channel reliability being W(Q0)<W(Q1)<W(Q2)<W(Q3)<W(Q4)<W(Q5) <W(Q6)<W(Q7)<W(Q8)<W(Q9)<W(Q10)<W(Q11)<W(Q12)<W(Q13)<W(Q14)<W(Q15)<W(Q16)<W(Q71)<W(Q18)<W(Q19)<W(Q20)<W(Q21)<W(Q22)<W(Q23)<W(Q24).
A Generator Polynomial g(D)
The generator polynomial g(D)=g0+g1·D+ . . . +gm·Dm can be any binary polynomial over GF(2), wherein h is the memory length of the generator polynomial g(D) or the degree of generator polynomial g(D). A generator polynomial g(D)=g0+g1·D+ . . . +gm·Dm has a corresponding generator bit sequence g=[g0, g1, . . . , gm] of length m+1. The generator polynomial g(D) and its corresponding generator bit sequence g are used interchangeably in this document.
In a first specific example with a memory length m=6, a generator polynomial g(D)=g0+g1·D + . . . +gm·Dm=g0+g1·D+g2·D2+g3·D3+g4·D4+g5·D5+g6·D6=1+D2+D3+D5+D6. In a second specific example with a memory length m=3, a generator polynomial g(D)=g0+g1·D+ . . . +gm·Dm=g0+g1·D+g2·D2+g3·D3=1+D+D3.
More specific examples for a generator polynomial g(D)=g0+g1·D+ . . . +gm·Dm are as follows:
wherein m is the memory length.
A Recursive Feedback Polynomial q(D)
The recursive feedback polynomial q(D)=q0+q1·D+ . . . +qm·Dm can be any binary polynomial over GF(2), wherein m is the memory length of the recursive feedback polynomial q(D) or the degree of the recursive feedback polynomial q(D). A recursive feedback polynomial q(D)=q0+q1·D+ . . . +qm·Dm has a corresponding recursive feedback bit sequence q=[q0, q1, . . . , qm] of length m+1. The recursive feedback polynomial q(D) and its corresponding recursive feedback bit sequence q are used interchangeably in this document.
In some embodiments, the value of q0 is a bit one “1” in the recursive feedback polynomial q(D).
In a first specific example with a memory length m=6, a recursive feedback polynomial is q(D)=q0+q1·D+ . . . +qm·Dm=q0+q1·D+q2·D2+q3·D3+q4·D4+q5·D5+q6·D6=1+D2+D4+D5+D6.
In a second specific example with a memory length m=3, a recursive feedback polynomial is q(D)=q0+q1·D+ . . . +qm·Dm=q0+q1·D+q2·D2+q3·D3=1+D2+D3.
Component Interleaver Patterns J(0), J(1), . . . , J(W−1)
For h=0, 1, . . . , W−1, the h-th component interleaver pattern J(h)=[J0(h), J1(h), . . . , JN
A first specific example with H=2, W=2, N0=16, N1=8, a 0-th component interleaver pattern J(0)=[J0(0), J1(0), . . . , JN
A second specific example with H=3, W=2, N0=N1=N2=8, a 0-th component interleaver pattern J(0)=[J0(0), J1(0), . . . , JN
A third specific example with H=3, W=3, N0=16, N1=8, and N2=2, a 0-th component interleaver pattern J(0)=[J0(0), J1(0), . . . , JN
A fourth specific example with H=3, W=1, N0=8, N1=16, and N2=2, a 2nd component interleaver pattern J(2)=[J0(2), J1(2), . . . , JN
In some embodiments, the first node performs a repetition by obtaining the input bit sequence c of length K and determining H component repetition output bit sequences c(0), c(1), c(2), . . . , c(H−1), wherein, for h=0, 1, 2, . . . , H−1, the h-th component repetition output bit sequence c(h)=[c0(h), c1(h), . . . , cK
In some embodiments, for h=0, 1, 2, . . . , H−1, the first node performs a component rate profiling by obtaining the h-th component repetition output bit sequences c(h)=[c0(h), c1(h), . . . , cK
In some embodiments, the first node performs a first concatenation by obtaining H component rate profiling output bit sequences v(0), v(1), v(2), . . . , v(H−1) and determining a concatenation output bit sequence y=[y0, y1, y2, . . . , YE−1] of length E, wherein, for h=0, 1, . . . , H−1, the h-th component rate profiling output bit sequence v(h)=[v0(h), v1(h), . . . , vN
In some embodiments, the first node performs a pre-transform by obtaining the concatenation output bit sequence y=[y0, y1, y2, . . . , YE−1] of length E and determining a pre-transform output bit sequence u=[u0, u1, u2, . . . , uE−1] of length E by at least one of the following: the generator polynomial g(D)=g0+g1·D+g2·D2+ . . . +gm·Dm over GF(2), the recursive feedback polynomial q(D)=q0+q1·D+q2·D2+ . . . +qm·Dm over GF(2), wherein, E is the length of the output bit sequence e=[e0, e1, e2, . . . , eE−1].
In some embodiments, the first node performs a segmentation by obtaining the pre-transform output bit sequence u=[u0, u1, u2, . . . , uE−1] of length E and determining H segmentation output bit sequences u(0), u(1), . . . , u(H−1) according to H component polar matrix sizes N0, N1, . . . , NH−1, wherein, H is the number of component polar matrices; for h=0, 1, . . . , H−1, the h-th segmentation output bit sequence u(h) is of length Nh, wherein Nh is the h-th component polar matrix size and E is the length of the output bit sequence e=[e0, e1, e2, . . . , eE−1].
In some embodiments, for h=0, 1, 2, . . . , H−1, the first node performs a component polar transform by obtaining the h-th segmentation output bit sequence u(h) of length Nh and determining an h-th component polar transform output bit sequence d(h)=[d0(h), d1(h), . . . , dN
Three examples are shown in
In some embodiments, the first node performs a second concatenation by obtaining the H component polar transform output bit sequences d(0), d(1), d(2), . . . , d(H−1) and determining the output bit sequence e=[e0, e1, . . . , eE−1] of length E, wherein, a specific example is shown in
In some embodiments, the number of interleaver patterns W is equal to the number of component polar matrices H and for h=0, 1, 2, . . . , H−1, the first node performs a component interleaving by obtaining the h-th component polar transform output bit sequence d(h)=[d0(h), d1(h), . . . , dN
In some embodiments, the number of interleaver patterns W is smaller than the number of component polar matrices H and for h=0, 1, 2, . . . , W−1, the first node performs a component interleaving by obtaining the h-th component polar transform output bit sequence d(h)=[d0(h), d1(h), . . . , dN
In some embodiments, the first node performs a component interleaving on W bit sequences of the H component polar transform output bit sequences d(0), d(1), d(2), . . . , d(H−1) to determine W component interleaving output bit sequences, wherein W is a non-negative integer not greater than H. In a first specific example with H=3 component polar transform output bit sequences d(0), d(1), d(2) and W=2, the first node performs a component interleaving on W=2 component polar transform output bit sequences d(0), d(2) to determine W=2 component interleaving output bit sequences d′(0), d′(2), wherein the 0-th component interleaving output bit sequence d′(0) is corresponding to the 0-th component polar transform output bit sequence d(0); the 2nd component interleaving output bit sequence d′(2) is corresponding to the 2nd component polar transform output bit sequence d(2).
In a second specific example with H=3 component polar transform output bit sequences d(0), d(1), d(2) and W=1, the first node performs a component interleaving on W=1 component polar transform output bit sequence d(0) to determine W=1 component interleaving output bit sequence d′(0), wherein the 1st component interleaving output bit sequence d′(0) is corresponding to the 1st component polar transform output bit sequence d(0).
This section discloses examples involving repetition.
Embodiment 4 is based on the above embodiments.
Here, the repetition input bit sequence can be an input bit sequence c=[c0, c1, . . . , cK−1] of length K; for h=0, 1, . . . , H−1, the h-th component repetition output bit sequence c(h)=[c0(h), c1(h), . . . , cK
In some embodiments, for h=0, 1, . . . , H−1, the repetition determines the h-th component repetition output bit sequence c(h) by setting the k-th bit ck(h) in the h-th component repetition output bit sequence c(h) to the bit with an index Rk(h) in the input bit sequence c=[c0, c1, . . . , cK−1], i.e., ck(h)=cR
In a first specific example with K=6, an input bit sequence c=[c0, c1, c2, c3, c4, c5], H=2 component repetition index sets R(0)={0, 1, 2, 3, 4, 5} with K0=6 and R(1)={0, 1, 2} with K1=3, the 0th component repetition output bit sequence c(0)=[c0(0), c1(0), c2(0), c3(0), c4(0), c5(0)]=[cR
In a second specific example with K=6, an input bit sequence c=[c0, c1, c2, c3, c4, c5], H=3 component repetition index sets R(0)={0, 1, 2, 3, 4, 5} with K0=6, R(1)={0, 1, 2} with K1=3 and R(2)={4} with K2=1, the 0th component repetition output bit sequence c(0)=[c0(0), c1(0), c2(0), c3(0), c4(0), c5(0)]=[cR
In some embodiment, the repetition comprises obtaining, by the first node, the input bit sequence c=[c0, c1, . . . , cK−1] of length K; and performing, by the first node, an rate profiling on the input bit sequence c=[c0, c1, . . . , cK−1] using the first data bit index set Q={Q0, Q1, . . . , QK−1} to obtain a repetition rate profile output bit sequence v′=[v′0, v′1, . . . , v′N−1] of length N as
In some embodiments, for h=0, 1, . . . , H−1, the repetition determines the h-th component repetition output bit sequence c(h) by setting the k-th bit ck(h) in the h-th component repetition output bit sequence c(h) to the bit with an index Qk in the repetition rate profile output bit sequence v′=[v′0, v′1, . . . , v′N−1], i.e., ck(h)=v′Q
In a first specific example with K=6, an input bit sequence c=[c0, c1, c2, c3, c4, c5], H=2 polar matrix sizes N0=16 and N1=8, a first data bit index set Q={12, 7, 11, 13, 14, 15}, K0=6, K1=3, we obtain a repetition rate profile output bit sequence v′=[v′0, v′1, . . . , v′N−1]=[v′0, v′1, v′2, v′3, v′4, v′5, v′6, v′7, v′8, v′9, v′10, v′11, v′12, v′13, v′14, v′15 ] of length Nm=max(N0, N1)=16, then we obtain the 0th component repetition output bit sequence c(0)=[c0(0), c1(0), c2(0), c3(0), c4(0), c5(0)]=[v′Q
In some embodiments, at least two of H repetition output bit sequences c(0), c(1), c(2), . . . , c(H−1) comprises the Qk-th bit v′Q
In some embodiments, at least two of H repetition output bit sequences c(0), c(1), c(2), . . . , c(H−1) comprises the k-th bit ck in the input bit sequence c=[c0, c1, . . . , cK−1] of length K. A specific example is all repetition output bit sequences c(0), c(1), c(H−1) comprises the 0-th bit c0 in the input bit sequence c=[c0, c1, . . . , cK−1] of length K, wherein a specific example is c0(0)=c0(1)= . . . =c0(H−2)=c0(H−1)==c0.
In some embodiments, at least two of H repetition output bit sequences c(0), c(1), c(2), . . . , c(H−1) are of the same length, i.e., there exists h≠k such that Kh=Kk, wherein for h=0, 1, . . . , H−1, Kh is the length of the h-th repetition output bit sequences c(h). A specific example with H=3, all repetition output bit sequences c(0), c(1), c(2) are of length K0=K1=K2=2.
In some embodiments, not all repetition output bit sequences c(0), c(1), c(2), . . . , c(H−1) are of the same length, i.e., there exists h≠k such that Kh≠Kk, wherein Kh is the length of the h-th repetition output bit sequence c(h) and Kk is the length of the k-th repetition output bit sequence c(k). A specific example with H=3, the 0-th repetition output bit sequence c(0) is of length K0=6 and the 1st repetition output bit sequence c(1) is of length K1=3, wherein K0≠K1.
In some embodiments, all repetition output bit sequences c(0), c(1), c(2), . . . , c(H−1) are of different lengths, i.e., if h≠k, Kh≠Kk, wherein Kh is the length of the h-th repetition output bit sequence c(h) and Kk is the length of the k-th repetition output bit sequence c(k). A specific example with H=3, the 0-th repetition output bit sequence c(0) is of length K0=6, the 1st repetition output bit sequence c(1) is of length K1=3, and the 2nd repetition output bit sequence c(2) is of length K2=1, wherein K0≠K1, K0≠K2, and K1≠K2.
This section discloses examples involving a component rate profiling.
Embodiment 5 is based on the above embodiments.
In some embodiments, for h=0, 1, . . . , H−1, the h-th component repetition output bit sequence c(h)=[c0(h), c1(h), . . . , cK
The component rate profiling determining an component rate profiling output bit sequence v=[u0, v1, . . . , vN−1] comprises obtaining, by the first node, a component rate profiling input bit sequence c′=[c′0, c′1, . . . , c′K−1]; and determining, by the first node, a component rate profiling output bit sequence v=[v0, v1, . . . , vN−1] by a component rate profiling using a component data bit index set Q′={Q′0, Q′1, . . . , Q′K′−1} of size K′; wherein, K′ is a component repetition length; N is the polar matrix size of a component polar matrix G(N).
In some embodiments, the component data bit index set Q′ is a subset of a fourth-type integer set ZN={0, 1, 2, . . . , N−2, N−1}, wherein, the fourth-type integer set ZN={0, 1, 2, . . . , N−2, N−1} comprises and only comprises all non-negative integers smaller than N. The component data bit index set Q′={Q′0, Q′1, . . . , Q′K′−1} has K′ non-negative elements Q′0, Q′1, . . . , Q′K−2, Q′K−1, i.e., the component data bit index set Q′is of size K′. In some embodiments, for k=0, 1, . . . , K′−2, the element Q′k in the component data bit index set Q′is smaller than Q′k+1, i.e., the component data bit index set Q′ is sorted in ascending order according to index values with Q′0<Q′1< . . . <Q′K′−2<Q′K′−1. In some embodiments, for k=0, 1, . . . , K′−2, the reliability of the Q′k-th polarized sub-channel (denoted as W(Q′k)) is smaller than the reliability of the Q′k+1-th polarized sub-channel (denoted as W(Q′k+1)), i.e., the component data bit index set Q′ is sorted in ascending order according to the polarized sub-channel reliability with W(Q′0)<W(Q′1)< . . . <W(Q′K′−2)<W(Q′K′−1). In some embodiments, for k=0, 1, . . . , K′−2, the element Q′k in the component data bit index set Q′ is greater than Q′k+1, i.e., the component data bit index set Q′ is sorted in descending order according to index values with Q′0>Q′1> . . . >Q′K′−2>Q′K−1. In some embodiments, for k=0, 1, . . . , K′−2, the reliability of the Q′k-th polarized sub-channel (denoted as W(Q′k)) is greater than the reliability of the Q′k+1-th polarized sub-channel (denoted as W(Q′k+1)), i.e., the component data bit index set Q′ is sorted in descending order according to the polarized sub-channel reliability with W(Q′0)>W(Q′1)> . . . >W(Q′K′−2)>W(Q′K′−1).
In a first specific example with N=8 and K′=4, a component data bit index set is Q′={Q′0, Q′1, Q′2, Q′3}={3, 5, 6, 7}. In a second specific example with N=32 and K′=25, a component data bit index set is Q′={Q′0, Q′1, Q′2, Q′3, Q′4, Q′5, Q′6, Q′7, Q′8, Q′9, Q′10, Q′11, Q′12, Q′13, Q′14, Q′15, Q′16, Q′17, Q′18, Q′19, Q′20, Q′21, Q′22, Q′23, Q′24}={5, 9, 6, 17, 10, 18, 12, 20, 24, 7, 11, 19, 13, 14, 21, 26, 25, 22, 28, 15, 23, 31, 27, 29, 30} with polarized sub-channel reliability with W(Q′0)<W(Q′1)<W(Q′2)<W(Q′3)<W(Q′4)<W(Q′5)<W(Q′6)<W(Q′7)<W(Q′8)<W(Q′9) <W(Q′10)<W(Q′11)<W(Q′12)<W(Q′13)<W(Q′14)<W(Q′15)<W(Q′16)<W(Q′17)<W(Q′18)<W(Q′19)<W(Q′20)<W(Q′21)<W(Q′22)<W(Q′23)<W(Q′24). In a third specific example with N=8 and K′=4, a component data bit index set is Q′={Q′0, Q′1, Q′2, Q′3}={7, 6, 5, 3}.
In some embodiments, the component rate profiling determines the component rate profiling output bit sequence v=[v0, v1, . . . , vN−1] corresponding to the component rate profiling input bit sequence c′=[c′0, c′1, . . . , c′K′−1] according to the component data bit index set Q′ is as follows.
wherein, a specific example pseudo-code for the rate profiling is as follows.
In some embodiments, for an index i belonging to the component data bit index set Q′, the bit vi in the component rate profiling output bit sequence v is set to a bit in the component rate profiling input bit sequence c′.
A first specific example with N=8, K′=3 and a component data bit index set Q′={5, 6, 7}, a component rate profiling input bit sequence c′=[c′0, c′1, c′2], the bits v5, v6, v7 with indices belonging to the component data bit index set Q′={5, 6, 7} in a component rate profiling output bit sequence v=[v0, v1, v2, v3, v4, v5, v6, v7] is set as v5=c′0, v6=c′1, and v7=c′2.
A second specific example with N=16, K′=6 and a component data bit index set Q′={12, 7, 11, 13, 14, 15}, a component rate profiling input bit sequence c′=[c′0, c′1, c′2, c′3, c′4, c′5], the bits v12, v7, v11, v13, v14, v15 with indices belonging to the data bit index set Q′={12, 7, 11, 13, 14, 15} in a component rate profiling output bit sequence v=[v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15] is set as v12=c′0, v7=c′1, v11=c′2, v13=c′3, v14=c′4, and v15=c′5.
A third specific example is given as
In some embodiments, for a index i not belonging to the component data bit index set Q′, the bit vi in the component rate profiling output bit sequence v is equal to 0.
A first specific example with N=8, K′=3 and Q′={5, 6, 7}, the bits v0, v1, v2, v3, v4 with indices not belonging to the component data bit index set Q′={5, 6, 7} in a component rate profiling output bit sequence v=[v0, v1, v2, v3, v4, v5, v6, v7] is set as v0=0, v1=0, v2=0, v3=0, and v4=0.
A second specific example with N=16, K′=6 and Q′={7, 11, 12, 13, 14, 15}, the bits v0, v1, v2, v3, v4, v5, v6, v8, v9, v10 with indices not belonging to the component data bit index set Q′={7, 11, 12, 13, 14, 15} in a component rate profiling output bit sequence v=[v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15] is set as v0=0, v1=0, v2=0, v3=0, v4=0, v5=0, v6=0, v8=0, v9=0, and v10=0.
A third specific example is given as
In some embodiments, the component rate profiling output bit sequence v is the multiplexing of the component rate profiling input bit sequence c′ and an all-zero sequence of length N−K′, wherein N is the polar matrix size and K′ is the component rate profiling input bit sequence length.
A first specific example with N=8 and K′=3 is a component rate profiling input bit sequence c′=[c′0, c′1, c′2] and an all-zero sequence of length N−K′=8−3=5, then a component rate profiling output bit sequence v=[v0, v1, v2, v3, v4, v5, v6, v7]=[0, 0, 0, 0, 0, c0, c1, c2].
A second specific example with N=16, K′=6, a component rate profiling input bit sequence c′=[c′0, c′1, c′2, c′3, c′4, c′5] and an all-zero sequence of length N−K′=16−4=12, then a component rate profiling output bit sequence v=[v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15]=[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, c0, 0, c1, c2, c3] is determined.
This section discloses examples involving a first concatenation.
Embodiment 6 is based on the above embodiments. The input of a concatenation operation can be based on the input sequence c.
In some examples, the concatenation block can be connected with one or more component rate profile block.
In some embodiments, the H component rate profiling output bit sequences v(0), v(1), . . . , v(H−1) are input to a first concatenation to determine a concatenation output bit sequence y=[y0, y1, y2, . . . , yE−1] of length E, wherein, for h=0, 1, . . . , H−1, Nh is the length of the h-th component rate profiling output bit sequence v(h)=[v0(h), v1(h), . . . , vN
Examples of systems involving a first concatenation block are given in
In some embodiments, the first concatenation comprises obtaining, by the first node, H component concatenation input bit sequences v(0), v(1), . . . , v(H−1); and determining, by the first node, a concatenation output bit sequence y=[y0, y1, y2, . . . , yE−1] as y=[v(0), v(1), . . . , v(H−1)]=[v0(0), v1(0), . . . , vN
Here, E is the length of the output bit sequence e=[e0, e1, e2, . . . , eE−1]; for h=0, 1, . . . , H−1, the h-th component concatenation input bit sequence v(h)=[v0(h), v1(h), . . . , vN
The purpose of the concatenation block is to combine the multiple input sequences to generate an output sequence, which can be used as input for other blocks within a system.
In some example, the first concatenation may comprise obtaining, by the first node, H component concatenation input bit sequences v(0), v(1), . . . , v(H−1); and determining, by the first node, a concatenation output bit sequence y=[y0, y1, y2, . . . , yE−1] as
Here, E is the length of the output bit sequence e=[e0, e1, e2, . . . , eE−1]; for h=0, 1, . . . , H−1, the h-th component concatenation input bit sequence v(h)=[v0(h), v1(h), . . . , vN
This section discloses examples related to pre-transform.
Embodiment 7 is based on the above embodiments.
The input of a pre-transform can be based on the input sequence.
In some examples, a pre-transform block is connected with a concatenation block.
In some embodiments, the concatenation output bit sequence y=[y0, y1, y2, . . . , YE−1] of length E is input to a pre-transform to determine a pre-transform output bit sequence u=[u0, u1, u2, . . . , uE−1] of length E by at least one of the following: the generator polynomial g(D)=g0+g1·D+g2·D2+ . . . +gm·Dm over GF(2), the recursive feedback polynomial q(D)=q0+q1·D+q2·D2+ . . . +qm·Dm over GF(2).
A pre-transform operation can be conducted based on either a generator polynomial or a recursive feedback polynomial.
In some embodiments, the pre-transform comprises obtaining, by the first node, a pre-transform input bit sequence of length N, and determining, by the first node, a pre-transform output bit sequence u=[u0, u1, . . . , uN−1] by using at least one of the following: the generator polynomial g(D)=g0+g1·D+ . . . +gm·Dm over GF(2), the recursive feedback polynomial q(D)=q0+q1·D+ . . . +qm·Dm .
In the above example, N can be any positive integer; m is a memory length; specific examples are given in
(Pre-Transform Using a Generator Polynomial g(D)
In some embodiments, the pre-transform determines the pre-transform output bit sequence u corresponding to the pre-transform input bit sequence y=[y0, y1, y2, . . . , yE−1] of length E according to a generator polynomial g(D)=g0+g1·D+g2·D+ . . . +gm−1·D+gm·D, wherein m is called a memory length of the generator polynomial g(D). The generator polynomial g(D)=g0+g1·D+ . . . +gm−1·Dm−1+gm·Dm can be any binary polynomial over GF(2), wherein m is the polynomial degree or the memory length. In a specific example with a memory length m=6, a generator polynomial is g(D)=g0+g1·D+g2·D2+g3·D3+g4·4D+g5·D5+g6·D6=1+0·D+1·D2+1·D3+0·D4+1·D5+1·D6=1+D2+D3+D5+D6. In another specific example with a memory length m=3, a generator polynomial is g(D)=g0+g1·D+g2·D2+g3·D3=1+1·D+0·D2+1·D3=1+D+D3.
wherein the summation and the multiplication is over GF(2); the bit yi−k=0 for i<k; gk is a coefficient of the term with degree K in the generator polynomial g(D)=g0+g1·D+ . . . +gm−1·Dm−1+gm·Dm over GF(2); a specific pseudo code is as follows.
(Pre-Transform Using a Recursive Feedback Polynomial q(D))
In some embodiments, the pre-transform determines the pre-transform output bit sequence u corresponding to the pre-transform input bit sequence y according to a recursive feedback polynomial q(D)=q0+q1·D+q2·D+ . . . +qm−1·D+qm·D, wherein m is called a memory length of the recursive feedback polynomial q(D).
The feedback polynomial q(D)=q0+q1·D+ . . . +qm−1·Dm−1+qm·Dm is a binary polynomial with the zero-degree coefficient q0 being 1 and other coefficients q1, . . . , qm being any binary values over GF(2), wherein m is a memory length. In a specific example with a memory length m=6, a feedback polynomial is q(D)=q0+q1·D+q2·D2+q3·D3+q4·D4+q5·D5+q6·D6=1+0·D+1·D2 +0·D3+1·D4+1·D5+1·D6=1+D2+D4+D5+D6. In another specific example with a memory length m=3, a feedback polynomial is q(D)=q0+q1·D+q2·D2+q3·D3=1+0·D+1·D2+1·D3=1+D2+D3.
(Pre-Transform Using Both a Generator Polynomial g(D) and a Recursive Feedback Polynomial q(D)
In some embodiments, the pre-transform determines the pre-transform output bit sequence u corresponding to the pre-transform input bit sequence y according to both a generator polynomial g(D)=g0+g1·D+ . . . +gm−1·Dm−1+gm·D and a recursive feedback polynomial q(D)=q0+q1·D+ . . . +qm−1·Dm−1+qm·Dm, wherein m is called a memory length for both the generator polynomial g(D) and the recursive feedback polynomial q(D).
The generator polynomial g(D)=g0+g1·D+ . . . +gm−1·Dm−1+gm·Dm can be any binary polynomial over GF(2), wherein m is the polynomial degree or the memory length. In a specific example with a memory length m=6, a generator polynomial is g(D)=g0+g1·D+g2·D2+g3·D3+g4·D4+g5·D5+g6·D6=1+0·D+1·D2+1·D3+0·D4+1·D5+1·D6=1+D2+D3+D5+D6. In another specific example with a memory length m=3, a generator polynomial is g(D)=g0+g1·D+g2·D2+g3·D3=1+1·D+0·D2+1·D3=1+D+D3. The recursive feedback polynomial q(D)=q0+q1·D+ . . . +qm−1·Dm−1+qm·Dm is a binary polynomial with the zero-degree coefficient q0 being 1 and other coefficients q1, . . . , qm being any binary values over GF(2), wherein m is the memory length. In a specific example with a memory length m=6, a recursive feedback polynomial is q(D)=q0+q1·D+q2·D2+q3·D3+q4·D4+q5·D5+q6·D6=1+0·D+1·D2+0·D3+1·D4+1·D5+1·D6=1+D2+D4+D5+D6. In another specific example with a memory length m=3, a recursive feedback polynomial is q(D)=q0+q1·D+q2·D2+q3·D3=1+0·D+1·D2+1·D3=1+D2+D3.
As shown in
A specific pseudo code for the above steps is as follows.
This section discloses examples related to segmentation.
Embodiment 8 is based on all of the above embodiments.
In some examples, the input of a segmentation block is based on the input sequence c.
In some examples, a segmentation block can relate to a pre-transform block.
In some embodiments, the pre-transform output bit sequence u=[u0, u1, u2, . . . , uE−1] of length E is input to a segmentation to determine H segmentation output bit sequences u(0), u(1), . . . u(H−1) by H component polar matrix sizes N0, N1, . . . , NH−1, wherein, H is the number of component polar matrices; for h=0, 1, . . . , H−1, the h-th segmentation output bit sequence u(h) is of length Nh, wherein Nh is the h-th component polar matrix size and E is the length of the pre-transform output bit sequence u and E=N0+N1+ . . . +NH−1.
In some examples, the segmentation operation comprises obtaining, by the first node, a segmentation input bit sequence of length E; and determining, by the first node, H segmentation output bit sequences u(0), u(1), . . . u(H−1) by H component polar matrix sizes N0, N1, . . . , NH−1 as below:
In the above example, the segmentation input bit sequence of length E is the pre-transform output bit sequence u=[u0, u1, u2, . . . , uE−1] of length E; for h=0, 1, . . . , H−1, the h-th segmentation output bit sequence u (h) is of length equal to the h-th component polar matrix size Nh. In some embodiments, the segmentation input bit sequence of length E consists of the H segmentation output bit sequences u(0), u(1), . . . u(H−1).
In some examples, a segmentation block can be connected to one or more component polar transform blocks.
Examples are given in
This section discloses examples involving polar transforms.
Embodiment 9 is based on all the above embodiments.
An encoding or decoding system may contains multiple component polar transforms.
The input of the component polar transforms can be based on the input sequence c.
In some examples, a component polar transform block can be connected with a segmentation block.
In one example, for h=0, 1, 2, . . . , H−1, the h-th segmentation output bit sequences u(h) of length Nh is input to a component polar transform to determine an h-th component polar transform output bit sequence d(h)=[d0(h), d1(h), . . . , dN
In some examples, a component polar transform block can be connected with a component interleaving block. In one example, the input of a component interleaving block is based on the output of a component polar transform block.
Some examples are shown in
This section discloses examples involving output bit sequence comprises component polar transform output bit sequences.
Embodiment 10 is based on the above embodiments.
In one example, the output bit sequence e=[e0, e1, . . . , eE−1] comprises H component polar transform output bit sequences d(0), d(1), . . . , d(H−1), wherein, for h=0, 1, . . . , H−1, the h-th component polar transform output bit sequence d(h)=[d0(h), d1(h), . . . , dN
In another example, the output bit sequence e=[e0, e1, . . . , eE−1] is a second concatenation of H component polar coding output bit sequences d(0), d(1), . . . , d(H−1) as follows: [e0, e1, e2, . . . , eE−1]=[d(0), d(1), . . . , d(H−1)]=[d0(0), d1(0), . . . dN
In yet another example, the output bit sequence e=[e0, e1, . . . , eE−1] is a second concatenation of H component polar coding output bit sequences d(0), d(1), . . . , d(H−1) as follows:
This section discloses example systems comprising component interleaving.
Embodiment 11 is based all of the above Embodiments.
A component interleaving operation can be achieved based on an interleaver pattern J.
In some examples, for h=0, 1, . . . , W−1, the h-th component polar transform output bit sequence d(h)=[d0(h), d1(h), . . . , dN
In some embodiments, the h-th component interleaver pattern J(h) is determined using the method in Example 1 with a polar matrix size N=Nh, wherein Nh is the h-th component polar matrix size. In some embodiments, the h-th component interleaver pattern J(h)is determined using the method in Example 2 with a polar matrix size N=Nh, wherein Nh is the h-th component polar matrix size.
In another example, a component interleaving determined by an component interleaver pattern J=[J0, J1, . . . , JN−2, JN−1] of length N comprises obtaining, by the first node, a component interleaving input bit sequence d=[d0, d1, . . . , dN−1] of length N; and determining, by the first node, a component interleaving output bit sequence d′=[d′0, d′1, . . . , d′N−1] of length N as d′i=dJ
In other words, the i-th bit of the interleaving output bit sequence d′ is equal to the Ji-th bit of the interleaving input bit sequence d=[d0, d1, . . . , dN−1], wherein, the component interleaver pattern J can be any permutation of the integer sequence [0, 1, 2, . . . , N−2, N−1].
Several examples are discussed below to indicate the interleaving process mentioned above.
Example 1: A first specific example of a component interleaver pattern J=[J0, J1, . . . , JN−2, JN−1] is determined as by a polar matrix size N and a sub-block interleaver pattern π=[π0, π1, π2, π3, π4, π5, π6, π7, π8, π9, π10, π11, π12, π13, π14, π15, π16, π17, π18, π19, π20, π21, π22, π23, π24, π25, π26, π27, π28, π29, π30, π31]=[0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31] as follows.
Example 2: A second specific example of an interleaver pattern J=[J0, J1, . . . , JN−2, JN−1] is that the relationship between the index i and the i-th element Ji in the interleaver pattern J satisfies the following quadratic form:
J
i=mod(f1·i+f2·i2, N)
where some examples of parameters f1 and f2 depending on a polar matrix size N are summarized in TABLE 1.
Example 3: A third example of a component interleaver pattern J=[J0, J1, . . . , JN−2, JN−1] with N=8 is J=[J0, J1, J2, J3, J4, J5, J6, J7]=[5, 4, 7, 1, 6, 0, 2, 3].
This section discloses examples of output bit sequences include component interleaving output bit sequences.
Embodiment 12 is based on all the Embodiments disclosed above.
In some embodiments, the output bit sequence e=[e0, e1, . . . , eE−1] comprises W component interleaving output bit sequences d′(0), d′(1), . . . , d′(W−1) and H−W component polar transform output bit sequences d(W), d(W+1), . . . , d(H−1), wherein, for h=0, 1, . . . , W−1, the h-th component interleaving output bit sequence d′(h)=[d′0(h), d′1(h), . . . , d′N
In some embodiments, the output bit sequence e=[e0, e1, . . . , eE−1] is a second concatenation of W=H component interleaving output bit sequences d′(0), d′(1), . . . , d′(H−1) as follows:
[e0, e1, e2, . . . , eE−1]=[d′(0), d′(1), . . . , d′(H−1)]=[d′0(0), d′1(0), . . . d′N
In some embodiments, the output bit sequence e=[e0, e1, . . . , eE−1] is a second concatenation of W=H component output bit sequences d′(0), d′(1), . . . , d′(H−1) as follows:
In some examples, the output bit sequence e=[e0, e1, . . . , eE−1] is a second concatenation of W component interleaving output bit sequences d′(0), d′(1), . . . , d′(W−1) and H−W component polar transform output bit sequences d(W), d(W+1), . . . , d(H−1) as follows:
[e0, e1, e2, . . . , eE−1]=[d′(0), d′(1), . . . , d′(W−1), d(W), d(W+1), . . . , d(H−1)]=[d′0(0), . . . d′N
In some embodiments, the output bit sequence e=[e0, e1, . . . , eE−1] is a second concatenation of W component interleaving output bit sequences d′(0), d′(1), . . . , d′(W−1) and H−W component polar transform output bit sequences d(W), d(W+1), . . . , d(H−1) as follows:
The implementations as discussed above will apply to a network communication.
Various preferred embodiments and additional features of the above-described methods of
In some embodiments, the repetition operation comprising: obtaining, by the first node, a repetition input bit sequence; and determining, by the first node, H component repetition output bit sequences c(0), c(1), . . . , c(H−1) based on at least one of: 1) a length list (K0, K1, . . . , KH−1), wherein Ki indicating the length of c(i) or 2) a repetition index list (R(0), R(1), . . . , R(H−1)). In some embodiments, at least one of the H component repetition output bit sequences c(0), c(1), . . . , c(H−1) has a length equal to the length of the input bit sequence. In some embodiments, none of the H component repetition output bit sequences c(0), c(1), . . . , c(H−1) has a length equal to the length of the input bit sequence. In some embodiments, at least one of the H component repetition output bit sequences c(0), c(1), . . . , c(H−1) is equal to the input bit sequence. In some embodiments, at least one element Ki in the length list (K0, K1, . . . , KH−1) is equal to K, wherein K is the length of the input bit sequence. In some embodiments, an element R(i) in the repetition index list (R(0), R(1), . . . , R(H−1)) is an integer set. In some embodiments, at least one element R(i) in the repetition index list (R(0), R(1), . . . , R(H−1)) is equal to a first-type integer set ZK={0, 1, 2, . . . , K−1}, wherein the first-type integer set ZK={0, 1, 2, . . . , K−1} comprises all non-negative integers smaller than K and K is the length of the input bit sequence. In some embodiments, for h=0, 1, . . . , H−2, R(h+1) is a subset of R(h). In some embodiments, at least two of the H component repetition output bit sequences share at least one common element. In some embodiments, c(h)=[c0(h), c1(h), . . . , cK
In some embodiments, at least two of the H component repetition output bit sequences c(i) and c(j) comprise matching sub-sequences generated based on the input bit sequence. In one example, an input bit sequence c=[c0, c1, c2, c3, c4, c5, c6, c7, c8], c(i)=[c0, c1, c7, c3] and c(j)=[c3, c2, c7, c5]. Here, c(i) and c(j) have matching subsequences [c7, c3] and [c3, c7] accordingly. Both matching sub-sequences are generated based on the input sequence c, i.e., the elements c3 and c7 are in the input sequence c. Also, the two sub-sequences [c7, c3] and [c3, c7] have a matching relationship, e.g., the third and fourth elements in c(i) (c7 and c3) determine the third and first elements (c7 and c3) in c(j) . The two matching subsequences do not need to be in the same order with each other. Also, the elements in a matching subsequence do not need to be in consecutive positions in c(i) or c(j).
In some embodiments, the output bit sequence is determined by further performing a rate profile operation, wherein the input of the rate profile operation is based on the input bit sequence. In some embodiments, the rate profile operation is performed on the input bit sequence c=[c0, c1, . . . , cK−1] using a first data bit index set Q={Q0, Q1, . . . , QK−1} to obtain a repetition rate profile output bit sequence v′=[v′0, v′1, . . . , v′N−1].
In some embodiments, the output bit sequence is determined by further performing a repetition operation, wherein the repetition operation comprises: determining, by the first node, H component repetition output bit sequences c(0), c(1), . . . , c(H−1) based on the repetition rate profile output bit sequence v′=[v′0, v′1, . . . , v′N−1] by at least one of: 1) a length list (K0, K1, . . . , KH−1), wherein Ki indicating the length of c(i) or 2) the first data bit index set Q={Q0, Q1, . . . , QK−1}. In some embodiments, at least one of the H component repetition output bit sequences c(0), c(1), . . . , c(H−1) has a length equal to the length of the input bit sequence. In some embodiments, none of the H component repetition output bit sequences c(0), c(1), . . . , c(H−1) has a length equal to the length of the input bit sequence. In some embodiments, at least one of the H component repetition output bit sequences c(0), c(1), . . . , c(H−1) is equal to the input bit sequence. In some embodiments, at least one element Ki in the length list (K0, K1, . . . , KH−1) is equal to K, wherein K is the length of the input bit sequence. In some embodiments, the first data bit index set Q={Q0, Q1, . . . , QK−1} is sorted according to index values or reliability of polarized sub-channels. In some embodiments, at least two of the H component repetition output bit sequences share at least one common element. In some embodiments, c(h)=[c0(h), c1(h), . . . , cK
In some embodiments, at least two of the H component repetition output bit sequences c(i) and c(j) comprise matching sub-sequences in the repetition rate profile output bit sequence v′=[v′0, v′1, . . . , v′N−1], where N is an integer larger than 1. In one example, a repetition rate profile output bit sequence v′=[v′0, v′1, v′2, v′3, v′4, v′5, v′6, Y′7], c(i)=[v′0, v′1, v′2] and c(j)=[v′2, v′1, v′4]. Here, c(i) and c(j) have matching subsequences [v′1, v′2] and [v′2, v′1] accordingly. Both matching subsequences are generated based on the repetition rate profile output bit sequence v′, i.e., the elements v′1 and v′2 are in the repetition rate profile output bit sequence v′. Also, the two subsequences [v′1, v′2] and [v′2, v′1] have a matching relationship, e.g., the second and third elements in c(i) (v′1 and v′2) map to the second and first elements (v′1 and v′2) in c(j). The two matching subsequences do not need to be in the same order with each other. Also, the elements in a matching subsequence do not need to be in consecutive positions in c(i) or c(j).
In some embodiments, the rate profile operation is performed with H components. In some embodiments, the h-th component of the rate profile operation is performed based on a component data bit set Q(h)={Q0(h), Q1(h), Q2(h), . . . , QK
In some embodiments, the above introduced methods further comprising performing a first concatenation operation, wherein the input of the first concatenation operation is based on the input sequence. In some embodiments, the first concatenation operation generates an intermediate output sequence having E bits. In some embodiments, the first concatenation operation is performed on a first H components bit sequences generated based on the input sequence.
In some embodiments, the above introduced methods further comprising performing a second concatenation operation, wherein the input of the second concatenation operation is based on the input sequence. In some embodiments, a second concatenation operation is performed on a second H components bit sequences generated based on the input sequence.
In some embodiments, the pre-transform generates an intermediate bit sequence having E bits. In some embodiments, a bit of the intermediate bit sequence is determined by a convolution bit sequence or a convolution polynomial. In some embodiments, the convolution bit sequence comprises a generator bit sequence g=[g0, g1, . . . , gm], or a recursive feedback bit sequence q=[q0, q1, . . . , qm], wherein m is a positive integer. In some embodiments, the convolution polynomial comprises a generator polynomial g(D)=g0+g1·D+ . . . +gm−1·Dm−1+gm·Dm, or a recursive feedback polynomial q(D)=q0+q1·D+ . . . +qm−1·Dm−1+qm·Dm, wherein m is a positive integer. In some embodiments, the output bit sequence is determined by performing a segmentation operation, wherein the input of the segmentation operation is based on the input bit sequence.
In some embodiments, the output bit sequence is determined further by performing an interleaving operation, wherein the input of the interleaving operation is based on the input bit sequence. In some embodiments, the interleaving operation is performed with W components, wherein W is an integer less than or equal to H. In some embodiments, the interleaving operation of any of the W components is determined by an interleaving pattern J(h)=[J0(h), J1(h), . . . , JN
It will be appreciated that the present document discloses methods and apparatus related to rate matching schemes applying to polar coding, PAC coding, or other pre-transformed polar coding. In 5G mobile communications standard of 3GPP, low-density parity-check (LDPC) codes are used for data transmission. However, LDPC has certain drawbacks compared to polar codes in short payload size (also called transport block size (TBS)). Alternatively, PAC codes can achieve finite-length bounds in moderate decoding complexity. PAC codes have code lengths with power of 2 (N=2n with positive integer n) as polar codes. However, to efficiently transmitting a payload (or transport block (TB)) in different wireless channel environments, it does not always have a code length of N=2n in time and frequency resources allocated by a base station (BS). Therefore, rate matching schemes are needed for applying PAC codes in wireless communications.
The disclosed and other embodiments, modules and the functional operations described in this document can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this document and their structural equivalents, or in combinations of one or more of them. The disclosed and other embodiments can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more of them. The term “data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them. A propagated signal is an artificially generated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus.
A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
The processes and logic flows described in this document can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).
Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.
While this document contains many specifics, these should not be construed as limitations on the scope of an invention that is claimed or of what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features that are described in this document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or a variation of a subcombination. Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results.
Only a few examples and implementations are disclosed. Variations, modifications, and enhancements to the described examples and implementations and other implementations can be made based on what is disclosed.
This patent document is a continuation of and claims benefit of priority to International Patent Application No. PCT/CN2022/129016, filed on Nov. 1, 2022. The entire content of the before-mentioned patent application is incorporated by reference as part of the disclosure of this application.
Number | Date | Country | |
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Parent | PCT/CN2022/129016 | Nov 2022 | WO |
Child | 18933200 | US |