This patent document is directed to digital communications.
Mobile communication technologies are moving the world toward an increasingly connected and networked society. The rapid growth of mobile communications and advances in technology have led to greater demand for capacity and connectivity. Other aspects, such as energy consumption, device cost, spectral efficiency, and latency are also important to meeting the needs of various communication scenarios. Various techniques, including new ways to provide higher quality of service, longer battery life, and improved performance are being discussed.
This patent document describes, among other things, techniques that related to Polarization-Adjusted Convolutional (PAC) coding with variable lengths are disclosed.
In one example aspect, a method for digital communication includes determining, by a first node, an output bit sequence having E bits based on an input bit sequence having K bits. The output bit sequence is determined based on a transform that is applied prior to applying a Polar transform having a size of N. The transform is based on at least one index set that is a subset of a set of bit indices. The set of bit indices comprises all non-negative integers that are less than N and wherein K<N and K<E. The method also includes transmitting, by the first node, a signal including the output bit sequence to a second node.
In another example aspect, a method for digital communication includes receiving, by a second node, a signal including an output bit sequence having E bits from a first node. The method also includes determining, by the second node, an input bit sequence having K bits by decoding the output bit sequence included in the signal. The input bit sequence is determined based on a transform that is applied after applying an inverse Polar transform having a size of N. The transform is based on at least one index set that is a subset of a set of bit indices. The set of bit indices comprises all non-negative integers that are less than N and wherein K<N and K<E.
In another example aspect, a communication apparatus is disclosed. The apparatus includes a processor that is configured to implement an above-described method.
In yet another example aspect, a computer-program storage medium is disclosed. The computer-program storage medium includes code stored thereon. The code, when executed by a processor, causes the processor to implement a described method.
These, and other, aspects are described in the present document.
In the Fifth generation (5G) mobile communications standard of the Third Generation Partnership Project (3GPP), low-density parity-check (LDPC) codes are used for data transmission. However, LDPC codes does not perform as well as polar codes in short payload size (also referred to a transport block size, TBS). Also, LDPC codes have high error floors (e.g., at a block error rate, BLER, of 0.0001). To fulfill the future ultra-reliable low latency communication (URLLC), there is a need for more powerful channel coding.
Polarization-Adjusted Convolutional (PAC) codes can achieve finite-length bounds in moderate decoding complexity. As a result, PAC codes have code lengths of N as polar codes, where N=2n and n is a positive integer. However, the size of a payload, or a transport block (TB), in different wireless channel environments does not always have a code length of N=2n in time and frequency resources allocated by a base station (BS). Rate matching schemes are thus needed for applying PAC codes in wireless communications to efficiently transmit the payload. This patent document discloses techniques that can be implemented in various embodiments to enable variable lengths of PAC coding so as to adapt to the different payload sizes in wireless communications to improve efficiency.
Section headings below are used in the present document only to improve readability and do not limit scope of the disclosed embodiments and techniques in each section to only that section. Certain features are described using the example of 5G wireless protocol. However, applicability of the disclosed techniques is not limited to only 5G wireless systems.
GF(2) denotes the Galois field of size 2 with two elements “0” and “1”.
br(i) denotes the bit-reversal function.
floor(x) denotes the largest integer not greater than x.
min(x, y) denotes the minimum value between x and y,
mod(x, y) denotes the remainder of x divided by y. For example, mod(5, 3)=2 and mod(3, 5)=3.
Xi,j denotes the element in the i-th row and j-th column of a matrix X, where an boldface capital letter is used to represent a matrix.
[x0, x1, . . . , xY-1] denotes a sequence (or a vector) of length Y containing elements x0, x1, . . . , xY-1.
{x0, x1, . . . , xY-1} denotes a set with Y distinct elements x0, x1, . . . , xY-1, for any i≠j, xi≠xj.
<x0, x1, . . . , xY-1> denotes an ordered set with Y distinct elements x0, x1, . . . , xY-1, for any i≠j, xi≠xj. Let X=<x0, x1, . . . , xY-1>, X(i) denotes the i-th element xi in the ordered set X.
For a set X, |X| denotes the set size (the number of elements in the set X).
ZN={0, 1, . . . , N−2, N−1} denotes the integer set containing all non-negative integers smaller than N.
A matrix with Yr rows and Yc columns is called a Yr-by-Yc matrix.
An upper triangular matrix X with Yr rows and Yc is such that an element Xi,j in the i-th row and j-th column of the matrix X is 0 for any j<i with i being non-negative integers smaller than Yr and j being non-negative integers smaller than Yc, where Yr and Yc are positive integers.
Indices for sequences, vectors, or matrices are starting from zero.
Additional notations are listed in Table 1 below.
In the 3GPP 5G standard, polar codes are used in control channel transmissions.
Operation 110: Adding frozen bits. The adding-frozen-bits operation 110 combines N-K zero bits with the input bit sequence c to form a polar transform input sequence u=[u0, u1, . . . , uN-2, uN-1] of length N according to the data bit index set Q. The polar transform input sequence u is determined by the input bit sequence c, the data bit index set Q, and the polar matrix size N as follows.
Operation 120: Polar transform. The polar transform operation 120 converts a first length-N bit sequence into a second length-N bit sequence by multiplying the first length-N bit sequence and the polar matrix G(N) over GF(2). A polar transform output bit sequence d=[d0, d1, . . . , dN-2, dN-1] of length N is determined by the polar transform input sequence u and the polar matrix G(N) as d=u·G(N), where the vector-matrix multiplication is over GF(2).
Operation 130: Rate matching. The rate matching operation of polar coding in 5G includes two operations: sub-block interleaving and bit selection.
(1) Sub-block interleaving: An interleaving output bit sequence d′=[d′0, d′1, . . . , d′N-2, d′N-1] of length N is determined by a sub-block interleaver pattern π of length 32, the polar transform output bit sequence d, and the polar matrix size N as follows.
Here, π=[π0, π1, π2, π3, π4, π5, π6, π7, π8, π9, π10, π11, π12, π13, π14, π15, π16, π17, π18, π19, π20, π21, π22, π23, π24, π25, π26, π27, π28, π29, π30, π31]=[0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31], and J=[J0, J1, . . . , JN-2, JN-1] is an interleaver pattern of length N determined by the sub-block interleaver pattern π and the polar matrix size N. The interleaver pattern J is a permutation of the integer sequence [0, 1, 2, . . . , N−2, N−1].
(2) Bit selection: There are three types of bit selection named as repetition, puncturing and shortening. With the interleaving output bit sequence d′, the length of the input bit sequence K, the length of the output bit sequence E, and the polar matrix size N, the output bit sequence e is determined as follows.
A. Repetition: For E≥N,
ek=d′mod(k,N), k=0, 1, 2, . . . , E−2, E−1.
B. Puncturing: For E<N and K|E≤ 7/16,
ek=d′N-E+k, k=0, 1, 2, . . . , E−2, E−1.
C. Shortening: For E<N and K|E> 7/16,
ek=d′k, k=0, 1, 2, . . . , E−2, E−1.
Rate matching can also be alternatively described as follows. Denote R=<R(0), R(1), . . . , R(Nr−2), R(Nr−1)> as an ordered rate matching index set of size Nr=min(E, N), where the ordered rate matching index set R is a subset of the integer set ZN. Then, with the polar transform output bit sequence d, the ordered rate matching index set R, the length of the output bit sequence E, and the polar matrix size N, the output bit sequence e is determined as ek=dR(mod(k,N), k=0, 1, 2, . . . , E−2, E−1. Here, the ordered rate matching index set R=<J0, J1, . . . , JN-2, JN-1> for bit selection with repetition; the ordered rate matching index set R=<JN-E, JN-E+1, JN-E+2, . . . , JN-2, JN-1> for bit selection with puncturing; and the ordered rate matching index set R=<J0, J1, . . . , JE-2, JE-1> for bit selection with shortening. J=[J0, J1, . . . , JN-2, JN-1] is the interleaver pattern of length N determined in the sub-block interleaving operation.
PAC codes is a class of pre-transformed polar codes. Specifically, PAC codes are polar codes using convolution transform.
Operation 210: Rate profiling. The rate profiling 210 shown in
Operation 220: Convolution transform. The convolution transform 220 shown in
where vi-k=0 if i<k.
Operation 230: Polar transform. The polar transform 230 as shown in
A Rate Profiling and a Convolution Transform Combines into a Precoding
The combination of a rate profiling and a convolution transform is a precoding for PAC codes, specifically a convolution precoding, where the precoding input bit sequence is the input bit sequence c=[c0, c1, . . . , cK-2, cK-1] of length K and the precoding output bit sequence is the convolution transform output bit sequence u=[u0, u1, . . . , uN-2, uN-1] of length N. Define a state bit sequence t=[t0, t1, t2, . . . , tm-1, tm] of length m+1. The precoding output bit sequence u is determined by the precoding input sequence c, the data bit index set Q of size K, the generator bit sequence g=[g0, g1, . . . , gm-1, gm] of length-(m+1) corresponding to the generator polynomial g(D)=g0+g1·D+ . . . +gm-1·Dm-1+gm·Dm over GF(2), and the polar matrix size N is as follows.
The rate profiling operation in PAC coding can be described as vector-matrix multiplication over GF(2). Specifically, the rate-profiling output bit sequence v is determined by the input bit sequence c as: v=c·F, where F is a rate profiling matrix with K rows and N columns defined by the data bit index set Q of size K with the following properties.
For example, for K=4, N=8 and Q={3, 5, 6, 7}, the rate profiling matrix F is a matrix with 4 rows and 8 columns as follow.
Similar to rate profiling, the convolution transform in PAC coding can be described as vector-matrix multiplication over GF(2). Specifically, the convolution transform output bit sequence u of length N is determined by the convolution transform input bit sequence of length N (the rate profiling output bit sequence v of length N) as u=v·C, where C is a convolution transform matrix of N rows and N columns defined by the generator polynomial g(D)=g0+g1·D+ . . . +gm-1·Dm-1+gm·Dm (or equivalently the generator bit sequence g=[g0, g1, . . . , gm-1, gm] of length-(m+1)) and the polar matrix size N. The convolution transform matrix C is a Toeplitz matrix defined as
for i=0, 1, 2, . . . , N−1 and j=0, 1, 2, . . . , N−1, where Ci,j is the element in the i-th row and j-th column of the convolution transform matrix C. Written in matrix form, the convolution transform matrix C is as follow.
For example, for N=8 and a generator polynomial g(D)=g0+g1·D+g2·D2+g3·D3=1+D2+D3 with a generator bit sequence g=[g0, g1, g2, g3]=[1, 0, 1, 1] and a memory length m=3, the 8-by-8 convolution transform matrix C is as follows.
With the rate profiling matrix F and the convolution transform matrix C, the precoding of PAC coding is u=c·W=c·F·C, where u is a precoding output bit sequence of length N, the input bit sequence c is a precoding input bit sequence of length K, and the matrix multiplication and the vector-matrix multiplication is over GF(2). W=F·C is the precoding matrix of PAC coding. The precoding matrix W is an upper triangular matrix with K rows and N columns such that an element Wi,j in the i-th row and j-th column of the precoding matrix W is 0 for any j<i with i and j being non-negative integers smaller than N.
With the rate profiling matrix F and the convolution transform matrix C above, the precoding matrix W=F·C of PAC coding is as follows.
Referring back to
Details about the above sets, sequences, matrices, and/or polynomials are further discussed below.
The data index set Q: The data index set Q is a subset of the first integer set ZN, wherein the number of elements in the data index set Q is equal to the length of the input bit sequence K (the data index set Q has K elements, or say, the data index set size is K). Elements in the data index set Q are non-negative integers smaller than the polar matrix size N. In a first specific example with N=8 and K=4, a data index set is Q={3, 5, 6, 7}. In a second specific example with N=32 and K=25, a data index set is Q={5, 9, 6, 17, 10, 18, 12, 20, 24, 7, 11, 19, 13, 14, 21, 26, 25, 22, 28, 15, 23, 31, 27, 29, 30}.
The rate profiling frozen bit sequence f: In some embodiments, the rate profiling frozen bit sequence f can be any bit sequence of length N-K. In a specific example with N=8 and K=3, a rate profiling frozen bit sequence is f=[1, 1, 0, 0, 1]. In another specific example with N=8 and K=3, a rate profiling frozen bit sequence is f=[0, 0, 0, 0, 0]. In a third specific example with N=32 and K=25, a rate profiling frozen bit sequence f is an all-zero bit sequence of length N-K=32-25=7. In some embodiments, the rate profiling frozen bit sequence f can be any bit sequence of length N. In a specific example with N=8, a rate profiling frozen bit sequence is f=[0, 0, 0, 1, 1, 1, 0, 1]. In another specific example with N=8, a rate profiling frozen bit sequence is f=[0, 0, 0, 0, 0, 0, 0, 0]. In a third specific example with N=32, a rate profiling frozen bit sequence f is an all-zero bit sequence of length N=32.
The rate profiling matrix F: The rate profiling matrix F is an upper triangular matrix with K rows and N columns having the following properties.
In a specific example with K=4 rows and N=8 columns, a rate profiling matrix F is as follows.
The 0th, 1st, 2nd and 4th columns are all-zero columns, and the 3rd, 5th, 6th and 7th columns has only one non-zero element “1” and comprises an identity matrix with K=4 rows and K=4 columns as
The generator bit sequence g: The generator bit sequence g=[g0, g1, . . . , gm] can be any binary sequence of length m+1, wherein m is called the memory length. In a specific example with a memory length m=6, a generator bit sequence is g=[g0, g1, g2, g3, g4, g5, g6]=[1, 0, 1, 1, 0, 1, 1]. In another specific example with a memory length m=3, a generator bit sequence is g=[g0, g1, g2, g3]=[1, 1, 0, 1].
The generator polynomial g(D): The generator polynomial g(D)=g0+g1·D+ . . . +gm-1·Dm-1+gm·Dm can be any binary polynomial over GF(2), wherein m is the generator polynomial degree. In a specific example with a memory length m=6, a generator polynomial is g(D)=g0+g1·D+g2·D2+g3·D3+g4·D++g5·D5+g6·D6=1+0. D+1·D2+1·D3+0·D4+1·D5+1·D6=1+D2+D3+D5+D6. In another specific example with a memory length m=3, a generator polynomial is g(D)=g0+g1·D+g2·D2+g3·D3=1+1·D+0·D2+1·D3=1+D+D3.
The recursive feedback bit sequence q: The recursive feedback bit sequence q=[q0, q1, . . . , qm] is a binary sequence of length m+1 with [q1, . . . , qm] being any binary sequence of length m and q0=1, wherein m is the memory length. In a specific example with a memory length m=3, a recursive feedback bit sequence is q=[q0, q1, q2, q3, q4, q5, q6]=[1, 0, 1, 0, 1, 1, 1]. In another specific example with a memory length m=3, a recursive feedback bit sequence is q=[q0, q1, q2, q3]=[1, 0, 1, 1].
The recursive feedback polynomial q(D): The recursive feedback polynomial q(D)=q0, +q1·D+ . . . +qm-1·Dm-1+qm·Dm is a binary polynomial with the zero-degree coefficient q0 being 1 and other coefficients q1, . . . , qm being any binary values over GF(2), wherein m is the memory length. In a specific example with a memory length m=6, a recursive feedback polynomial is q(D)=q0+q1·D+q2·D2+q3·D3+q4·D4+q5·D5+q6·D6=1+0·D+1·D2+0·D3+1·D4+1·D5+1·D6=1+D2+D4+D5+D6. In another specific example with a memory length m=3, a recursive feedback polynomial is q(D)=q0+q1·D+92·D2+q3·D3=1+0·D+1·D2+1·D3=1+D2+D3.
The state bit sequence t: The state bit sequence t is for storing the convolution state.
The pre-transform matrix T: The pre-transform matrix T is a binary upper triangular matrix with N rows and N columns satisfying the following: Ti,j=0 for any integers i and j with 0≤j<i<N, wherein Ti,j is the element in the i-th row and the j-th column of the pre-transform matrix T.
Row properties of the pre-transform matrix T: In some embodiments, the pre-transform matrix T has N−Nr rows with all elements being zero, wherein Nr is the size of the ordered rate matching index set. In some embodiments, for a row index i not belonging to the ordered rate matching index set R, all elements in the i-th row of the pre-transform matrix T are zero. In some embodiments, the pre-transform matrix T has N−1−Qmax rows with all elements being zero, wherein Qmax is an element that has a largest value in the data index set Q with
In some embodiments, the pre-transform matrix T has all elements in the last N−1−Qmax rows being zero, wherein Qmax is an element that has a largest value in the data index set Q with
In some embodiments, the pre-transform matrix T has all elements in the i-th rows being zero for i being larger than Qmax, wherein Qmax is an element that has a largest value in the data index set Q with
In some embodiments, the pre-transform matrix T has N−1−Rmax rows with all elements being zero, wherein Rmax is an element that has a largest value in the ordered rate matching index set R with
In some embodiments, the pre-transform matrix T has all elements in the last N−1−Rmax rows being zero, wherein Rmax is an element that has a largest value in the ordered rate matching index set R with
In some embodiments, the pre-transform matrix T has all elements in the i-th rows being zero for i being larger than Rmax, wherein Rmax is an element that has a largest value in the data index set R with
Column properties of the pre-transform matrix T: In some embodiments, the pre-transform matrix T has N−Nr columns with all elements being zero, wherein Nr is the ordered rate matching index set size. In some embodiments, for a column index j not belonging to the ordered rate matching index set R, all elements in the j-th column of the pre-transform matrix T are zero. In some embodiments, the pre-transform matrix T has N−1-Qmax columns with all elements being zero, wherein Qmax is an element that has a largest value in the data index set Q with
In some embodiments, the pre-transform matrix T has all elements in the last N−1-Qmax columns being zero, wherein Qmax is an element that has a largest value in the data index set y with
In some embodiments, the pre-transform matrix T has all elements in the j-th column being zero for j being larger than Qmax, wherein Qmax is an element that has a largest value in the data index set Q with
In some embodiments, the pre-transform matrix T has N−1−Rmax columns with all elements being zero, wherein Rmax is an element that has a largest value in the ordered rate matching index set R with
In some embodiments, the pre-transform matrix T has all elements in the last N−1−Rmax columns being zero, wherein Rmax is an element that has a largest value in the ordered rate matching index set R with
In some embodiments, the pre-transform matrix T has all elements in the j-th column being zero for j being larger than Rmax, wherein Rmax is an element that has a largest value in the data index set R with
The precoding matrix W: The precoding matrix W is a binary upper triangular matrix with K rows and N columns having the following properties: Wi,j=0 for any integers i and j with 0≤ j<i<K, where Wi,j is the element in the i-th row and j-th column of the precoding matrix W.
In some embodiments, the precoding matrix W has at least N−Nr columns with all elements being zero, wherein Nr is the set size of the ordered rate matching index set R. In some embodiments, for a column index j not belonging to the ordered rate matching index set R, all elements in the j-th column of the precoding matrix W are zero.
In some embodiments, the precoding matrix W has at least N−1−Rmax columns with all elements being zero, wherein Rmax is an element that has a largest value in the data index set R with
In some embodiments, for a column index j larger than Rmax, all elements in the j-th column of the precoding matrix W are zero, wherein Rmax is an element that has a largest in the data index set R with
The ordered rate matching index set R: The ordered rate matching index set R can be any subset of the first integer set ZN having Nr elements, wherein Nr=min(N, E) and elements in the ordered rate matching index set R are non-negative integers smaller than the polar matrix size N. A first specific example of the ordered rate matching index set R is of size Nr=N and R contains all elements in the first integer set ZN, wherein R=<R(0), R(1), R(2), . . . , R(Nr−2), R(Nr−1)>=<0, 1, 2, . . . , N−2, N−1>. A second specific example of the ordered rate matching index set R is of size Nr=E and R contains all non-negative integers smaller than E: R=<R(0), R(1), R(2), . . . , R(Nr−2), R(Nr−1)>=<0, 1, 2, . . . , E−2, E−1>. A third specific example of the ordered rate matching index set R is of size Nr=E and R contains all integers smaller than N and larger than N−E−1: R=<R(0), R(1), R(2), . . . , R(Nr−2), R(Nr−1)>=<N−E, N−E+1, N−E+2, . . . , N−2, N−1>. Let J=[J0, J1, . . . , JN-2, JN-1] be an interleaver pattern of length N determined by the sub-block interleaver pattern π=[π0, π1, π2, π3, π4, π5, π6, π7, π8, π9, π10, π11, π12, π13, π14, π15, π16, π17, π18, π19, π20, π21, π22, π23, π24, π25, π26, π27, π28, π29, π30, π31]=[0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31] and the polar matrix size N as follows. Here, J=[J0, J1, . . . , JN-2, JN-1] is an interleaver pattern that is a permutation of the integer sequence [0, 1, 2, . . . , N−2, N−1], wherein a specific example of J is defined as follows.
A fourth specific example of the ordered rate matching index set R is of size Nr=N and R contains all elements in the first integer set ZN. R=<R(0), R(1), R(2), . . . , R(Nr−2), R(Nr−1)>=<J0, J1, . . . , JN-2, JN-1>; wherein, Ji is the i-th element in the interleaver pattern J=[J0, J1, . . . , JN-2, JN-1]. A fifth specific example of the ordered rate matching index set R is of size Nr=E and R contains all elements in the interleaver pattern J with indices smaller than E. R=<R(0), R(1), R(2), . . . , R(Nr−2), R(Nr−1)>=<J0, J1, . . . , JE-2, JE-1>, wherein, J; is the i-th element in the interleaver pattern J=[J0, J1, . . . , JN-2, JN-1]. A sixth specific example of the ordered rate matching index set R is of size Nr=E and R contains all elements in the interleaver pattern J with indices larger than N−E−1 and smaller than N. R=<R(0), R(1), R(2), . . . , R(Nr−2), R(Nr−1)>=<JN-E, JN-E+1, JN-E+2, . . . , JN-2, JN-1>, wherein, Ji is the i- th element in the interleaver pattern J=[J0, J1, . . . , JN-2, JN-1].
The precoding input set PI: The precoding input index set PI can be any subset of the first integer set ZN. The precoding input set PI can be used in a pre-transform operation of precoding to enable variable lengths so as to improve transmission efficiency of the payload.
A first specific example of the precoding input index set PI is PI equal to the first integer set ZN. A second specific example of the precoding input index set PI is that PI consists of all non-negative integers not greater than Qmax, PI={0, 1, 2, . . . , Qmax−1, Qmax} with Qmax+1 elements, wherein Qmax is an element that has the largest value in the data index set Q with
A third specific example of the precoding input index set PI is PI equal to the ordered rate matching index set R. A fourth specific example of the precoding input index set PI is that PI consists of all non-negative integers not greater than Rmax, PI={0, 1, 2, . . . , Rmax−1, Rmax} with Rmax+1 elements, wherein Rmax is an element that has the largest value in the ordered rate matching index set R with
The precoding output set PO: The precoding output index set PO can be any subset of the first integer set ZN. The precoding output index set PO can be used in a pre-transform operation of precoding to enable variable lengths so as to improve transmission efficiency of the payload.
A first specific example of the precoding output index set PO is PO equal to the first integer set ZN. A second specific example of the precoding output index set PO is that PO consists of all non-negative integers not greater than Qmax, PO={0, 1, 2, . . . , Qmax−1, Qmax} with Qmax+1 elements, wherein Qmax is the element with largest value in the data index set Q with
A third specific example of the precoding output index set PO is PO equal to the ordered rate matching index set R. A fourth specific example of the precoding output index set PO is that PO consists all non-negative integers not greater than Rmax, PO={0, 1, 2, . . . , Rmax−1, Rmax} with Rmax+1 elements, wherein Rmax is the element with largest value in the ordered rate matching index set R with
The precoding frozen bit sequence h: In some embodiments, the precoding frozen bit sequence h can be any bit sequence of length N−NPO, wherein NPO is the size of the precoding output index set PO and N is the polar matrix size. A specific example with N=8 and NPO=5, the precoding frozen bit sequence is h=[1, 0, 1] of length N−NPO=8−5=3. Another specific example with N=32 and NPO=5, the precoding frozen bit sequence h is an all-zero sequence of length N−NPO=32-5=27.
In some embodiments, the precoding frozen bit sequence h can be any bit sequence of length N, wherein N is the polar matrix size. A specific example with N=8, the precoding frozen bit sequence is h=[0, 0, 0, 0, 0, 1, 0, 1] of length N=8. Another specific example with N=32, the precoding frozen bit sequence h is an all-zero sequence of length N=32.
The polar matrix G(N): The polar matrix G(N) with N rows and N columns is one of the following: (1) G(N)=(P(2))⊗n; (2) G(N)=B(N)·(P(2))⊗n; (3) G(N)=P(N); or (4) G(N)=B(N)·P(N), where the matrix operation is over GF(2),
is the n-th Kronecker power of the matrix P(2), and B(N) is a bit-reversal permutation matrix with N rows and N columns. 0 is an all-zero matrix with N/2 rows and N/2 columns. Let Bi,j(N) be the element at the i-th row and j-th column of the bit-reversal permutation matrix B(N). Then, we have
for 0<i<N and 0<j<N, where br(i) is the bit-reversal function defined as br(i)=Σk=0n-1bk·2n-1-k and [bn-1, bn-2, . . . , b1, b0] is the n-bit binary expansion of the integer i=Σk=0n-1bk·2k. A sequence (or a vector) x of length N over GF(2) multiplying the polar matrix G(N) over GF(2) is called a polar transform on the sequence (vector) x. Denote y=x·G(N), where the vector-matrix multiplication is performed over GF(2). Then, y is the polar transform of x.
In some embodiments, the i-th bit ui in the precoding output sequence u is determined by a subset of elements in the precoding input bit sequence c with indices in the integer set {0, 1, 2, . . . , i−1, i}, all non-negative integers not greater than i.
In some embodiments, the i-th bit ui in the precoding output sequence u is a linear combination over GF(2) of elements c0, c1, c2, . . . , ci-1, ci in the precoding input bit sequence c.
In some embodiments, the i-th output bit ui in the precoding output sequence u of length N is determined by a sub-sequence of the precoding input sequence c with indices in the set {0, 1, 2, . . . , NE(i)−2, NE(i)−1} and the rate profile frozen bit sequence f=[f0, f1, . . . , fN-K-1] of length N-K, wherein NE(i) is the size of the set {0, 1, 2, . . . , i}∩Q, wherein, the rate profile frozen bit sequence f can be any binary sequence of length N-K. In some embodiments, the rate profile frozen bit sequence f is the all-zero sequence of length N-K.
In some embodiments, for i not belonging to the precoding output index set PO, the i-th output bit ui in the precoding output sequence u of length N is set to a bit in a precoding frozen bit sequence h=[h0, h1, . . . , hN
In some embodiments, for i not belonging to the precoding output index set PO, the i-th output bit ui in the precoding output sequence u of length N is set to bit 0.
In some embodiments, the i-th bit ui in the precoding output sequence u is determined by both a subset of elements in the precoding input bit sequence c with indices in the integer set {0, 1, 2, . . . , i−1, i} and a subset of elements in the precoding output bit sequence u with indices in the integer set {0, 1, 2, . . . , i−2, i−1}.
In some embodiments, the i-th bit ui in the precoding output sequence u is a linear combination over GF(2) of elements c0, c1, c2, . . . , ci-1, ci in the precoding input bit sequence c and elements u0, u1, u2, . . . , ui-2, ui-1 in the precoding output bit sequence u.
In some embodiments, a precoding output bit in the precoding output bit sequence u is determined by both (1) current precoding input bit and preceding precoding input bits in the precoding input bit sequence c; and (2) current precoding output bit and preceding precoding output bits in the precoding output bit sequence u.
In some embodiments, the precoding input sequence c has a length K. The precoding output bit sequence u has a length N. The precoding output bit sequence u is determined by performing vector-matrix multiplication on the precoding input bit sequence c and the precoding matrix W with K rows and N columns as u=c·W. The precoding input sequence c of length K is the input bit sequence of length K and the vector-matrix multiplication is performed over GF(2).
In some embodiments, the precoding output bit sequence u of length N is determined by performing vector-matrix multiplication on the precoding input bit sequence c and the precoding matrix W with K rows and N columns and adding the precoding frozen bit sequence h of length N as u=c·W+h. The precoding input sequence c of length K is the input bit sequence of length K. Both the vector-matrix multiplication and the vector-vector addition are performed over GF(2).
In some embodiments, the precoding output sequence u of length N is determined using both the rate profiling matrix F with K rows and N columns and the pre-transform matrix T with N rows and N columns by multiplying the precoding input sequence c with the rate profiling matrix F and the pre-transform matrix T as u=c·F·T. The precoding input sequence c is the input bit sequence c of length K, N is the polar matrix size, and the matrix multiplication and the vector-matrix multiplication are performed over GF(2).
In some embodiments, the precoding output sequence u of length N is determined using the rate profiling matrix F with K rows and N columns, the rate profiling frozen bit sequence f of length N, and the pre-transform matrix T with N rows and N columns by multiplying the precoding input sequence c with the rate profiling matrix F over GF(2), adding the rate profiling frozen bit sequence f of length N over GF(2), and multiplying the pre-transform matrix T over GF(2) as u=(c·F+f)·T. The precoding input sequence e is the input bit sequence e of length K. N is the polar matrix size. The matrix multiplication, the vector-matrix multiplication and the vector-vector addition are performed over GF(2).
In some embodiments, the precoding output sequence u of length N is determined using the rate profiling matrix F with K rows and N columns, the pre-transform matrix T with N rows and N columns, and the precoding frozen bit sequence h of length N by multiplying the precoding input sequence c with the rate profiling matrix F over GF(2); multiplying the pre-transform matrix T over GF(2); and adding the precoding frozen bit sequence h of length N over GF(2) as u=c·F·T+h. The precoding input sequence c is the input bit sequence c of length K. N is the polar matrix size. The matrix multiplication, the vector-matrix multiplication and the vector-vector addition are performed over GF(2).
In some embodiments, the precoding output sequence u of length N is determined using both the rate profiling matrix F with K rows and N columns, the rate profiling frozen bit sequence f of length N, the pre-transform matrix T with N rows and N columns, and the precoding frozen bit sequence h of length N by multiplying the precoding input sequence c with the rate profiling matrix F over GF(2); adding the rate profiling frozen bit sequence f of length N over GF(2); multiplying the pre-transform matrix T over GF(2); and adding the precoding frozen bit sequence h of length N over GF(2) as u=(c·F+f)·T+h. The precoding input sequence c is the input bit sequence c of length K. N is the polar matrix size. The matrix multiplication, the vector-matrix multiplication and the vector-vector addition are performed over GF(2).
Precoding Determined by Q, f, g or (D), PI, and PO, h, t
In some embodiments, the precoding determines the precoding output bit sequence u of length N using at least one of the following: the data index set Q, the rate profiling frozen bit sequence f, the generator bit sequence g=[g0, g1, . . . , gm], the generator polynomial g(D)=g0+g1·D+ . . . +gm-1·Dm-1+gm·Dm over GF(2), the precoding input index set PI, the precoding output index set PO, the precoding frozen bit sequence h, or the state bit sequence t=[t0, t1, . . . , tm-1, tm]. The rate profiling frozen bit sequence f is of length N-K, the precoding frozen bit sequence h is of length N−NPO and NPO is the size of the precoding output index set PO.
Table 2 shows example Algorithms 1A-1L, which are example implementations for the precoding. In the example Algorithms 1A-1L, the state bit sequence t=[t0, t1, . . . , tm-1, tm] is initialized to all zeros. If an index i belong to the data index set Q, the bit to in the state bit sequence t=[t0, t1, . . . , tm-1, tm] is set to a bit in the precoding input bit sequence c. If an index i belongs to the precoding output index set PO, the i-th bit ui of the precoding output bit sequence u is determined by the generator bit sequence g=[g0, g1, . . . , gm] and the state bit sequence t=[t0, t1, . . . , tm-1, tm], wherein, ui=mod(Σj=0mgj·tj, 2). If an index i belongs to the precoding output index set PO, the i-th bit ui of the precoding output bit sequence u is determined by the generator polynomial g(D)=g0+g1·D+ . . . +gm-1·Dm-1+gm·Dm over GF(2) (e.g., as shown in
In some embodiments, if an index i does not belong to the data index set Q, the bit t0 in the state bit sequence t=[t0, t1, . . . , tm-1, tm] is set to 0, e.g., as in Algorithms 1A, 1B, 1C, 1G, 1H, and 1I. In some examples, if an index i does not belong to the data index set Q, the bit to in the state bit sequence t=[t0, t1, . . . , tm-1, tm] is set to a bit in the rate profiling frozen bit sequence f, e.g., as shown in Algorithms 1D, 1E, 1F, 1J, 1K, and 1L.
In some embodiments, if an index i does not belong to the precoding output index set PO, the i-th bit ui of the precoding output bit sequence u is set to 0, e.g., as shown in Algorithms 1A, 1D, 1G, and 1J.
In some embodiments, if an index i does not belong to the precoding output index set PO, the i-th bit ui of the precoding output bit sequence u is set to t0 in the state bit sequence t=[t0, t1, . . . , tm-1, tm], e.g., as shown in Algorithms 1B, 1E, 1H, and 1K.
In some examples, if an index i does not belong to the precoding output index set PO, the i-th bit ui of the precoding output bit sequence u is set to a bit in the precoding frozen bit sequence h, as shown in Algorithms 1C, 1F, 1I, and 1L. The precoding frozen bit sequence h is of length N−NPO and NPO is the size of the precoding output index set PO.
In some examples, if an index i belongs to the precoding input index set PI, a right shift is performed on the state bit sequence t=[t0, t1, . . . , tm-1, tm] as follows.
In some examples, for all indices i, a right shift is performed on the state bit sequence t=[t0, t1, . . . , tm-1, tm] as follows.
The state bit sequence t=[t0, t1, . . . , tm-1, tm] of length m+1 is for storing the convolution state. gj can be either elements in the generator bit sequence g or coefficients in the generator polynomial g(D), e.g., as shown in
Precoding Determined by Q, f, g or q(D), PI, and PO, h, t
In some embodiments, the precoding determines the precoding output bit sequence u of length N using at least one of the following: the data index set Q, the rate profiling frozen bit sequence f, the recursive feedback bit sequence q=[q0, q1, . . . , qm], the recursive feedback polynomial q(D)=q0+q1·D+ . . . +qm·Dm over GF(2), the precoding input index set PI, the precoding output index set PO, the precoding frozen bit sequence h, or the state bit sequence t=[t0, t1, . . . , tm-1, tm] of length m+1. The rate profiling frozen bit sequence f is of length N-K. The precoding frozen bit sequence h is of length N−NPO and NPO is the size of the precoding output index set PO.
Table 3 shows example Algorithms 2A-2L, which are example implementations for the precoding. In the example Algorithms 2A-2L, the state bit sequence t=[t0, t1, . . . , tm-1, tm] is initialized to all zeros. If an index i belong to the data index set Q, the bit to in the state bit sequence t=[t0, t1, . . . , tm-1, tm] is set to a bit in the precoding input bit sequence c. If an index i belongs to the precoding output index set PO, the i-th bit ui of the precoding output bit sequence u is determined by the recursive feedback bit sequence q=[q0, q1, . . . , qm] and the state bit sequence t=[t0, t1, . . . , tm-1, tm], wherein, ui=mod(Σj=0mgj·tj, 2). If an index i belongs to the precoding output index set PO, the i-th bit ui of the precoding output bit sequence u is determined by the recursive feedback polynomial q(D)=q0+q1·D+ . . . +qm-1·Dm-1+qm·Dm over GF(2) and the state bit sequence t=[t0, t1, . . . , tm-1, tm], wherein, ui=mod(Σj=0mgj·tj, 2).
In some embodiments, if an index i does not belong to the data index set Q, the bit to in the state bit sequence t=[t0, t1, . . . , tm-1, tm] is set to 0. e.g., as in Algorithms 2A, 2B, 2C, 2G, 2H, and 2I.
In some embodiments, if an index i does not belong to the data index set Q, the bit to in the state bit sequence t=[t0, t1, . . . , tm-1, tm] is set to a bit in the rate profiling frozen bit sequence f, e.g., as in Algorithms 2D, 2E, 2F, 2J, 2K, and 2L.
In some embodiments, if an index i does not belong to the precoding output index set PO, the i-th bit ui of the precoding output bit sequence u is set to 0, e.g., as in Algorithms 2A, 2D, 2G, and 2J.
In some embodiments, if an index i does not belong to the precoding output index set PO, the i-th bit ui of the precoding output bit sequence u is set to t0 in the state bit sequence t=[t0, t1, . . . , tm-1, tm], e.g., as in Algorithms 2B, 2E, 2H, and 2K.
In some embodiments, if an index i does not belong to the precoding output index set PO, the i-th bit ui of the precoding output bit sequence u is set to a bit in the precoding frozen bit sequence h, e.g., as in Algorithms 2C, 2F, 2I, and 2L. The precoding frozen bit sequence h is of length N−NPO and NPO is the size of the precoding output index set PO.
In some examples, if an index i belongs to the precoding input index set PI, a right shift is performed on the state bit sequence t=[t0, t1, . . . , tm-1, tm] as follows.
In some examples, for all indices i, a right shift is performed on the state bit sequence t=[t0, t1, . . . , tm-1, tm] as follows.
t=[t0, t1, . . . , tm-1, tm] is a state bit sequence of length m+1 for storing the convolution state. qj can be either elements in the recursive feedback bit sequence q or coefficients in the recursive feedback polynomial q(D).
Precoding Determined by Q, f, g or g(D), q or q(D), PI, and PO, h, t
In some embodiments, the precoding determines the precoding output bit sequence u of length N using at least one of the following: the data index set Q, the rate profiling frozen bit sequence f, the generator bit sequence g=[g0, g1, . . . , gm], the generator polynomial g(D)=g0+g1·D+ . . . +gm·Dm over GF(2), the recursive feedback bit sequence q=[q0, q1, . . . , qm], the recursive feedback polynomial q(D)=q0+q1·D+ . . . +qm·Dm over GF(2), the precoding input index set PI, the precoding output index set PO, the precoding frozen bit sequence h, or the state bit sequence t=[t0, t1, . . . , tm-1, tm]. The rate profiling frozen bit sequence f is of length N-K. The precoding frozen bit sequence h is of length N−NPO and NPO is the size of the precoding output index set PO.
Table 4 shows example Algorithms 3A-3L, which are example implementations for the precoding. In the example Algorithm 3A-3L, the state bit sequence t=[t0, t1, . . . , tm-1, tm] is initialized to all zeros. If an index i belong to the data index set Q, the bit to in the state bit sequence t=[t0, t1, . . . , tm-1, tm] is set to a bit in the precoding input bit sequence c. If an index i belongs to the precoding output index set PO, the i-th bit ui of the precoding output bit sequence u is determined by the generator bit sequence g=[g0, g1, . . . , gm] (or the generator polynomial g(D)=g0+g1·D+ . . . +gm·Dm over GF(2)), the recursive feedback bit sequence q=[q0, q1, . . . , qm] (or the recursive feedback polynomial q(D)=q0+q1·D+ . . . +qm·Dm over GF(2)), and the state bit sequence t=[t0, t1, . . . , tm-1, tm].
In some embodiments, if an index i does not belong to the data index set Q, the bit to in the state bit sequence t=[t0, t1, . . . , tm-1, tm] is set to 0, e.g., as in Algorithm 3A, 3B, 3C, 3G, 3H, and 3I. In some embodiments, if an index i does not belong to the data index set Q, the bit to in the state bit sequence t=[t0, t1, . . . , tm-1, tm] is set to a bit in the rate profiling frozen bit sequence f, e.g., as in Algorithm 3D, 3E, 3F, 3J, 3K, and 3L. In some embodiments, if an index i does not belong to the precoding output index set PO, the i-th bit ui of the precoding output bit sequence u is set to 0, e.g., as in Algorithm 3A, 3D, 3G, and 3J. In some embodiments, if an index i does not belong to the precoding output index set PO, the i-th bit ui of the precoding output bit sequence u is set to t0 in the state bit sequence t=[t0, t1, . . . , tm-1, tm], e.g., as in Algorithm 3B, 3E, 3H, and 3K.
In some embodiments, if an index i does not belong to the precoding output index set PO, the i-th bit ui of the precoding output bit sequence u is set to a bit in the precoding frozen bit sequence h, e.g., as in Algorithm 3C, 3F, 3I, and 3L. The precoding frozen bit sequence h is of length N−NPO and NPO is the size of the precoding output index set PO. In some embodiments, if an index i belongs to the precoding input index set PI, a right shift is performed on the state bit sequence t=[t0, t1, . . . , tm-1, tm] as follows, e.g., as in Algorithm 3A, 3B, 3C, 3D, 3E, and 3F.
In some examples, for all indices i, a right shift is performed on the state bit sequence t=[t0, t1, . . . , tm-1, tm] as follows, e.g., as in Algorithm 3G, 3H, 3I, 3J, 3K, and 3L.
t=[t0, t1, . . . , tm-1, tm] is a state bit sequence of length m+1 for storing the convolution state. gj can be either elements in the generator bit sequence g or coefficients in the generator polynomial g(D). qj can be either elements in the recursive feedback bit sequence q or coefficients in the recursive feedback polynomial q(D).
In some embodiments, the precoding comprises a rate profiling and a pre-transform. The rate profiling comprises obtaining, by the first node, a rate profiling input bit sequence, and determining, by the first node, a rate profiling output bit sequence v=[v0, v1, . . . , vN-1]. The pre-transform comprises obtaining, by the first node, a pre-transform input bit sequence, and determining, by the first node, a pre-transform output bit sequence.
The rate profiling: The rate profiling comprises obtaining, by the first node, a rate profiling input bit sequence, and determining, by the first node, a rate profiling output bit sequence v=[v0, v1, . . . , vN-1]. As shown in
The pre-transform: The pre-transform comprises obtaining, by the first node, a pre-transform input bit sequence, and determining, by the first node, a pre-transform output bit sequence u=[u0, u1, . . . , uN-1]. As shown in
Parameters for the rate profiling: The rate profiling determines the rate profiling output bit sequence v corresponding to the rate profiling input bit sequence c by the first node using at least one of the following: the data index set Q), the rate profiling matrix F with K rows and N columns, or the rate profiling frozen bit sequence f.
In some embodiments, the rate profiling output bit sequence vis the multiplexing of the rate profiling input bit sequence c and the rate profiling frozen bit sequence f. The rate profiling frozen bit sequence f is of length N-K, and N is the polar matrix size and K is the rate profiling input bit sequence length. A first specific example with N=8 and K=3 is a rate profiling input bit sequence c=[c0, c1, c2] and a rate profiling frozen bit sequence f=[f0, f1, f2, f3, f4], then a rate profiling output bit sequence v=[v0, v1, v2, v3, v4, v5, v6, v7]=[f0, f1, f2, f3, f4, c0, c1, c2]. A second specific example with N=16 and K=4 is a rate profiling input bit sequence c=[c0, c1, c2, c3] and a rate profiling frozen bit sequence f=[f0, f1, f2, f3, f4, f5, f6, f7, f8, f0, f10, f11], then a rate profiling output bit sequence v=[v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v1, v12, v13, v14, v15]=[f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, c0, f11, c1, c2, c3]. A third specific example is given in Algorithm 4A of Table 5.
In some embodiments, for an index i belonging to the data index set Q, the bit vi in the rate profiling output bit sequence v is a bit in the rate profiling input bit sequence c. A first specific example with N=8, K=3 and a data index set Q={5, 6, 7}, a rate profiling input bit sequence c=[c0, c1, c2], the bits v5, v6, v7 with indices belonging to the data index set Q={5, 6, 7} in a rate profiling output bit sequence v=[v0, v1, v2, v3, v4, v5, v6, v7] is set as v5=c0, v6=c1, and v7=c2. A second specific example with N=16, K=4 and a data index set Q={11, 13, 14, 15}, a rate profiling input bit sequence c=[c0, c1, c2, c3], the bits v11, v13, v14, v15 with indices belonging to the data index set Q={11, 13, 14, 15} in a rate profiling output bit sequence v=[v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15] is set as v11=c0, v13=c1, v14=c2, and v15=c3. A third specific example is given in Algorithm 4A of Table 5. A fourth specific example is given in Algorithm 4B of Table 5.
In some embodiments, for a index i not belonging to the data index set Q, the bit vi in the rate profiling output bit sequence v is a bit in the rate profiling frozen bit sequence f. A first specific example with N=8, K=3 and Q={5, 6, 7}, a rate profiling frozen bit sequence f=[f0, f1, f2, f3, f4], the bits v0, v1, v2, v3, v4 with indices not belonging to the data index set Q={5, 6, 7} in a rate profiling output bit sequence v=[v0, v1, v2, v3, v4, v5, v6, v7] is set as v0=f0, v1=f1, v2=f2, v3=f3, and v4=f4. A second specific example with N=16, K=4 and Q={11, 13, 14, 15}, a rate profiling frozen bit sequence f=[f0, f1, f2, f3, f4, f5, f6, f7, f8, f0, f10, f11], the bits v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v12 with indices not belonging to the data index set Q={11, 13, 14, 15} in a rate profiling output bit sequence v=[v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15] is set as v0=f0, v1=f1, v2=f2, v3=f3, v4=f4, v5=f5, v6=f6, v1=f7, v8=f8, v9=f0, v10=f10, and v12=f1. A third specific example is given in Algorithm 4A of Table 5.
In some embodiments, the rate profiling output bit sequence vis the multiplexing of the rate profiling input bit sequence c and an all-zero sequence of length N-K, wherein N is the polar matrix size and K is the rate profiling input bit sequence length. A first specific example with N=8 and K=3 is a rate profiling input bit sequence c=[c0, c1, c2] and an all-zero sequence of length N−K=8−3=5, then a rate profiling output bit sequence v=[v0, v1, v2, v3, v4, v5, v6, v7]=[0, 0, 0, 0, 0, c0, c1, c2]. A second specific example with N=16 and K=4 is a rate profiling input bit sequence c=[c0, c1, c2, c3] and an all-zero sequence of length N-K=16−4=12, then a rate profiling output bit sequence v=[v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15]=[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, c0, 0, c1, c2, c3]. A third specific example is given in Algorithm 4B of Table 5.
In some embodiments, for an index i not belonging to the data index set Q, the bit vi in the rate profiling output bit sequence v is equal to 0. A first specific example with N=8, K=3 and Q={5, 6, 7}, the bits v0, v1, v2, v3, v4 with indices not belonging to the data index set Q={5, 6, 7} in a rate profiling output bit sequence v=[v0, v1, v2, v3, v4, v5, v6, v7] is set as v0=0, v1=0, v2=0, v3=0, and v4=0. A second specific example with N=16, K=4 and Q={11, 13, 14, 15}, the bits v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v12 with indices not belonging to the data index set Q={11, 13, 14, 15} in a rate profiling output bit sequence v=[v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15] is set as v0=0, v1=0, v2=0, v3=0, v4=0, v5=0, v6=0, v7=0, v8=0, v9=0, v10=0, and v12=0. A third specific example is given in Algorithm 4B of Table 5.
In some embodiments, the rate profiling output sequence v of length N is the multiplication of the rate profiling input bit sequence c and the rate profiling matrix F with K rows and N columns as v=c·F. The rate profiling input bit sequence is the input sequence c of length K, the vector-matrix multiplication is over GF(2). In a specific example with K=4 rows and N=8 columns, a rate profiling matrix
a rate profiling input bit sequence c=[c0, c1, c2, c3], then a profiling output sequence v=c·F=[0, 0, 0, c0, 0, c1, c2, c3].
In some embodiments, the rate profiling output sequence v of length N is determined by adding the rate profiling frozen bit sequence f and the multiplication of the rate profiling input bit sequence c and the rate profiling matrix F with K rows and N columns as v=c·F+f. The rate profiling input bit sequence is the input sequence c of length K, the vector-matrix multiplication is over GF(2), the vector-vector addition is over GF(2), the rate profiling frozen bit sequence f is of length N. In a specific example with K=4 rows and N=8 columns, a rate profiling matrix
a rate profiling input bit sequence c=[c0, c1, c2, c3], a rate profiling frozen bit sequence f=[f0, f1, f2, f3, f4, f5, f6, f7], then a profiling output sequence v=c·F+f=[f0, f1, f2, mod(c0+f3, 2), f4, mod(c1+f5, 2), mod(c2+f6, 2), mod(c3+f7, 2)].
Parameters for determining the pre-transform: The pre-transform determines the pre-transform output bit sequence u corresponding to the pre-transform input bit sequence v by the first node using at least one of the following: the generator bit sequence g=[g0, g1, . . . , gm] over GF(2), the generator polynomial g(D)=g0+g1·D+ . . . +gm-1·Dm-1+gm·Dm over GF(2), the recursive feedback bit sequence q=[q0, q1, . . . , qm]over GF(2), the recursive feedback polynomial q(D)=q0+q1·D++qm·Dm over GF(2), the state bit sequence t=[t0, t1, . . . , tm-1, tm] of length m+1, the pre-transform matrix T with N rows and N columns, the precoding input index set PI, the precoding output index set PO, or the precoding frozen bit sequence h.
In some embodiments, the pre-transform output sequence u of length N is the multiplication of the pre-transform input bit sequence and the pre-transform matrix T with N rows and N columns as u=v·T. The pre-transform input bit sequence is the rate profiling output sequence v of length N, the pre-transform output sequence u of length N is the precoding output bit sequence, the vector-matrix multiplication is over GF(2).
In some embodiments, the pre-transform output sequence u of length N is determined by adding the precoding frozen bit sequence h and the multiplication of the pre-transform input bit sequence v and the pre-transform matrix T with N rows and N columns as u=v·T+h. The pre-transform input bit sequence is the rate profiling output bit sequence v of length N, the vector-matrix multiplication is over GF(2), the vector-vector addition is over GF(2), the length of precoding frozen bit sequence h is equal to the polar matrix size N.
A Pre-Transform Determined by g or g(D), t, PI, PO, h
In some embodiments, the pre-transform determines the pre-transform output bit sequence u of length N using at least one of the following: the generator bit sequence g=[g0, g1, . . . , gm], the generator polynomial g(D)=g0+g1·D+ . . . +gm-1·Dm-1+gm·Dm over GF(2), the precoding input index set PI, the precoding output index set PO, or the precoding frozen bit sequence h. The precoding frozen bit sequence h is of length N−NPO and NPO is the size of the precoding output index set PO. Table 6 shows example Algorithms 5A-5G, which are example implementations for the pre-transform.
In some embodiments, if an index i belongs to the precoding output index set PO, the bit with the index i (ui) of the pre-transform output bit sequence u is determined by at least one of the following: the generator bit sequence g=[g0, g1, . . . , gm], the generator polynomial g(D)=g0+g1·D+ . . . +μm′D™ over GF(2), and L bits in the pre-transform input bit sequence v=[v0, v1, . . . , vN-1] with indices being the Z largest values in a first intersection set M1. The first intersection set M1 is the intersection set of a set with non-negative integers not greater than i ({0, 1, . . . , i−1, i}) and the precoding input index set PI. L=min(|M1|, min(i+1, m+1)) with |M1| being the number of elements in the first intersection set M1.
A first specific example with N=16, i=3, m=6, a generator polynomial g(D)=g0+g1·D+g2·D2+g3·D3+g4·D4+g5·D5+g6·D6, a precoding output index set PO={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, and a precoding input index set PI={0, 2, 3, 5, 7, 8, 10} is:
A second specific example with N=16, i=9, m=3, a generator sequence g=[g0, g1, g2, g3], a precoding output index set PO={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, and precoding input index set PI={0, 2, 3, 5, 7, 8, 10} is:
In some embodiments, if an index i belongs to the precoding output index set PO, the bit with the index i (ui) of the pre-transform output bit sequence u is determined by at least one of the following: the generator bit sequence g=[g0, g1, . . . , gm], the generator polynomial g(D)=g0+g1·D+ . . . +gm·Dm over GF(2), and/or L bits vi, vi-1, . . . , vi-L+1 in the pre-transform input bit sequence v=[v0, v1, . . . , vN-1] with indices being the L largest values in a set with non-negative integers not greater than i ({0, 1, . . . , i−1, i}), where L=min(i+1, m+1).
A first specific example with i=3, m=6, a precoding output index set PO={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, and a generator polynomial g(D)=g0+g1·D+g2·D2+g3·D3+g4·D4+g5·D5+g6·D6 is
A second specific example with N=16, i=9, m=3, a precoding output index set PO={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, and a generator sequence g=[g0, g1, g2, g3] is
In some embodiments, for any index i, the bit with the index i (ui) of the pre-transform output bit sequence u is determined by at least one of the following: the generator bit sequence g=[g0, g1, . . . , gm], the generator polynomial g(D)=g0+g1·D+ . . . +gm·Dm over GF(2), and/or L bits in the pre-transform input bit sequence v=[v0, v1, . . . , vN-1] with indices being the L largest values in a first intersection set M1. The first intersection set M1 is the intersection set of a set with non-negative integers not greater than i ({0, 1, . . . , i−1, i}) and the precoding input index set PI, and L=min(|M1|, min(i+1, m+1)) with |M1| being the number of elements in the first intersection set M1.
A first specific example with N=16, i=2, m=6, a generator polynomial g(D)=g0+g1·D+g2·D2+g3·D3+g4·D4+g5·D5+g6·D6, and a precoding input index set PI={0, 2, 3, 5, 7, 8, 10} is:
A second specific example with N=16, i=9, m=3, a generator sequence g=[g0, g1, g2, g3], and a precoding input index set PI={0, 2, 5, 7, 8, 10} is:
In some examples, if an index i does not belong to the pre-transform output index set PO, the bit with the index i (ui) of the pre-transform output bit sequence u is set to 0, e.g., as in Algorithms 5A and 5D. In some examples, if an index i does not belong to the pre-transform output index set PO, the bit with the index i (ui) of the pre-transform output bit sequence u is set to the i-th bit vi of the pre-transform input bit sequence v, e.g., as in Algorithms 5B and 5E. In some examples, if an index i does not belong to the pre-transform output index set PO, the bit with the index i (u1) of the pre-transform output bit sequence u is set to a bit in the precoding frozen bit sequence h as in Algorithm 5C, and 5F, wherein the precoding frozen bit sequence h is of length N−NPO and NPO is the size of the precoding output index set PO.
In Algorithms 5A-5G, N is the polar matrix size, m is the memory length, vi is the bit with index i in the pre-transform input bit sequence, ui is the bit with index i in the pre-transform output bit sequence, gk is the bit with index k in the generator sequence g=[g0, g1, . . . , gm] or the coefficient of the term with degree K in the generator polynomial g(D)=g0+g1·D+ . . . +gm-1·Dm-1+gm·Dm over GF(2).
A pre-transform determined by q or q(D), t, PI, PO, h
In some embodiments, the pre-transform determines the pre-transform output bit sequence u of length N using at least one of the following: the recursive feedback bit sequence q=[q0, q1, . . . , qm], the recursive feedback polynomial q(D)=q0+q1·D+ . . . +qm-1·Dm-1+qm·Dm over GF(2), the precoding input index set PI, the precoding output index set PO, or the precoding frozen bit sequence h. The precoding frozen bit sequence h is of length N−NPO and NPO is the size of the precoding output index set PO. Table 7 shows example algorithms 6A-6G, which are example implementations for the pre-transform.
In some embodiments, if an index i belongs to the pre-transform output index set PO, the bit with the index i (ui) of the pre-transform output bit sequence u is determined by at least one of the following: the recursive feedback bit sequence q=[q0, q1, . . . , qm], the recursive feedback polynomial q(D)=q0+q1·D+ . . . +qm′Dm over GF(2), the i-th bit vi in the pre-transform input bit sequence v=[v0, v1, . . . , vN-1], and/or L bits in the pre-transform output bit sequence u=[u0, u1, . . . , uN-1] with indices being the L largest values in a second intersection set M2. The second intersection set M2 is the intersection set of a set with non-negative integers smaller than i({0, 1, . . . , i−2, i−1}) and the pre-transform output index set PI, and L=min(|M2|, min(i, m)) with |M2| being the number of elements in the second intersection set M2 (e.g., as shown in Algorithm 6A, 6B, and 6C of Table 7). A first specific example with N=16, i=3, m=6, a recursive feedback polynomial q(D)=g0+q1·D+q2·D2+q3·D3+q4·D4+q5·D5+q6·D6 with q0=1, a precoding output index set PO={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, and a precoding input index set PI={0, 2, 3, 5, 7, 8, 10} is:
A second specific example with N=16, i=9, m=3, a recursive feedback sequence q=[q0, q1, q2, q3] with q0=1, a precoding output index set PO={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, and a precoding input index set PI={0, 2, 3, 5, 7, 8, 10} is:
In some embodiments, if an index i belongs to the precoding output index set PO, the bit with index i (ui) of the pre-transform output bit sequence u is determined by at least one of the following: the recursive feedback bit sequence q=[q0, q1, . . . , qm], the recursive feedback polynomial q(D)=q0+q1D+ . . . +qm′D™ over GF(2), the bit with index i (vi) in the pre-transform input bit sequence v=[v0, v1, . . . , vN-1], and/or L bits ui-1, ui-2, . . . , ui-L in the pre-transform output bit sequence u=[u0, u1, . . . , uN-1] with indices being the L largest values in a set with non-negative integers smaller than i {0, 1, . . . , i−2, i−1}. L=min(i, m) (e.g., as shown in Algorithm 6D, 6E, and 6F).
A first specific example with N=16, i=3, m=6, a precoding output index set PO={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, and a recursive feedback polynomial q(D)=90+q1·D+q2·D2+q3·D3+q4·D4+q5·D5+q6·D6 is:
A second specific example with N=16, i=9, m=3, a recursive feedback q=[q0, q1, q2, q3] with q0=1, and a precoding output index set PO={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, is:
In some embodiments, for any index i, the bit with the index i (ui) of the pre-transform output bit sequence u is determined by at least one of the following: the recursive feedback bit sequence q=[q0, q1, . . . , qm], the recursive feedback polynomial q(D)=q0+q1·D+ . . . +qm·Dm over GF(2), the i-th bit vi in the pre-transform input bit sequence v=[v0, vi, . . . , vN-1], and/or L bits in the pre-transform output bit sequence u=[u0, u1, . . . , uN-1] with indices being the L largest values in a second intersection set M2. The second intersection set M2 is the intersection set of a set with non-negative integers smaller than i ({0, 1, . . . , i−2, i−1}) and the precoding output index set PI, and L=min(|M2|, min(i, m)) with |M2| being the number of elements in the second intersection set M2 (e.g., as shown in Algorithm 6G).
A first specific example with N=16, i=3, m=6, a recursive feedback polynomial q(D)=q0+q1·D+q2·D2+q3·D3+q4·D4+q5·D5+q6·D6 with q0=1, and a precoding input index set PI={0, 2, 3, 5, 7, 8, 10} is:
A second specific example with N=16, i=9, m=3, a recursive feedback sequence q=[q0, q1, q2, q3] with q0=1, and a precoding input index set PI={0, 2, 3, 5, 7, 8, 10} is
In some embodiments, if an index i does not belong to the precoding output index set PO, the bit with the index i (ui) of the pre-transform output bit sequence u is set to 0 (e.g., as in Algorithms 6A and 6D). In some embodiments, if an index i does not belong to the pre-transform output index set PO, the bit with the index i (ui) of the pre-transform output bit sequence u is set to the i-th bit vi of the pre-transform input bit sequence v (e.g., as in Algorithms 6B and 6E). In some embodiments, if an index i does not belong to the pre-transform output index set PO, the bit with the index i (ui) of the pre-transform output bit sequence u is set to a bit in the precoding frozen bit sequence h (e.g., as in Algorithms 6C and 6F). The precoding frozen bit sequence h is of length N−NPO and NPO is the size of the precoding output index set PO.
In example Algorithms 6A-6G, Nis the polar matrix size, m is the memory length, vi is the bit with index i in the pre-transform input bit sequence, ui is the bit with index i in the pre-transform output bit sequence, q is the bit with index k in the recursive feedback sequence q=[q0, q1, . . . , qm] or the coefficient of the term with degree K in the recursive feedback polynomial q(D)=q0+q1·D+ . . . +qm-1. Dm-1+qm·Dm over GF(2).
A Pre-Transform Determined by g or g(D), q or q(D), t, PI, PO, h
In some embodiments, the pre-transform determines the precoding output bit sequence u of length N using at least one of the following: the generator bit sequence g=[g0, g1, . . . , gm], the generator polynomial g(D)=g0+g1·D+ . . . +gm-1·Dm-1+gm·Dm over GF(2), the recursive feedback bit sequence q=[q0, q1, . . . , qm], the recursive feedback polynomial q(D)=q0+q1·D+ . . . +qm-1·Dm-1+qm·Dm over GF(2), the precoding input index set PI, the precoding output index set PO, the precoding frozen bit sequence h, or the state bit sequence t=[t0, t1, . . . , tm-1, tm] of length m+1. The precoding frozen bit sequence h is of length N−NPO and NPO is the size of the precoding output index set PO. Examples of implementation for the pre-transform can be found in Algorithms 7A-7G of Table 8.
In some embodiments, if an index i belongs to the precoding output index set PO, the bit with the index i (ui) of the pre-transform output bit sequence u is determined based on at least one of: the bit with index i (vi) of the pre-transform input bit sequence v, the generator bit sequence g=[g0, g1, . . . , gm], the generator polynomial g(D)=g0+g1·D+ . . . +gm·Dm over GF(2), the recursive feedback bit sequence q=[q0, q1, . . . , qm], the recursive feedback polynomial q(D)=90+q1·D+ . . . +qm·Dm over GF(2), and/or the state bit sequence t=[t0, t1, . . . , tm-1, tm]. The pre-transform can be implemented using example implementations given in Algorithms 7A-7G of Table 8. The pre-transform can comprise setting, by the first node, the bit with index 0 in the state bit sequence t to be the bit with index i (vi) of the precoding input bit sequence v, t0=vi, determining, by the first node, a summation bit s by the recursive feedback bit sequence q=[q0, q1, . . . , qm] (or the recursive feedback polynomial q(D)=q0+q1D+ . . . +qm·Dm over GF(2)) and the updated state bit sequence t=[t0, t1, . . . , tm-1, tm] as s=mod(Σj=0m qj·tj, 2), setting, by the first node, the bit with index 0 in the state bit sequence t to the summation bit s, t0=s, and determining, by the first node, the bit with index i (ui) of the precoding output bit sequence u by the generator bit sequence g=[g0, g1, . . . , gm] (or the generator polynomial g(D)=g0+g1·D+ . . . +gm·Dm over GF(2)) and the updated state bit sequence t=[10, 11, . . . , tm-1, tm] as ui=mod(Σj=0m qj·tj, 2).
Table 8 shows example Algorithms 7A-7G, which are example implementations for the pre-transform.
In some embodiments, if an index i does not belong to the precoding output index set PO, the bit with the index i (ui) of the pre-transform output bit sequence u is set to 0, e.g., as in Algorithms 7A and 7D. In some embodiments, if an index i does not belong to the precoding output index set PO, the bit with the index i (ui) of the pre-transform output bit sequence u is set to the bit with index i (vi) of the pre-transform input bit sequence v, e.g., as in Algorithms 7B and 7E. In some embodiments, if an index i does not belong to the precoding output index set PO, the bit with the index i (ui) of the pre-transform output bit sequence u is set to a bit in the precoding frozen bit sequence h, e.g., as in Algorithms 7C and 7F, wherein the precoding frozen bit sequence h is of length N−NPO and NPO is the size of the precoding output index set PO. In some embodiments, if an index i belongs to the precoding input index set PI, a right shift is performed on the state bit sequence t=[t0, t1, . . . , tm-1, tm] and the bit with index 0 (t0) in the state bit sequence tis set to 0 as follows, e.g., as in Algorithms 7A, 7B, 7C, and 7G.
In some embodiments, for any index i, a right shift is performed on the state bit sequence t=[t0, t1, . . . , tm-1, tm] and the bit with index 0 (t0) in the state bit sequence t is set to 0 as follows, e.g., as in Algorithms 7D, 7E, and 7F.
In Algorithms 7A-7G, N is the polar matrix size, m is the memory length, vi is the bit with index i in the pre-transform input bit sequence, ui is the bit with index i in the pre-transform output bit sequence, qk is the bit with index k in the recursive feedback sequence q=[q0, q1, . . . , qm] or the coefficient of the term with degree K in the recursive feedback polynomial q(D)=90+q1·D+ . . . +qm-1·D™-1+qm·Dm over GF(2), gk is the bit with index k in the generator sequence g=[g0, g1, . . . , gm] or the coefficient of the term with degree K in the generator polynomial g(D)=g0+g1·D+ . . . +gm-1·Dm-1+gm·Dm over GF(2).
Polar Transform: A polar transform comprises obtaining, by the first node, a polar transform input bit sequence; and determining, by the first node, a polar transform output bit sequence d=[d0, d1, . . . , dN-1]. Both the polar transform input bit sequence and the polar transform output bit sequence d are of length equal to the polar matrix size N. The polar transform output bit sequence d is determined by the first node by multiplying the polar transform input bit sequence u and the polar matrix G(N) of N rows and N columns, d=u·G(N), wherein the vector-matrix multiplication is performed over GF(2). In some embodiments, the polar transform input bit sequence is the precoding output bit sequence u=[u0, u1, . . . , uN-1] of length N as shown in
Rate Matching: A rate matching comprises obtaining, by the first node, a rate matching input bit sequence; and determining, by the first node, a rate matching output bit sequence. The rate matching input bit sequence is the polar transform output bit sequence d=[d0, d1, . . . , dN-1] of length N. The rate matching output bit sequence is the output bit sequence e=[e0, e1, . . . , eE-1] of length E. N is the polar matrix size. Specific examples of rating matching are shown in
In some embodiments, the rate matching determines the rate matching output bit sequence d corresponding to the rate matching input bit sequence e by the first node using the ordered rate matching index set R=<R(0), R(1), . . . , R(Nr−2), R(Nr−1)>, wherein Nr is the ordered rate matching index set size and Nr is equal to the minimum value between N and E, Nr=min(N, E); wherein N is N is the polar matrix size. E is the length of the rate matching output bit sequence or the length of the output bit sequence e. A first specific example is ek=dR(mod(k,N), k=0, 1, 2, . . . , E−2, E−1. A second specific example is ek=dR(k), k=0, 1, 2, . . . , E−2, E−1.
A third specific example is:
A fourth specific example is:
In some embodiments, the rate matching comprises an interleaving. The interleaving comprises obtaining, by the first node, an interleaving input bit sequence; and determining, by the first node, an interleaving output bit sequence d′=[d′0, d′1, . . . , d′N-1]. Nis the polar matrix size. The interleaving input bit sequence is the polar transform output bit sequence d=[d0, d1, . . . , dN-1] of length N. The interleaving output bit sequence d′=[d′0, d′1, . . . , d′N-1] is of length N.
In some embodiments, the interleaving determines the interleaving output bit sequence d′=[d′0, d′1, . . . , d′N-1] corresponding to the interleaving input bit sequence by an interleaver pattern J=[J0, J1, . . . , JN-2, JN-1] of length N as d′i=dJ
A first specific example of the interleaver pattern J=[J0, J1, . . . , JN-2, JN-1] is determined as:
π=[π0, π1, π2, π3, π4, π5, π6, π7, π8, π9, π10, π11, π12, π13, π14, π15, π16, π17, π18, π19, π20, π21, π22, π23, π24, π25, π26, π27, π28, π29, π30, π31]=[0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31] is a sub-block interleaver pattern and N is the polar matrix size.
A second specific example of the interleaver pattern J=[J0, J1, . . . , JN-2, JN-1] is that the relationship between the index i and the i-th element Ji in the interleaver pattern J satisfies the following quadratic form: Ji=mod(f1·i+f2·i2, N). Some examples of parameters f1 and f2 depending on the polar matrix size N are summarized in Table 9.
In some embodiments, the rate matching comprises an bit selection. The bit selection comprises obtaining, by the first node, a bit selection input bit sequence, and determining, by the first node, a bit selection output bit sequence. The bit selection output bit sequence is the output bit sequence e=[e0, e1, . . . , eE-1] of length E. In some embodiments, the bit selection input bit sequence is the polar transform output bit sequence d of length N, wherein N is the polar matrix size. Specific examples are shown in
A first specific example is that the bit selection determines the bit selection output bit sequence e=[e0, e1, . . . , eE-1] to be the first E bits in the bit selection input bit sequence d=[d0, d1, . . . , dv] as ek=dk, k=0, 1, 2, . . . , E−2, E−1. E is not greater than N.
A second specific example is that the bit selection determines the bit selection output bit sequence e=[e0, e1, . . . , eE-1] to be the last E bits in the bit selection input bit sequence d=[d0, d1, . . . , dN] as ek=dN-E+k, k=0, 1, 2, . . . , E−2, E−1. E is not greater than N.
A third specific example is that the bit selection determines the bit selection output bit sequence e=[e0, e1, . . . , eE-1] to be the repetition of bits in the bit selection input bit sequence d=[d0, d1, . . . , dN] as ek=dmod(k,N), k=0, 1, 2, . . . , E−2, E−1. E is not less than N.
In some embodiments, the bit selection input bit sequence is the interleaving output bit sequence d′ of length N, wherein N is the polar matrix size. Examples are shown in
A first specific example is that the bit selection determines the bit selection output bit sequence e=[e0, e1, . . . , eE-1] to be the first E bits in the interleaving output bit sequence d′=[d′0, d′1, . . . , d′N-1] as ek=d′, k=0, 1, 2, . . . , E−2, E−1. E is not greater than N.
A second specific example is that the bit selection determines the bit selection output bit sequence e=[e0, e1, . . . , eE-1] to be the last E bits in the interleaving output bit sequence d′=[d′0, d′1, . . . , d′N-1] as ek=d′N−E+k, k=0, 1, 2, . . . , E−2, E−1. E is not greater than N.
A third specific example is that the bit selection determines the bit selection output bit sequence e=[e0, e1, . . . , eE-1] to be the repetition of bits in the interleaving output bit sequence d′=[d′0, d′1, . . . , d′N-1] as ek=d′mod(k,N), k=0, 1, 2, . . . , E−2, E−1. E is not less than N.
Second Interleaving after Rate Matching
In some embodiments, the output sequence e=[e0, e1, . . . , eE-1] is further interleaved into a second output bit sequence f=[f0, f1, . . . , fE-1], wherein E is the length of the output sequence e.
Modulation after Rate Matching or Second Interleaving
In some embodiments, the output sequence e=[e0, e1, . . . , eE-1] is further modulated into a first output symbol sequence x=[x0, x1, . . . , XE/Qm−1] using one of the following modulation schemes: π/2 binary phase shift keying (π/2-BPSK), binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), quadrature amplitude modulation (QAM), phase shift keying (PSK), amplitude shift keying (ASK), or amplitude phase shift keying (APSK). Qm is the modulation order.
In some embodiments, the second output bit sequence f=[f0, f1, . . . , fE-1] is further modulated into a first output symbol sequence x=[x0, x1, . . . , XE/Qm−1] using one of the following modulation schemes: π/2 binary phase shift keying (π/2-BPSK), binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), quadrature amplitude modulation (QAM), phase shift keying (PSK), amplitude shift keying (ASK), or amplitude phase shift keying (APSK). Qm is the modulation order.
In some embodiments, the input bit sequence c comprises Lcrc cyclic redundancy check (CRC) bits determined by a cyclic generator polynomial g′ (D)=g′Lcrc·DLcrc+g′Lcrc−1·DLcrc−1+ . . . +g′2·D2+g′1·D+g′0 with coefficients over GF(2) and K-Lcrc payload bits.
In some embodiments, the input bit sequence c is determined by the first node by attaching Lcrc cyclic redundancy check (CRC) bit to a payload sequence of length K-Lcrc, wherein, the Lcrc CRC bits are determined by a cyclic generator polynomial g′(D)=g′Lcrc·DLcrc+g′Lcrc−1·DLcrc−1+ . . . +g′2·D2+g′1·D+g′0 with coefficients over GF(2).
Some additional examples of the disclosed coding scheme are described below.
In Example 1, a first node obtains an input bit sequence c=[c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18, c19, c20, c21, c22, c23] of length K=24. As shown in
and the precoding frozen bit sequence h is an all-zero vector.
After the rate matching, the first node transmits a signal including the output bit sequence e to a second node.
In Example 2, a second node receives a signal including an output bit sequence e=[e0, e1, e2, e3, e4, e5, e6, e7, e8, e9, e10, e11, e12, e13, e14, e15, e16, e17, e18, e19, e20, e21, e22, e23, e24, e25, e26, e27] of length E=28 sent by a first node. The second node determines an estimated bit sequence of an input bit sequence c=[c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18, c19, c20, c21, c22, c23] of length K=24. As shown in
In Example 3, a first node obtains an input bit sequence c=[c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18, c19, c20, c21, c22, c23] of length K=24. As shown in
a precoding input index set PI={0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28} with all elements from an ordered rate matching index set R=<R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), R(24), R(25), R(26), R(27)>=<0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28>, and
a precoding output index set PO={0, 1, 2, . . . , Rmax−1, Rmax}={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28} with all elements being non-negative integers not greater than the maximum value Rmax=28 in the ordered rate matching index set R.
The precoding is as follows (e.g., see also Algorithm 2E of Table 3).
(P(2))⊗5 is the 5-th Kronecker power of the matrix P(2).
After the bit selection, the first node transmits a signal including the output bit sequence e to a second node.
In Example 4, a first node obtains an input bit sequence c=[c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11] of length K=12. As in
The rate profiling output bit sequence vis obtained by setting the bits in the rate profiling output bit sequence v with indices belonging to the data bit index set Q being bits in the input bit sequence c while other bits in the rate profiling output bit sequence v is set to bits in the rate profiling frozen bit sequence f as follows.
The pre-transform output bit sequence u is determined as follows (e.g., see also Algorithm 7F of Table 8).
(P(2))⊗5 is the 5-th Kronecker power of the matrix P(2), B(32) is a bit-reversal permutation matrix with N=32 rows and N=32 columns.
After the rate matching, the first node transmits a signal including the output bit sequence e to a second node.
In Example 5, a first node obtains an input bit sequence c=[c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11] of length K=12. As in
The rate profiling output bit sequence v is obtained by setting bits in the rate profiling output bit sequence v with indices belonging to the data bit index set Q being the modulo-2 of a bit in the input bit sequence c and a bit in the rate profiling frozen bit sequence f and setting bits in the rate profiling output bit sequence v with indices not belonging to the data bit index set Q being bits in the rate profiling frozen bit sequence f as follows.
The pre-transform output bit sequence u is determined as follows.
(P(2))⊗5 is the 5-th Kronecker power of the matrix P(2), B(32) is a bit-reversal permutation matrix with N=32 rows and N=32 columns.
After the bit selection, the first node transmits a signal including the output bit sequence e to a second node.
In Example 6, a first node obtains an input bit sequence c=[c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11] of length K=12. As in
The rate profiling matrix F is
The rate profiling frozen bit sequence is f=[f0, f1, f2, f3, f4, f5, f6, f7, f8, f0, f10, f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, f26, f27, f28, f29, f30, f31]=[0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, 1].
The pre-transform matrix Tis
(P(2))⊗5 is the 5-th Kronecker power of the matrix P(2).
After the bit selection, the first node transmits a signal including the output bit sequence e to a second node.
In Example 7, a first node obtains an input bit sequence c=[c0, c1, c2, . . . , cK-2, cK-1] of length K. The input sequence c comprises Lcrc cyclic redundancy check (CRC) bits determined by a cyclic generator polynomial g′(D)=g′Lcrc·DLcrc+g′Lcrc−1·DLcrc−1+ . . . +g′2·D2+g′1·D+g′0 with coefficients over GF(2) and K-Lcrc payload bits. As in
Then, the pre-transform output bit sequence u is determined as follows (e.g., see also Algorithm 5A). If an index i does not belong to precoding output index set PO, the i-th bit ui in the pre-transform output bit sequence u is set to 0.
(P(2))⊗n is the 5-th Kronecker power of the matrix P(2).
For i=0, 1, . . . , N−2, N−1, the i-th bits of the interleaving output bit sequence d′ is equal to the Ji-th bit of the interleaving input bit sequence d. J=[J0, J1, . . . , JN-2, JN-1] is an interleaver pattern of length N determined by the sub-block interleaver pattern π and the polar matrix size N. The interleaver pattern J=[J0, J1, . . . , JN-2, JN-1] is a permutation of the integer sequence [0, 1, 2, . . . , N−2, N−1].
After the bit selection, the first node transmits a signal including the output bit sequence e to a second node.
In Example 8, a first node obtains an input bit sequence c=[c0, c1, c2, . . . , cK-2, cK-1] of length K. The input sequence c comprises Lcrc cyclic redundancy check (CRC) bits determined by a cyclic generator polynomial g′ (D)=g′Lcrc·DLcrc+g′Lcrc−1·DLcrc-1+ . . . +g′2·D2+g′ D+g′0 with coefficients over GF(2) and K−Lcrc payload bits. As in
a generator polynomial g(D)=g0+g1·D+ . . . +gm·Dm over GF(2) or equivalently a generator bit sequence g=[g0, g1, . . . , gm] with a memory length m, a precoding input index set PI, and
The pre-transform output bit sequence u is determined as follows (e.g., see also Algorithm 5B). If an index i does not belong to the precoding output index set PO, the i-th bit ui in the pre-transform output bit sequence u is set to the i-th bit vi in the pre-transform input bit sequence v.
After the rate matching, the first node modulates the output bit sequence e into a first output symbol sequence x=[x0, x1, . . . , XE/Qm−1] using the quadrature phase shift keying (QPSK) modulation and transmits a signal including the first output symbol sequence x to a second node, wherein, Qm=2 is the modulation order of QPSK.
Example settings for the precoding input index set PI, the precoding output index set Po and the ordered rate matching index set R in the above process are as follows,
Here, {0, 1, 2, . . . , Qmax−1, Qmax} denotes a set comprising all elements being non-negative integers not greater than the value Qmax and the value Qmax is the maximum value in the data bit index set Q,
R(0), R(1), . . . , R(E−2), R(E−1) are E distinct elements in the ordered rate matching index set R=<R(0), R(1), . . . , R(E−2), R(E−1)> of size E.
It is noted that
In some embodiments, the at least one index set comprises all non-negative integers that are equal to or smaller than Qmax, where Qmax is an element that has a largest value in a first index set (having K elements, Q being a subset of the set of bit indices that comprises all non-negative integers that are less than N. For example, Q is a data bit index set and
In some embodiments, the at least one index set is same as an ordered rate matching index set R=<R(0), R(1), . . . , R(Nr−2), R(Nr−1)>, where Nr=min(E, N).
In some embodiments, the at least one index set comprises all non-negative integers that are equal to or smaller than Rmax, wherein Rmax is an element that has a largest value in an ordered rate matching index set R with
In some embodiments, the output bit sequence consists of bits in an output bit sequence of the Polar transform with indices being in an ordered rate matching index set R=<R(0), R(1), . . . , R(Nr−2), R(Nr−1)>. The output bit sequence of the Polar transform has a length N, and Nr=min(E, N). For example, K=4, N=8, E=6, R=<R(0), R(1), R(2), R(3), R(4), R(5)>=<0, 1, 3, 4, 7, 5>, and a polar transform output bit sequence d=[d0, d1, d2, d3, d4, d5, d6, d7]. The output bit sequence e=[c0, c1, c2, c3, c4, c5]=[dR(0), dR(1), dR(2), dR(3), dR(4), dR(5)]=[d0, d1, d3, d4, d7, d5].
In some embodiments, the output bit sequence is determined based on an intermediate bit sequence (e.g., the sequence u), and wherein an i-th bit of the intermediate bit sequence is set to a predetermined value in response to an index i not being in the at least one index set. The predetermined value comprises 0, a value in a state bit sequence, or a value in a frozen bit sequence.
In some embodiments, the output bit sequence is determined based on an intermediate bit sequence (e.g., the sequence u), and wherein an i-th bit of the intermediate bit sequence is set to an i-th bit of a rate profile output bit sequence in response to an index i not being in the at least one index set. The rate profile output bit sequence is of length N.
In some embodiments, an j-th bit of an intermediate bit sequence (e.g., sequence u) is determined by a convolution bit sequence or a convolution polynomial in response to an index j being in the at least one index set. In some embodiments, the convolution bit sequence comprises a generator bit sequence g=[g0, g1, . . . , gm], or a recursive feedback bit sequence q=[40, 41, . . . , qm]. In some embodiments, the convolution polynomial comprises a generator polynomial g(D)=g0+g1·D)+. . . +gm-1·Dm-1+gm·Dm, or a recursive feedback polynomial q(D)=q0+q1D+ . . . +qm-1·Dm-1+qm·Dm.
In some embodiments, a state bit sequence t=[t0, t1, . . . , tm-1, tm] configured to store a convolution state is shifted in response to an index i being in the at least one index set. In some embodiments, the input bit sequence is represented as c, wherein the output bit sequence is determined based on an intermediate bit sequence (e.g., sequence u), and wherein an i-th bit in the intermediate bit sequence is determined based on a linear combination of elements c0, c1, c2, . . . , ci-1, ci in c.
In some embodiments, the output bit sequence is determined based on an intermediate bit sequence (e.g., sequence u), and wherein an i-th bit in the intermediate bit sequence is determined by a sub-sequence of the input bit sequence and a rate profile frozen bit sequence f=[f0, f1, . . . , fN-K−1] that is a binary sequence of length N-K. In some embodiments, the output bit sequence is determined based on an intermediate bit sequence (e.g., sequence u). An i-th bit in the intermediate bit sequence is determined based on a linear combination of bits in a rate profile output bit sequence with indices being in the at least one index set (e.g., the intersection of the input index set and the bit index set) and not greater than i, where the rate profile output bit sequence is of length N. For example, if PI={3, 4, 6, 7}, then 0-th bit in the intermediate bit sequence is determined by an empty set { }={0} n PI, 1-st bit in the intermediate bit sequence is determined by an empty set { }={0, 1}∩PI, 2-nd bit in the intermediate bit sequence is determined by an empty set { }={0, 1, 2}∩PI, 3-rd bit in the intermediate bit sequence is determined by an set {3}={0, 1, 2, 3}∩PI, 4-th bit in the intermediate bit sequence is determined by an set {3, 4}={0, 1, 2, 3, 4}∩PI, 5-th bit in the intermediate bit sequence is determined by an set {3, 4}={0, 1, 2, 3, 4, 5}∩PI, 6-th bit in the intermediate bit sequence is determined by an set {3, 4, 6}={0, 1, 2, 3, 4, 5, 6}∩PI, 7-th bit in the intermediate bit sequence is determined by an set {3, 4, 6, 7}={0, 1, 2, 3, 4, 5, 6, 7}∩PI.
In some embodiments, the input bit sequence is represented as c. The output bit sequence is determined based on an intermediate bit sequence (e.g., sequence u). An i-th bit in the intermediate bit sequence is determined based on a linear combination of elements c0, c1, c2, . . . , cM-2, CM-1 in c. M represents a number of elements that are shared by a first index set Q that is a subset of the set of bit indices and a second index set {0, 1, 2, . . . , i−1, i} that comprises all non-negative integers not greater than i. For example, for Q={3, 5, 7}, i=1, Q∩{0, 1, 2, . . . , i−1, i}={ } and M=0; for Q={3, 5, 7}, i=3, Q∩{0, 1, 2, . . . , i−1, i}={3} and M=1; for Q={3, 5, 7}, i=4, Q∩{0, 1, 2, . . . , i−1, i}={3} and M=1; for Q={3, 5, 7}, i=5, we have Q∩{0, 1, 2, . . . , i−1, i}={3, 5} and M=2, etc. The i-th bit in the intermediate bit sequence is based on a linear combination of elements v0, vi, v2, . . . , vi in v, where v having N bits is the input of a transform. For example, for K=3 and N=8, c=[c0, c1, c2], Q={3, 5, 7}, v=[v0, v1, v2, v3, v4, v5, v6, v7]=[0, 0, 0, c0, 0, c1, 0, c2]. v3, v5, v7 are set to c0, c1, c2, respectively, while other bits in v are all set to 0. The 0th bit in the intermediate bit sequence is based on a linear combination of element v0 (no element in c). The 1st bit in the intermediate bit sequence is based on a linear combination of elements v0, v1 (no element in c). The 2nd bit in the intermediate bit sequence is based on a linear combination of elements v0, vi, v2 (no element in c). The 3rd bit in the intermediate bit sequence is based on a linear combination of elements v0, v1, v2, v3 (or a linear combination of element c0). The 4th bit in the intermediate bit sequence is based on a linear combination of elements v0, v1, v2, v3, v4 (also a linear combination of element c0). The 5th bit in the intermediate bit sequence is based on a linear combination of elements v0, vi, v2, v3, v4, v5 (or a linear combination of elements c0, c1). The 6th bit in the intermediate bit sequence is based on a linear combination of elements v0, v1, v2, v3, v4, v5, v6 (or a linear combination of elements c0, c1). The 7th bit in the intermediate bit sequence is based on a linear combination of elements v0, v1, v2, v3, v4, v5, v6, v7 (or a linear combination of elements c0, c1, c2).
It will be appreciated by one of skill in the art that the disclosed techniques can be applied prior to the Polar transform in channel coding to improve transmission efficiency. For example, in some embodiments, a method for wireless communication can include applying a pre-transform operation prior to the Polar coding such that, as a result of the pre-transform operation (e.g., based on rate profiling to account for different payload sizes), a subset of bits having a length not equal to the Polar coding length N is coded to provide variable code lengths that are adaptive according to the payload size. As described in this patent document, the pre-transform operation can include shuffling based on indexes. Various possible pre-transform techniques are described with reference to
The disclosed and other embodiments, modules and the functional operations described in this document can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this document and their structural equivalents, or in combinations of one or more of them. The disclosed and other embodiments can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more them. The term “data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them. A propagated signal is an artificially generated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus.
A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
The processes and logic flows described in this document can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit). Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random-access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.
While this patent document contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.
Only a few implementations and examples are described, and other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.
This patent document is a continuation of and claims benefit of priority to International Patent Application No. PCT/CN2022/121869, filed on Sep. 27, 2022. The entire content of the before-mentioned patent application is incorporated by reference as part of the disclosure of this application.
Number | Date | Country | |
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Parent | PCT/CN2022/121869 | Sep 2022 | WO |
Child | 18926197 | US |