Patent Application
20070241384
The present invention relates to memory devices, in particular to non-volatile memory devices.
A floating gate non-volatile memory cell store information by storing an electrical charge on the floating gate. The floating gate is capacitively coupled to a control gate. In order to write to a cell, a potential difference is created between the control gate and some other region such as a source, drain, or channel region of the cell. The voltage on the control gate is capacitively coupled to the floating gate so as to cause a potential difference between the floating and the source, drain or channel region. As in the case of a write, the potential difference is used to place a charge on the floating gate.
As integrated devices become smaller and smaller, SoC (System on Chip) is becoming more and more common. An essential building block is the non-volatile memory. In order to provide the many functions of a SoC, many different function blocks must be integrated into one chip. However, today's SoC is primarily based on logic process, and the non-volatile memory is generally handled using a specialty process other than the logic process. The logic process is the dominant process and is popular with IC designers. Since the specialty processes are less common, it is often much more expensive and adds substantial costs to the development of the SoC device.
One solution is to fabricate entire SoC using the specialty process for the non-volatile memory devices. However, using this approach, the performance of the other logic devices is sacrificed for the benefit of ease in fabricating the non-volatile memory devices. Since many IC designers are not as familiar with the specialty processes as the traditional logic process approach, designs becomes more risky and complicated. A further disadvantage is the high cost and lagged support. Since the specialty processes are not widely used within the semiconductor fabrication community, lagged technical support is often associated with the specialty processes which can cause delays in developing the SoC.
Many approaches have been introduced to solve the issue of conformity with non-volatile memory devices and the traditional logic process. Designers have adopted to using a pair of pmos (positive channel metal oxide silicon) and nmos (negative channel metal oxide silicon) devices that are coupled with both of their gates connected and floated. The floated poly gate is used to store charge. Program and erase functions are enabled thru mosfet tunneling and other physical effects. However, in order to avoid a latch-up during high-voltage operation between pmos and nmos devices, this memory cell has to be made large. In addition, capacitance ratio is determined by the nmos and pmos capacitances. Since nmos and pmos work in different modes, that is, one is in accumulation mode, and the other is in inversion mode, they produce non-linear capacitance. The non-linear capacitance effects of the nmos and pmos devices require additional circuitry and special attention to achieve desired linear behavior in the memory devices.
Others have used soft and hard breakdown effects to generate a series of different resistance so that stored value can be differentiated and recognized. However, due to difficulty in controlling the breakdown and unknown effects in the breakdown process, those devices have very limited times of programmability.
Accordingly, there is a need for a non-volatile memory cell design that is compatible with well-known proven logic process which overcomes the disadvantages of earlier attempts while maintaining compactness and reliability in the memory cell.
The present invention discloses methods and apparatuses for a non-volatile semiconductor memory device. In accordance with an embodiment, the non-volatile memory structure takes advantage of capacitance between metal areas on one or more metal layers that may be used for interconnects. The capacitance formed from the one or more metal areas on one or more metal layers has advantages of being more linear and can be formed using well-known proven process techniques of fabrication. Accordingly, embodiments of the present invention disclose a non-volatile semiconductor memory device having multiple layers to provide a source, a drain, and a floating gate, comprising a plurality of metal areas on one or more metal layers to provide interconnects to the non-volatile memory wherein at least two of the plurality of metal areas on one or more metal layers are configured to provide a capacitor having a capacitance that is capacitively coupled to the floating gate.
In accordance with another aspect of the present invention, the non-volatile semiconductor comprise a via coupling the at least two of the plurality of metal areas on one or more metal layers to form the capacitor.
In accordance to yet another aspect of the present invention, at least two of the plurality of metal areas that provide the interconnects to the non-volatile memory are electrically isolated from the at least two of the plurality of metals areas that form the capacitor.
Other aspects and advantages of the present invention will become apparent to those skilled in the art from reading the following detailed description when taken in conjunction with the accompanying drawings.
The present invention will now be described in detail with reference to preferred embodiments as illustrated in the accompanying figures. During the description, specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without some or all of the specific details. In order to not unnecessarily obscure the present invention, some well know process steps or structures may not have been described in detail.
In one embodiment, the present invention relates to semiconductor memories, and more particularly to non-volatile memories and structures of such which provide efficient fabrication and functionality of the memories using preferred logic process of manufacturing. The present invention takes geometric advantage of inherent layering of materials at reduced ratios in sub-micron process.
In modern device and advanced process technology, coupling capacitance between metals is becoming a majority part of the overall capacitance, while the weight of plate capacitance becomes less. For example, minimal metal separation is 0.3 um on a typical 0.25 um technology, and this is 0.23 um on a typical 0.18 um. It makes coupling capacitance between the same layer metals with minimal separation increase 30%, while gate capacitance (the same area) over the generation is kept the same, that is, gate capacitance for minimal geometry becomes smaller. Overall, it makes coupling capacitance between the same layer metals overtake values from gate capacitor and a flash cell with such a structure has the correct capacitance ratio for proper memory operation, such as, program, erase, and read.
Accordingly, in accordance to an embodiment of the present invention, a pmos device works as programmable cell, and a metal-insulator-metal works as coupling capacitor. In practice, the coupling capacitor is typically set to be 5-10 times of the capacitance of the programmable cell. In a present embodiment, the programmable cell is a PMOS device based on standard logic process. In general, standard logic process offers at least two types of devices: core devices and I/O devices. I/O devices have thicker oxides and operate at higher voltages. To use the I/O device for programmable cells, oxide thickness of programmable cells is typically more than 70 Angstroms. Operating the programmable cells at 3.3V for I/O device logic process meets the standard logic requirement. However, in order to keep devices small, for sub-micron device, for example, 0.18 um and 0.13 um, line width of a thin device could be used for such purpose with a process step to increase oxide thickness of such device to that of I/O device cell. Accordingly, the coupling capacitor or control gate for the programmable memory cell can be fabricated using the standard logic process.
The features and advantages of the present invention can be better understood with reference to the figures and the description which follow. In accordance to a present embodiment,
Since the capacitance is formed by the coupling of two or more metal areas on one or more metal layers, it is scalable with technology shrinkage. In addition, the metal layer to metal layer capacitor has better linearity and stability than mos capacitances.
In accordance to another embodiment of the invention,
In accordance to another embodiment of the present invention, the diffusion layer 104, 204, 404, or 504 is used to provide the interconnects to the memory cells including the bit lines. In this case, the metal layers can be better isolated from the interconnects and the metal layers can be more fully used to provide capacitance.
As can be appreciated from the foregoing, the disclosed non-volatile memory cell takes advantage of shrinking geometries and the inherent capacitance associated with close proximity of the metal layer to provide control gate capacitance for controlling the charge on the floating gate. Although the present invention has been described using pmos and nmos transistors, other transistors technologies are equally applicable.
While the invention has been described in details with reference to the present embodiment, it shall be appreciated that various changes and modifications are possible to those skilled in the art without departing the spirit of the invention. Thus, the scope of the invention is intent to be solely defined in the accompanying claims.
