Patent Application
20070009067
1. Field of the Invention
The present invention relates generally to reducing processor generated interference with radio frequencies used in a wireless device, and, more particularly, to advantageous techniques for selecting a processor frequency for operating a processor or other peripherals based on the radio frequencies presently utilized or planned to be used by the wireless device.
2. Relevant Background
Common radio frequency bands for today's wireless communication systems range from around 400 MHz to over 2.4 GHz. Within this range, frequency sub-bands are defined for wireless communication such as the cellular band, the global positioning system (GPS) band, the personal communication service (PCS) band, the international mobile telecommunication (IMT) band, and the general use frequency band which includes the Bluetooth® communication protocol. A wireless device typically has radio circuits which communicate in one or more of these radio frequency bands.
The speed at which microprocessors operate in wireless devices continues to increase. It is expected that this trend of increasing processor speed will continue in order to satisfy the demand for additional functions on the wireless device, such as television applications, high intensity video gaming applications, or the like.
As the speed of microprocessors increases, power consumption on the wireless device increases as well. In order to address power consumption issues, some conventional processors have been developed that employ dynamic frequency scaling which means that the processor can adjust its clock rate higher or lower over. This adjustment is commonly performed in response to changes in the of work load of the processor. With a high work load, the processor runs at the higher clock rate to meet the needs of the high work load. However, the power consumption of the processor running at the higher clock rate is higher than the power consumption when the processor is running at a lower clock rate to handle a lighter work load.
Classic interference reduction techniques such as filtering, static processor clock selection and physical shielding are commonly used to reduce processor interference with radio frequencies by the device. However, these techniques are static in nature because they require careful frequency planning at design or provisioning time to preclude use of operating a processor at radio frequencies. Accordingly there is a need in the art for flexible techniques to allow adaptive energy consumption while still allowing a wide range of processor frequencies to be utilized without undue interference of radio frequencies.
As the speed of microprocessors increase and those increased speeds enter the frequency range of the radio frequency band, running microprocessors at speeds within the radio frequency band may cause interference with a wireless device's radio circuits. Furthermore, the harmonic frequencies resulting from microprocessors running at speeds within the radio frequency band may also cause interference with the radio circuits.
Moreover, embodiments of the present invention recognize a need for methods, apparatus, and computer readable medium for dynamically determining processor frequencies to operate a processor or other peripheral device in a wireless device to reduce interference on radio frequencies used by the wireless device. The interference to be reduced may include interference signals caused by the operating speed of the processor, clock signals driving peripheral devices, and the harmonic frequencies generated from signals generated at a processor frequency. By utilizing knowledge of the radio frequencies in use or those frequencies that might be used in dynamically determining a processor frequency for a processor or other peripheral, an embodiment of the present invention controls processor operation so that it operates at frequencies and generates harmonics within the radio frequency range during a time when those corresponding radio frequencies are not being used by a radio in the wireless device. This runtime interference avoidance technique provides frequency scaling processors more freedom in the selection of operating frequencies thereby allowing better optimization of throughput versus energy consumption.
To such ends, an embodiment of the present invention includes a method having the steps of determining at least one radio frequency used in the wireless device and assigning an interference factor to a potential processor frequency corresponding to at least one radio frequency used in the wireless device. The method further includes the step of selecting a first processor frequency other than the potential processor frequency to avoid interference with the at least one radio frequency.
A more complete understanding of the present invention, as well as further features and advantages of the invention, will be apparent from the following Detailed Description and the accompanying drawings.
The present invention will now be described more fully with reference to the accompanying drawings, in which several embodiments of the invention are shown. This invention may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
It will be appreciated that the present invention may be embodied as methods, systems, or computer program products. Accordingly, the present invention may take the form of a hardware embodiment, a software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product on a computer-usable storage medium having computer-usable program code embodied in the medium. Any suitable computer readable medium may be utilized including hard disks, CD-ROMs, optical storage devices, flash memories, or magnetic storage devices.
Computer program code which may be compiled, assembled, predecoded after compiling or assembly, or the like in accordance with the teachings of the invention may be initially written in a programming language such as C, C++, native Assembler, JAVA®, Smalltalk, JavaScript®, Visual Basic®, TSQL, Perl, or in various other programming languages. Program code or computer readable medium refers to machine language code such as object code whose format is understandable by a processor. Software embodiments of the invention do not depend upon their implementation with a particular programming language. When program code is executed, a new task which defines the operating environment for program code is created.
In
The radio frequency table will be discussed in further detail in connection with the discussion of
During operation, the radio frequency controller 230 retrieves a transmitting frequency and a receiving frequency from memory 240. The memory 240 may also contain allowable frequencies which have been dynamically determined based on the available frequencies for a region in which the wireless device 200 operates. For example, a wireless device having a global position system may sense its region of operation and retrieve a transmitting and receiving frequency from the memory 240 which corresponds to the sensed region of operation. The radio frequency controller 230 communicates both the transmitting and receiving frequencies to the oscillator circuit 220. The radio frequency controller 230 may suitably be implemented in appropriate code according to the teachings of the invention running a microprocessor.
The oscillator circuit 220 generates first and second clock signals corresponding to the retrieved transmitting and receiving frequency, respectively. The oscillator circuit 220 sends the first clock signal to the hardware transmission circuit 215 and the second clock signal to the hardware receiver circuit 225. In general, clock signals are typically square waves. Consequently, the first and second clock signals are susceptible to interference with other signals having the same frequency and signals having frequencies equal to their odd harmonics.
The hardware transmission circuit 215 may suitably be a known radio frequency transmission circuit which steps up the strength of a carrier signal at the frequency defined by the first clock signal. The carrier signal carries baseband information produced by the wireless device 200 to define an outgoing radio frequency signal. For ease of illustration, the baseband connections to the hardware transmission circuit 215 are not shown. The combiner 210 accepts the outgoing radio frequency signal from the hardware transmission circuit 215 and couples it to antenna 207.
When receiving a signal through antenna 207, the combiner 210 couples the received signal to the hardware reception circuit 225. The hardware reception circuit 225 removes the carrier signal from the received signal to output the baseband signal to the software receiver module 235. The hardware reception circuit 225 may suitably be a high gain circuit for receiving a low power incoming signal and stepping up the strength of the baseband signal. The software receiver module 235 decodes the baseband signal to provide the information content to the radio frequency controller 230 for subsequent consumption. Furthermore, the software receiver module 235 may optionally analyze the decoded information to determine whether the transmitting or receiving carrier frequencies will change in the near future as a result of communicating with an external device such as a base station or the like. For example, a base station may communicate one or more supported frequencies over which the wireless device may choose to communicate. The software receiver module 235, in this example, determines those suggested frequencies and communicates those suggested frequencies to the radio frequency controller 230. The radio frequency controller 230 may write those suggested frequencies into a radio frequency table in memory 240, may utilize those suggested frequencies by communicating them to the radio oscillator circuit 220, or both. It should be noted that the radio frequencies used by a wireless device may hop from one frequency to another with regularity.
The baseband processing component 250 includes a processor clock controller 255, a clock generator 275, an allowance table 260 stored in memory 270, a processor 265, and an operating system 268 which provides a platform upon which software tasks 280 may run. The term “operating system” as used herein may include known operating systems, kernels, simple schedulers, and the like. The processor clock controller 255 couples to the radio frequency controller 230, the allowance table 260, the clock generator 275 and the processor 265. The clock generator 275 further couples to processor 265. Software tasks 280 couple to the operating system 268.
The processor clock controller 255 is typically a software component that accepts status information from radio frequency controller 230. The status information may include current frequencies being utilized by the radio 205, candidate frequencies which may be utilized by the radio 205, a particular use by the radio 205 for these candidate frequencies, and the bandwidth associated with each of these reported frequencies. The status information may optionally include other information such as current signal strength, signal-to-noise ratio (SNR) of the candidate frequencies, and the like. The processor clock controller 255 utilizes the status information and the allowance table 260 to determine at what frequency processor 265 will operate. The allowance table 260 includes potential processor frequencies or clock speeds at which processor 265 or other peripheral device may operate. The processor clock controller 255 modifies the potential processor frequencies if the frequencies in the status information correspond to frequencies in the allowance table 260. The processor clock controller 255 may also modify the potential processor frequencies further if the harmonics of the frequencies in the status information correspond to frequencies in the allowance table 260. A more detailed description of the allowance table 260 and these modifications are provided in connection with the discussion of
The processor clock controller 255 from time to time evaluates the work load offered by software tasks 280 to determine a processor frequency at which to operate processor 265 to meet the needs of the offered work load while minimizing battery consumption. For example, this evaluation may occur at 50 millisecond intervals. The work load on the processor 265 is dependent on the number of tasks in software tasks 280 and the amount of instructions which are ready to execute in each task. A software task may include, for example, displaying video on a screen, rendering video game graphics, or the like. Increasing the operating speed of processor 265, increases the speed of execution of software tasks 280 at the expense of higher power consumption.
This evaluation also includes selecting a processor frequency from the allowance table 260 to reduce interference effects potentially caused by operating processor 265 at a selected frequency. In this way, the processor clock controller 255 selects a frequency at which processor 265 will operate based on both radio frequencies used to reduce interference and offered load information to balance power consumption. The processor clock controller 255 communicates this selected frequency to the clock generator 275. The clock generator 275 generates a clock signal based on the selected frequency and drives processor 265 or other device peripherals with the generated clock signal. It is noted that each peripheral may or may not have its own frequency scaling processor. Furthermore, each peripheral may be driven by a clock signal having a different frequency.
Alternatively, the processor clock controller 255 may provide entries of the allowance table 260 as input to a known dynamic frequency selection technique which selects a frequency based only on work load. In this alternative, the processor clock controller 255 provides potential processor frequencies which have already excluded used radio frequencies without having to make a selection.
Since processor frequency selection is dynamic and is made from time to time, the processor 265 may have to change from one operating frequency to a newly selected second operating frequency. One approach for moving from one operating frequency to another includes turning off the current clock rate followed by turning on the selected clock rate. A second approach includes slewing the clock rate in incremental steps from the first clock rate to the selected clock rate. A more detailed description of slewing the clock rate to reduce interference with used radio frequencies is provided in connection with the discussion of
It is noted that the radio frequency controller 230 and the processor clock controller 255 may be embodied in code and execute on the same processor 265 or different processors. In such a software embodiment, communications between the radio frequency controller 230 and the processor clock control 255 may include many known software techniques such as remote procedure call (RPC), inter-task message passing, common variable access, or the like. Alternatively, the radio frequency controller 230 and the processor clock controller 255 may be embodied in a hardware circuit or firmware. In this alternative embodiment, communications between the radio frequency controller 230 and the processor clock control 255 may include many known hardware or firmware techniques including setting and reading a status register or registers, passing a stream of serial information, or the like.
Two main phases of operation, a maintenance phase and a selection phase, involve the allowance table 260. During the maintenance phase, the processor clock controller 255 receives information corresponding to the radio frequency table 300. Alternatively to receiving an entire table's worth of information, the processor clock controller 255 may receive only the used frequencies and their associated uses. The processor clock controller 255 transforms the used frequencies using bandwidth information and harmonic multipliers to determine corresponding processor frequencies in column 410A of allowance table 260. The bandwidth information may be passed as separate parameters in a status information message from the radio frequency controller 230. Harmonic multipliers may be determined by the particular use of a radio frequency or may be pre-defined. The processor clock controller 255 then assigns an interference factor associated with the determined frequencies based on the particular usages of the corresponding used radio frequencies.
For example, referring to row 315 of radio frequency table 300, frequency F1 is currently being used for cellular reception of a voice signal. When the processor clock controller 255 analyzes F1 and its corresponding use, the processor clock controller 255 determines, for example, that the 5th and 7th harmonics of F1 should be considered. The processor clock controller 255 assigns a weighted interference factor of 7 to F1, F5, and F7 as shown in allowance table 260. This weight factor is utilized during the selection phase described below. It should be noted that the processor clock controller 255 may assign weights to the harmonic frequencies F5 and F7 which are different from the weight assigned to F1. Such a varying weight assignment is particularly useful when the impact of interference on a harmonic varies in level depending on the degree of the harmonic.
By way of another example, referring to row 335 of the radio frequency table 300, frequency F4 is currently being used for cellular transmission of a voice signal. When the processor clock controller 255 analyzes F4 and its corresponding use, the processor clock controller 255 assigns a weight factor of 2 to F4 as shown in the allowance table. The lower weight indicates that depending on the strength of the transmission signal, some interference may be tolerated. For example, if the battery level of a wireless device is high and a strong cellular transmission signal is currently being produced, the likelihood of interference with the transmission signal is reduced. Thus, a lower weight factor is assigned.
Assignment of a weighted interference factor to a processor frequency may include many considerations including whether a corresponding radio frequency is sufficiently shielded by a particular hardware design, whether a harmonic of a corresponding radio frequency is sufficiently shielded by a particular hardware design, strength of a signal, a tolerance for noise of the signal, whether a digital signal is involved, quality of service requirements for the wireless device, and the like. If, for example, the strength of signal is considered, the stronger the strength of the used radio frequency, the lower an interference factor would be assigned to the corresponding processor frequency. If, for example, a digital signal is being communicated is considered, the effectiveness of error correction coding of the digital signal may be analyzed when assigning a weighted interference factor.
The described embodiment of the present invention allows selection of a processor frequency which corresponds to a radio frequency if there are other mechanisms in the wireless device that sufficiently protect that radio frequency from interference. Such leveraging of other techniques allows the embodiment of the invention to be advantageously flexible in not precluding frequencies unnecessarily.
During the selection phase, the processor clock controller 255 determines that a new processor frequency needs to be selected. This determination may be done from time to time or on a periodic basis such as every 50 milliseconds. In making the selection, the processor clock controller 255 considers the current offered work load and balances battery consumption for operating the processor 265 to meet the needs of the offered work load. In so doing, the processor clock controller 255 accesses a system tolerance level. The system tolerance level may suitably be a register or software variable which aggregates operating characteristics of the wireless device such as the current level of battery, work load, and the like. In deciding whether to select a frequency, the processor clock controller 255 compares an interference factor associated with a processor frequency in the allowance table 260 with the system tolerance level. If the interference factor is greater than the system tolerance level, the corresponding processor frequency is to be avoided. Otherwise, the corresponding frequency may be selected.
For example, if the processor 265 was operating at frequency F8 and the processor clock controller 255 determines that the clock rate of processor 265 may be decreased because the desired work load is being met, the processor clock controller 255 would evaluate the interference factor of the next lower frequency, F7, for example. In evaluating whether to select F7, the processor clock controller 255 compares the interference factor 7 with the current system tolerance level. If the interference factor is greater than the current system tolerance level, F7 would not be selected. Assuming that the current system tolerance level is 6, the processor clock controller 255 would then consider F6 and find that the interference level associated with F6 is less than the current system tolerance level. Thus, the processor clock controller 255 would select F6.
Using this technique, when the system tolerance level is set to 0, in the extreme situation, only a radio frequency that has a 0 interference factor will be selected. This setting may occur when the battery level is high but the receiving signal strength of the radio is low. When the system tolerance level is set to 10, in the other extreme situation, any frequency may be selected. This setting may occur when the battery level is low and all signals used by the radio are running at a high power level to give preference to battery energy conservation.
It should be recognized that another embodiment of the invention may include an interference factor that contains a binary value. If the interference factor has one value, the processor clock controller 255 may select the corresponding processor frequency. If the interference factor has the other value, the processor clock controller 255 must not select the corresponding processor frequency. When an interference factor contains a binary value, the system tolerance level described above is not utilized.
Although this discussion is in terms of frequency, it should be recognized that the teachings of the invention are not limited to avoiding particular frequencies but may also select a processor frequency which avoids frequency bands associated with a particular radio frequency as well.
Frequency spectrum 510B illustrates the potential processor frequencies 535 at which processor 265 or other peripheral device may operate. The potential processor frequencies 535 are specified in an allowance table, such as the allowance table 260. It should be noted that the range of potential frequencies may expand as the technology of frequency scaling processors progress. Furthermore, to save power consumption, processor 265 may employ voltage scaling which means operating the processor at lower voltage levels at the low frequency clock rate and higher voltage levels at the higher frequency clock rate. The more potential operating frequencies available, the more flexibility the processor clock control 255 has in selecting an operating frequency which meets processor throughput requirements while reducing power and reducing interference with used radio frequencies.
Frequency spectrum 510C illustrates the radio frequencies 545A used by the wireless device 200 and the selected frequency 545B for operating processor 265. First and second harmonic frequencies 555A and 555B of selected frequency 545B are also shown. Note that the selected frequency 700 MHz and its harmonics, 1400 MHz and 2100 MHz and so on, do not interfere with used radio frequencies 545A.
Rather then stepping between two operating frequencies, the operating frequency is slewed to selected interim frequencies which reduce interference of used radio frequencies. In the depicted example of
At step 740, the method 700 selects a processor frequency from the allowance table which satisfies a system tolerance level, thus, ensuring that operating a processor or generating a clock signal at the selected frequency will not unacceptably interfere with radio frequencies in use or might be used in the near future. Step 740 may also integrate with conventional techniques of selecting operating speeds based on offered work load to a processor. To this end, step 740 may provide a list of frequencies extracted from the allowance table that have an interference factor of 0 to a conventional work load technique from which the conventional technique chooses to run a processor. Alternatively, step 740 may provide a list of frequencies that satisfy the system tolerance level to the conventional work load technique from which the conventional work load technique chooses to run a processor. By step 740 providing the list of frequencies that can be used in accordance with the teachings of the invention to a conventional technique, the conventional technique is enhanced to select a processor frequency which best matches the work load of the processor and, additionally, avoids undue interference with used radio frequencies.
While the invention is disclosed in the context of embodiments, it will be recognized that a wide variety of implementations may be employed by persons of ordinary skill in the art consistent with the above discussion and the claims which follow below.
