Patent Application
20070058766
This invention relates generally to the transmitting and receiving of serial data, and more specifically, to methods and apparatus for recovering serial data received from an external circuit.
Whenever serial data is transmitted from one module to another, for example, from one circuit to another, it is typically transmitted without an accompanying clock transmission for data synchronization. In such a scenario, a substitute clock signal is generated at the receiving module in order to clock in the serial data to the module. If the rate of the serial data is at a known frequency, for example, as is the case with a synchronous data format, then a clock that is approximately the same frequency as the serial data can be provided through another source. With one clock being generated at the “sending” module, and another clock being generated at the “receiving” module, it is typical that these clocks are not exactly the same frequency, resulting in a shifting, or non-stable, phase relationship between the transmitted data, and the clock being utilized to clock in such data. The clock at the receiving module, along with a phase aligner, are utilized to recover the data in the absence of a fixed data/clock phase relationship.
At least one known phase aligner requires four phased clock inputs. The four clock inputs are separated from each other by a quarter of a clock cycle. For reference purposes, the first clock is considered to be at a 0° phase shift, the second clock is considered to be at a 90° phase shift, the third clock is considered to be at a 180° phase shift, and the fourth clock is considered to be at a 270° phase shift. Extra care is taken during the design phase as well as for the placement and routing of signals for these phase aligners so that the phase relationship, rising/falling edge, and clock duty cycle timing of the clock signals is tightly controlled. If these parameters are not tightly controlled, the phase aligner may not be able to correctly track the data through the various phases, especially if the duty cycle of the data is not optimal. Also, since timing of these clock inputs may be subjected to variations in operational temperature and voltage conditions, as well as process variations in the manufacturing of the die on which these circuits are formed, the performance of such phase aligners may become degraded.
The above described phase aligners are typically utilized along with a small FIFO buffer (e.g., an eight bit buffer), a phase detector, and a phase locked loop (PLL) to provide a type of data recovery and to match the PLL clock to the data rate. Various clock and data recovery (CDR) circuits are used extensively in the industry, especially in high-speed SONET applications. A CDR circuit could be used, instead, to recover both the data stream and the clock signal. However, CDR circuits are much larger, more complex, and more expensive than the above described phase aligner approach.
CDR circuits are able to provide low jitter data recovery for high bandwidth data, however, in applications where high speed and jitter is not an issue, utilizing a phase aligner is the preferred solution.
A phase alignment device for alignment of phase between a data signal and a clock signal is provided. The phase alignment device comprises a signal generator generating an enable signal, based on the selected phase reference signal, configured to control shifting of the data signal through an external data buffering device, a reference signal module generating phase reference signals based on the clock signal, the phase reference signals differing in phase from one another, and a data sampler identifying a reference point in the data signal. The phase alignment device further comprises a phase capture module identifying one of the phase reference signals closest in phase to the reference point in the data signal as a selected phase reference signal.
A method for recovering serial data from a signal in the absence of a fixed data and clock phase relationship is also provided. The method comprises generating phase reference signals based on a clock signal, the phase reference signals differing in phase from one another, identifying a reference point in a data signal, and identifying one of the phase reference signals closest in phase to the reference point in the data signal as a selected phase reference signal. The method also comprises generating an enable signal based on the selected phase reference signal, and using the enable signal to control shifting of the data signal through an external data buffering device.
A phase alignment device for alignment of phase between a data input signal and an externally generated clock signal, where the clock signal has a frequency that is higher than a frequency of the data signal is also provided. The phase alignment device comprises a data sampler comprising a circuit that identifies a reference point in the data input signal and shifts the data input signal to an aligned data output of the phase alignment device based on the clock signal, and a reference signal module generating phase reference signals based on the clock signal, the phase reference signals differing in phase from one another. The phase alignment device further comprises a phase capture module comprising logic that identifies the phase reference signal closest in phase to the identified reference point in the data input signal, a signal generator outputting an enable signal to an external device, the enable signal causing the external device to receive as an input the aligned data output of the phase alignment device.
The tri-phase aligner 20 aligns the input data 24 using a triple-rate clock signal 22, which as the name implies, is a clock signal that is substantially three times the frequency of the input data 24. The clock signal 22 is three times the frequency of the input clock 12, which results in multiple opportunities to align the data with the clock 12 in phase. Within the tri-phase aligner 20, the input data 24 is sampled using the triple-rate clock signal 22, and then an edge detection circuit (not shown in
In one embodiment, the tri-phase aligner 20 selects the phase that occurs 120° after the rising edge of the input data 24. However, whenever the input data 24 is transitioning across one of the boundaries of the three phases generated within the tri-phase aligner 20, the tri-phase aligner 20 is configured to select a new phase (one of the other two phases. In one embodiment, for one data bit cycle, the selected phase is either the 0° or the 240° phase. In the embodiment, the 0° or the 240° phase is selected because the change in the rising edge of the samples of the input data 24 takes place before the new phase is selected. Once a new phase has been selected, it will remain in effect until the next rising edge of the input data 24.
The block diagram of
The tri-phase aligner 100 further includes data delay flip-flops 112, 114, and 116 which, along with AND gate 118, are configured to resynchronize data in signal 120 to the triple rate clock 110. Resynchronized data signal 130 is then passed on as an aligned data output, to be received by FIFO 40 (shown in
The triple enable register flip-flop 140 generates a triple enable output 142 which is used by the aligner FIFO 40 to enable when the aligned data output signal 130 is to be clocked into the FIFO 40, based on the triple rate clock 110. In one embodiment, the tri-phase aligner 100 generally centers the triple enable output 142 in the middle phase (e.g., 120 degrees) of the aligned data output 130, however, when the data transitions from being in phase with one phase of the triple rate clock 110 to being in phase with an earlier or later phase of the clock 110, then the tri-phase aligner 100 will select either of an earlier or later phase so that the triple enable output 142 is resynchronized with the aligned data output 130. Further, when the data transitions from one phase to the next earlier phase, such as from phase three to phase two (e.g., 240 degrees to 120 degrees), then an extra pulse is generated by triple enable register flip-flop 140, along with gates U16 and U17, to ensure that all the data bits are clocked into the FIFO 40 during this transition. Without the extra pulse, one data bit would be lost, since the choice to transition to the new phase is made the next clock cycle after the new phase enable has occurred.
Signal H is the enable signal output by flip-flip 140 (shown in
Tri-phase aligner 100 is much simpler than at least some previous phase aligner designs and the size of tri-phase aligner 100 is about a third of the size of these known previous designs. Tri-phase aligner 100 further does not require the same type of tight control that the four phase clock based phase aligners require. Specifically, the triple rate clock 110 does not require that its propagation delay, or its rising/falling edge, matches the timing of another clock, as some phase aligners do. Also, tri-phase aligner 100 is synchronous and does not use internally generated clocks. Therefore, aligner 100 can be synthesized, placed, and routed along with the other circuitry within an AS1C or FPGA design, or fabricated with discrete logic, without any special considerations. Previous phase aligner designs required that the aligner be synthesized, placed, and routed as a separate logic block so as to tightly control the timing of the phase clocks.
While the embodiments described herein refer specifically to a tri-phase arrangement with a triple rate clock, other embodiments are contemplated to be within the scope of the disclosure. Specifically, the rate of the clock may be increased to a different multiple of the data rate, for example, five times the data rate, and an aligner circuit supporting such a clock rate would incorporate analogous circuitry, for example, five phase enable flip-flops, five data delay flip-flops, and five data storage flip-flops along with similarly configured logic as illustrated in
While the invention has been described in terms of various specific embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the claims.
