For the purposes of illustrating the various aspects of the invention, there are shown in the drawings forms that are presently preferred, it being understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.
A general presentation of the concepts pertinent herein is presented to aid in describing one or more embodiments of the present invention. For an inverter having “L” stages, and having a size ratio of “N” between the last stage and the first stage thereof, existing systems typically include a size ratio between successive stages established according to the following formula:
Rm-(m-1)=N(1/L-1)),
where “m” represents a given stage number within the inverter, and “m−1” represents the stage immediately preceding the given stage number.
In one or more embodiments of the present invention, it is proposed to change the size ratio between at least two adjacent inverter stages from that conventionally practiced. Specifically, the proposed “m” stage to “m−1” stage size ratio may be represented by the relationship:
The foregoing relationship is proposed because simulation results indicate that changing the relationship as indicated may beneficially reduce duty cycle distortion arising from clock signal propagation through an inverter circuit.
It is noted that slew rate and delay time are parameters of inverter circuits to be kept in mind while optimizing the parameter of duty cycle distortion. Accordingly, the optimization of inverter stage size ratios to minimize duty-cycle distortion is preferably conducted subject to the constraint that the parameters of slew rate and delay time be kept within reasonable bounds.
We turn now from the general case to the more specific case of three-stage inverters. Simplifying the formula provided above, for a three-stage inverter, conventional size ratios between the second stage and first stage and that between the third stage and the second stage are provided by the formula R2-1=R3-2=N1/2. In the foregoing, R2-1 is the size ratio between the second and first stages, and R3-2 is the size ratio between the third and second stages.
Recalling the previously mentioned simulation results, it is noted here, specifically with respect to three-stage inverters, that simulation results have indicated that duty cycle distortion improves where R2-1 is less than N1/2. Accordingly, attention is directed to
In one or more embodiments, the ratio of the FET size of the third stage 130 to that of the first stage 110 is equal to “N.” While one or more embodiments of the present invention are described as including FETs, the invention is not limited to the use of this type of transistor. In some cases, the term “size ratio” is applied to the ratio of sizes of FETs in different stages of inverter circuit 100. However, the term “size ratio” is also applied more generally to a ratio of sizes of successive stages of inverter circuits, as the present invention is not limited to the use of FETs.
In accordance with the goal of determining a desired value of R2-1, the following discussion concerns simulation results using a range of successive stage FET size ratios and FETs having differing performance criteria. While the simulation results discussed below are for inverters employing FETS, the present invention is not limited to the use of FETs.
In connection with
The vertical dashed line shows the value R2-1 commonly employed in existing inverter circuits. In the plot of
R2-1=Sqrt (8)≈2.828. In the plot of
Gate widths, in linear units, which may be employed with one or more embodiments of the present invention are provided below. It is noted that gate widths are a function of the LSI process technology generation employed, such as but not limited to 90 nm (nanometers), 65 nm, and 45 nm. Accordingly, the present invention is not limited the specific gate widths listed below. The abbreviation “um” below refers to micrometers.
In
The upper and lower plots of both
Next, in
Three plots are shown in
In
The upper and lower plots of
It remains to determine how the values of R2-1 indicated as desirable from the standpoint of duty-cycle distortion by the plots of
In the case of N=16, the delay time and slew rate for which are illustrated in
From the above simulated results for N=8, it appears that selecting an R2-1 value of about 2 provides better (lower) duty cycle distortion than the Sqrt (8) value commonly employed in existing inverter circuits. Moreover, this value of R2-1 prevents the significant degradation (increase) in delay time and slew rate resulting from still lower values of R2-1.
A parallel observation may be made regarding the results for the case where N=16. The results indicate that for N=16, selecting an R2-1 value of about 3 provides better (lower) duty cycle distortion than using the value of Sqrt (16)=4 commonly employed in existing inverter circuits. Moreover, this value of R2-1 prevents significant degradation (increase) in delay time and slew rate which result from the use of R2-1 values significantly lower than 3.
The simulated results discussed above indicate that values of R2-1 lower than the conventional value of N1/(L-1) for the general case of an inverter circuit with “L” stages and more particularly, lower than Sqrt (L) or L1/2 for three-stage inverters may provide desired performance characteristics for inverter circuits. The above results indicate that R2-1 values of 2 and 3 provide beneficial results for three-stage inverters having N values of 8 and 16, respectively. However, it remains to describe the ranges of R2-1 values contemplated for use in one or more embodiments of the present invention.
The ranges of R2-1 values contemplated for use in one or more embodiments of the present invention may be expressed multiplicatively and/or exponentially. For example, for the case where N=8, the preferred R2-1 value of 2 is about 30% lower than the conventional value of Sqrt (8) of 2.828. When N=16, the preferred R2-1 value of 3 is 25% below the conventional value of Sqrt (16)=4. Thus, the desired ranges of preferred R2-1 value may be expressed multiplicatively, or in other words, as percentages of the value arrived at using the conventional formula described earlier herein.
For the purpose of the following discussion of preferred ranges, the “conventional value” for size ratio between successive stages of an inverter is considered to be N(1/L-1).
Thus, in one or more embodiments, Rm-(m-1) (size ratio between two successive stages in an inverter circuit) may be 5% or more lower than the conventional value. In other embodiments, Rm-(m-1) may be 10% or more lower than the conventional value. In still other embodiments, Rm-(m-1) may be 20% or more lower than the conventional value. In still other embodiments, Rm-(m-1) may be 25% or more lower than the conventional value. In still other embodiments, Rm-(m-1) may be between 25% and 35% lower than the conventional value.
We turn now to preferred ranges of R2-1 as expressed in terms of an exponent value to which N may be raised, for a three-stage inverter circuit. It is noted that the conventional value of such an exponent for a three-stage inverter circuit is 0.5, since the conventional value of R2-1 is N1/2. It is noted that for a preferred R2-1 value of 2 for the case where N=8, the applicable exponent value is 0.333. And for a preferred R2-1 value of 3, for N=16, the exponent value is 0.39.
Thus, in one or more embodiments, the exponent value to which N may be raised may be less than 0.5. In one or more other embodiments the exponent value may be between 0.1 and 0.45. In still other embodiments, the exponent value may be between 0.2 and 0.4. In still other embodiments, the exponent value may be between 0.25 and 0.35. In still other embodiments, the exponent value may be between 0.3 and 0.4.
The principles discussed above are not limited to inverter circuits having values of N of 8 or 16, but may be applied to inverter circuits having any permissible value of N, where “N” may be any positive real number.
Lower duty-cycle distortion attained by the system and method described above may result in improved clock signal quality. This improved clock signal quality may provide the benefit that a given clock frequency may require a lower supply voltage and correspondingly lower power consumption. Alternatively, a higher clock frequency could be employed while using a given power consumption level.
It is noted that the methods and apparatus described thus far and/or described later in this document may be achieved utilizing any of the known technologies, such as standard digital circuitry, analog circuitry, any of the known processors that are operable to execute software and/or firmware programs, programmable digital devices or systems, programmable array logic devices, or any combination of the above. One or more embodiments of the invention may also be embodied in a software program for storage in a suitable storage medium and execution by a processing unit.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.