Claims
- 1. A method of providing a hierarchy of interrupts for a plurality of processor interrupt modes comprising the steps of:
establishing a plurality of processor mode programs at different priority modes of operation including (1) user mode programs at lowest priority, (2) system mode programs, (3) non-maskable interrupt mode programs and (4) debug mode programs at the highest priority; and utilizing a hierarchy of (1) general purpose interrupts (GPI) and system call interrupts (SYSCALL) at user mode, (2) non-maskable interrupts at user and system mode and (3) debug interrupts (DBI) at user, system and non-maskable interrupt mode to automatically cause transitions between the modes of operation.
- 2. The method of claim 1 further comprising the step of utilizing hardware to automatically mask or disable interrupts at the same or a lower level once an interrupt is acknowledged and to record the processor modes in readable and writeable status and control registers.
- 3. The method of claim 2 further comprising the step of reenabling a disabled interrupt at the same or a lower level once the acknowledged interrupt has completed.
- 4. The method of claim 3 further comprising the step of copying to memory registers which were saved by hardware when the interrupt was acknowledged.
- 5. The method of claim 1 wherein a default rule is that GPI, SYSCALL, NMI and DBI may preempt a user mode program.
- 6. The method of claim 5 wherein SYSCALL explicitly preempts a specified user mode program.
- 7. The method of claim 1 wherein a default rule is that NMI and DBI may preempt a GPI program (ISR) running in the system mode.
- 8. The method of claim 1 wherein a default rule is that DBI may preempt an NMI program (ISR).
- 9. The method of claim 1 wherein a default rule is that GPI save status of a program counter, status flags and 2-cycle instruction data registers when acknowledged.
- 10. The method of claim 1 wherein a SYSCALL operates the same as a GPI from the standpoint of saving state and uses the same registers as the GPIs.
- 11. The method of claim 1 wherein the DBI save status and 2-cycle instruction data registers when they preempt user mode programs, but save only status information when they preempt GPI ISRs or NMI ISRs.
- 12. The method of claim 1 wherein the NMI save status but share the same hardware with GPI mode whereby NMI are non-recoverable, but the context in which they occur is saved.
- 13. A method of initiating an interrupt comprising the steps of:
executing a load instruction; and directly setting bits in an interrupt request register (IRR) that is located in a digital signal processor (DSP) interrupt control unit (ICU) in response to the load instruction.
- 14. A method of initiating an interrupt comprising the steps of:
executing a DSU COPY instruction; and
directly setting bits in an interrupt request register (IRR) that is located in a digital signal processor (DSP) interrupt control unit (ICU) in response to the DSU COPY instruction.
- 15. A method of initiating an interrupt comprising the steps of:
executing on a BIT instruction; and directly setting bits in an interrupt request register (IRR) that is located in a digital signal processor (DSP) interrupt control unit (ICU) in response to the BIT instruction.
- 16. A method of generating a SYSCALL interrupt comprising the steps of:
establishing an argument to a SYSCALL instruction which is a vector number; and executing on the SYSCALL instruction to establish the SYSCALL interrupt.
- 17. The method of claim 16 wherein the SYSCALL instruction is a control instruction which combines the features of a call instruction with those of an interrupt and the SYSCALL interrupt is a synchronous interrupt which operates at the same levels as general purpose interrupts (GPIs).
- 18. The method of claim 16 wherein the vector number refers to an entry in a SYSCALL table which is located in a sequence processor (SP) memory.
- 19. A method for invoking any interrupt type by writing to a particular address on a master control bus (MCB) comprising the steps of:
mapping an address to an address interrupt; writing to the address; detecting the write to the address mapped to the address interrupt; and asserting to a digital signal processor (DSP) core interrupt control unit the corresponding interrupt signal.
- 20. A hardware system for providing interrupt forwarding registers comprising:
a sequence processor (SP); at least one processing element (PE); a compute register file (CRF); a plurality of functional units; and a condition generation unit (CGU); wherein when an interrupt occurs and is acknowledged, all instructions in the decode phase are allowed to proceed through execute; one-cycle instructions are allowed to complete and update their target registers and flags; and any two-cycle instructions are allowed to complete, but their output which may include output data, output register addresses and flag information is saved in a set of special purpose interrupt forwarding registers and no update is made to the CRF or status registers.
- 21. The apparatus of claim 20 wherein the hardware comprises multiple PEs and when an interrupt occurs interface signals are provided to all PEs to support operations independently in each PE dependent upon the local PE instruction sequence prior to the interrupt.
- 22. The apparatus of claim 21 wherein there are different mixtures of 1-cycle and 2-cycle instruction in each PE at the time of the interrupt, and by using the signal interface and local information in each PE, the proper operation will occur in each PE on a return from the interrupt.
- 23. The apparatus of claim 22 wherein interface signals include save/restore signals, interrupt signals, and extended or normal pipe status signals.
- 24. The apparatus of claim 20 wherein the address of an instruction in a FETCH phase is saved to an appropriate link register.
- 25. The apparatus of claim 20 wherein an interrupt handler is invoked through a vector table and branch to target address.
- 26. The apparatus of claim 20 wherein when a RETI instruction is executed, it causes a restoration of a saved save condition register (SCR0) and link address from appropriate link and saved-status registers.
- 27. The apparatus of claim 20 wherein when an instruction at a link address reaches the EXECUTE phase, data in interrupt forwarding registers for those units whose last instruction prior to interrupt handling was a two-cycle instruction, is made available to the CRF and the CGU instead of data coming from a corresponding unit.
- 28. A method for providing debug interrupt processing comprising the steps of:
initiating external debugger program communication with a target program core through a master control bus (MCB) or through JTAG to a test module residing on the MCB; and initiating a debug interrupt on the target processor core utilizing the test module residing on a master control bus (MCB).
- 29. The method of claim 28 further comprising the steps of:
storing an interrupt vector table including a debug vector containing an address of a debug instruction register (DBIR); and attempting an instruction fetch from the address of the DBIR causing a processor to enter a STALL state, and causing a status bit to be posted to a debug status register (DBTAT) to indicate a debug stall is in effect thereby allowing the test module to hook the processor.
- 30. The method of claim 29 further comprising the steps of:
detecting the debug stall bit set utilizing the test module; reading a section of instruction memory using MCB read accesses; saving the read section of instruction memory to an external location; and injecting debug monitor code into the read section of instruction memory.
- 31. The method of claim 30 further comprising the step of writing a JMPD instruction to the DBIR.
- 32. The method of claim 31 wherein a direct address contained in the JMPD instruction points to the debug monitor code; and this sequence of steps causes the DBIP bit to be set in the DBSTAT, indicating to the hardware that an instruction is present in the DBIR, causing a fetch unit to retrieve this instruction and execute it.
- 33. The apparatus of claim 20, wherein each PE further comprises a program settable SetCC register, SetCC decode logic, logic that combines flags as specified by the SetCC decode logic, and an interrupt signal interface from each PE to interrupt control logic in the SP for the purposes of specifying interrupts independently from each PE, collectively gathering PE interrupts in the interrupt control unit, and causing PE interrupts.
- 34. A hardware system providing array conditional execution comprising:
a sequence processor (SP); at least one processing element (PE); a plurality of functional units; a condition generation unit (CGU); a program settable SetCC register; SetCC decode logic; logic that combines flags as specified by the SetCC decode logic; and conditional execution control logic that allows arithmetic condition flags (ACFs) to be set when an instruction specifies execute and set ACFs as specified by the SetCC register.
- 35. A hardware system providing conditional branch capability comprising:
a sequence processor (SP); at least one processing element (PE); at least one execution unit supporting packed data operations; and OR logic that combines side effects of individual packed data operations to create signal categories of side effect signals representing the OR of the individual packed data operation side effects.
- 36. A method of providing a hierarchy of interrupts for a plurality of processor interrupt modes of an array processor comprising the steps of:
establishing a plurality of processor mode programs at different priority modes of operation including (1) user mode programs at lowest priority, (2) system mode programs, (3) non-maskable interrupt mode programs and (4) debug mode programs at the highest priority; and utilizing a hierarchy of (1) general purpose interrupts (GPI) and system call interrupts (SYSCALL) at user mode, (2) non-maskable interrupts at user and system mode and (3) debug interrupts (DBI) at user, system and non-maskable interrupt mode to automatically cause transitions between the modes of operation.
- 37. The method of claim 36 further comprising the step of utilizing hardware to automatically mask or disable interrupts at the same or a lower level once an interrupt is acknowledged and to record the processor modes in readable and writeable status and control registers.
- 38. The method of claim 37 further comprising the step of reenabling a disabled interrupt at the same or a lower level once the acknowledged interrupt has completed.
- 39. The method of claim 38 further comprising the step of copying to memory registers which were saved by hardware when the interrupt was acknowledged.
- 40. The method of claim 36 wherein a default rule is that GPI, SYSCALL, NMI and DBI may preempt a user mode program.
- 41. The method of claim 40 wherein SYSCALL explicitly preempts a specified user mode program.
- 42. The method of claim 36 wherein a default rule is that NMI and DBI may preempt a GPI program (ISR) running in the system mode.
- 43. The method of claim 36 wherein a default rule is that DBI may preempt an NMI program (ISR).
- 44. The method of claim 36 wherein a default rule is that GPI save status of a program counter, status flags and 2-cycle instruction data registers when acknowledged.
- 45. The method of claim 36 wherein a SYSCALL operates the same as a GPI from the standpoint of saving state and uses the same registers as the GPIs.
- 46. The method of claim 36 wherein the DBI save status and 2-cycle instruction data registers when they preempt user mode programs, but save only status information when they preempt GPI ISRs or NMI ISRs.
- 47. The method of claim 36 wherein the NMI save status but share the same hardware with GPI mode whereby NMI are non-recoverable, but the context in which they occur is saved.
- 48. A method of initiating an interrupt in an array processor comprising the steps of:
executing a load instruction; and directly setting bits in an interrupt request register (IRR) that is located in a digital signal processor (DSP) interrupt control unit (ICU) in response to the load instruction.
- 49. A method of initiating an interrupt in an array processor comprising the steps of:
executing a DSU COPY instruction; and directly setting bits in an interrupt request register (IRR) that is located in a digital signal processor (DSP) interrupt control unit (ICU) in response to the DSU COPY instruction.
- 50. A method of initiating an interrupt in an array processor comprising the steps of:
executing on a BIT instruction; and directly setting bits in an interrupt request register (IRR) that is located in a digital signal processor (DSP) interrupt control unit (ICU) in response to the BIT instruction.
- 51. A method of generating a SYSCALL interrupt in an array processor comprising the steps of:
establishing an argument to a SYSCALL instruction which is a vector number; and executing on the SYSCALL instruction to establish the SYSCALL interrupt.
- 52. The method of claim 51 wherein the SYSCALL instruction is a control instruction which combines the features of a call instruction with those of an interrupt and the SYSCALL interrupt is a synchronous interrupt which operates at the same levels as general purpose interrupts (GPIs).
- 53. The method of claim 51 wherein the vector number refers to an entry in a SYSCALL table which is located in a sequence processor (SP) memory.
- 54. A method for invoking any interrupt type by writing to a particular address on a master control bus (MCB) of an array processor comprising the steps of:
mapping an address to an address interrupt; writing to the address; detecting the write to the address mapped to the address interrupt; and asserting to a digital signal processor (DSP) core interrupt control unit the corresponding interrupt signal.
Parent Case Info
[0001] The present application claims the benefit of U.S. Provisional Application Ser. No. 60/184,529 entitled “Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response” filed Feb. 24, 2000 which is incorporated by reference herein in its entirety.
Provisional Applications (1)
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Number |
Date |
Country |
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60184529 |
Feb 2000 |
US |