Patent Grant
9749159
A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
1. Technological Field
The present disclosure relates generally to the field of data networking and telecommunications. More particularly, in one exemplary aspect, the present disclosure is directed to scrambling symbols over multi-lane serial interfaces in order to improve undesired electromagnetic emissions.
2. Description of Related Technology
Many serial communications systems send data over more than one lane or channel. Commercial examples include without limitation, DisplayPort, HDMI (High-Definition Multimedia Interface), etc.
As is well known within the electrical arts, rapid signaling changes in a transmission line will generate undesirable electromagnetic interference (EMI) in neighboring circuitry and/or devices. Consequently, in order to reduce EMI, certain technologies (such as for example and without limitation, DisplayPort, Firewire, etc.) utilize a transmitter “scrambler” that is configured to add/spread the signal with pseudorandom noise; the resulting “scrambled” signal has a reduction in peak spectral noise, and a wider spectral “footprint”. The receiver has a corresponding “descrambler” which can remove the pseudorandom noise and reconstruct the original signal. Many types of pseudorandom number generators exist; however, scramblers are typically implemented with linear feedback shift registers (LFSRs) due to the simplicity and relatively inexpensive cost.
One problem with multi-channel scrambling technologies (such as DisplayPort, etc.) occurs when the same data is transmitted on each channel. For example, during video data transmissions so-called “blanking” intervals can include long periods of null data which are typically represented with the same value (e.g., all zeros (0) or all ones (1)). Under these circumstances, the scrambled result for each lane of the multi-lane transceiver is identical (each lane transmits the same value, which is identically scrambled). Since each lane is perfectly correlated with the other lanes, the overall EMI magnitude of the multi-lane transmission is a direct sum of each of the contributing EMIs. The resulting spectral footprint of the multi-lane transmission line may be strong enough to interrupt nearby circuitry. Large EMI can be especially problematic for devices that have very aggressive form factors (i.e., where components are in very close proximity).
Accordingly, improved apparatus and methods are needed in order to address these EMI concerns with regards to multi-lane serial bus technologies such as e.g., DisplayPort, etc. More generally, such apparatus and methods would ideally provide for mechanisms that improve the EMI characteristics of multi-lane high speed serial bus operation, while also advantageously leveraging existing hardware in certain implementations so as to minimize circuitry costs in future implementations.
The aforementioned needs are satisfied by providing, inter alia, improved apparatus and methods for scrambling symbols over multi-lane serial interfaces in order to improve undesired electromagnetic emissions.
A method for scrambling a plurality of symbols is disclosed. In one embodiment, the method includes: scrambling a plurality of symbols according to at least a corresponding plurality of scrambling values; transmitting the plurality of scrambled symbols via a corresponding plurality of lanes to a receiver; and where the receiver is configured to responsive to receiving the plurality of scrambled symbols, descramble the plurality of scrambled symbols.
In another embodiment, the method includes: responsive to receiving a plurality of scrambled symbols, descramble the plurality of scrambled symbols according to a corresponding plurality of scrambling values; where the plurality of scrambling values are associated within each lane of a multi-lane receiver.
A multi-lane transmitter is also disclosed. In one embodiment, the multi-lane transmitter is configured to scramble each lane according to a distinct scrambling value.
A multi-lane receiver is further disclosed. In one embodiment, the multi-lane receiver is configured to descramble each lane according to a distinct scrambling value.
A multi-lane communication system is additionally disclosed. In one embodiment, the multi-lane communication system is configured to scramble/descramble symbols over multi-lane serial interfaces in order to improve undesired electromagnetic emissions.
Other features and advantages will immediately be recognized by persons of ordinary skill in the art with reference to the attached drawings and detailed description of exemplary embodiments as given below.
All Figures© Copyright 2013 Apple Inc. All rights reserved.
Reference is now made to the drawings, wherein like numerals refer to like parts throughout.
Exemplary embodiments are now described in detail. While these embodiments are primarily discussed in the context of an HDMI and DisplayPort audio/visual (A/V) networks, it will be recognized by those of ordinary skill that the present disclosure is not in any way limited to such applications. In fact, the various aspects set forth herein are useful in any network that can benefit from the reduction of electromagnetic interference in multi-lane serial bus transactions.
Furthermore, while these embodiments are disclosed in a serial transmission of digital data represented as electrical levels, ones having ordinary skill in the related arts will recognize that the various techniques may also extend to other systems and applications including, inter alia, multi-level wired systems (e.g., three-level encoded Ethernet), and modulated transmission schemes (e.g., a high frequency carrier that is modulated in the amplitude or frequency domain {AM or FM} by the signals being transmitted).
Existing HDMI Operation—
Referring now to
The exemplary HDMI interface comprises four (4) unidirectional differential signaling pairs that consist of: three (3) data channels (data channel 0, data channel 1, data channel 2), and a clock (characterized by a 1/10 bit-rate frequency). In other configurations (such as e.g., future implementations of HDMI, and Mobile High Definition Link (MHL)), the clock differential pair may be replaced with another data channel.
Prior art HDMI TMDS observes a fixed set of rules that enables only a subset of possible symbols, based on the type of data. Moreover, for simplicity, only 10-bit patterns are used to represent the information to be transmitted (i.e., the symbols do not change in length). Specifically, the 10-bit encodings used for control and preamble transmissions share common symbols which are disjoint from (i.e., do not overlap) the 10-bit symbols used for the other types of data (guard band, data island and video data). Similarly, the 10-bit symbol encodings used for data island transmissions (also referred to as TERC4 (TMDS Error Reduction Coding 4-bit) encoding) are distinct. The 10-bit symbols used for the guard band are a subset of the symbol encodings used for video data.
Existing HDMI implementations do not implement any form of scrambling over the individual channels. Incipient research is directed to incorporating scrambling functionality to improve future implementations of HDMI.
Existing DisplayPort Operation—
From an application software standpoint, DisplayPort is very similar to HDMI, in fact in some applications DisplayPort can be used to encapsulate HDMI data. However, the physical interface of DisplayPort is markedly different.
Referring now to
While TMDS could be considered a form of 8B/10B encoding, it is appreciated that as used within the relevant arts, the term “8B/10B” refers to a specific protocol developed by IBM (the IBM 8B/10B scheme was subject to patents which have since expired). DisplayPort utilizes the IBM 8B/10B encoding (as described within “A DC Balanced, Partitioned-Block, 8B/10B Transmission Code” to Widmer and Franaszek, incorporated herein by reference in its entirety). 8B/10B encoding maps an 8-bit data byte or one of a set of twelve control symbols to a 10-bit symbol in order to achieve the DC balance. The mapping is such that the mapped versions of the control symbols and data symbols are distinct. The 8-bit symbol can either be an 8-bit data byte or a control symbol. In both cases, they are mapped into 10-bit symbols. One particularly useful property of 8B/10B encoded symbols is that in any sequence of 10-bit symbols, there will never be more than a disparity of +1 or −1 when counting the number of ones and zeros (at symbol boundaries). For example, if after a number of 10-bit symbols the running disparity is −1, then the next symbol will either have exactly five (5) ones and five (5) zeros (i.e., the running disparity remains −1), or it will have six (6) ones and four (4) zeros (i.e., the running disparity changes to +1). Since the running disparity is only used at symbol boundaries, the bit-wise running disparity can range between +3 and −3.
As the scheme name suggests, eight (8) bits of data are encoded and transmitted as a 10-bit symbol. The low five (5) bits of data are encoded into a 6-bit group (i.e. the so-called 5b/6b portion) and the top three (3) bits are encoded into a 4-bit group (i.e. the so-called 3b/4b portion). These two sub-encoding groups are subsequently concatenated together to form the 10-bit symbol that is transmitted over the transmission medium. The data symbols are often referred to in the format “D.x.y” where x ranges in value from 0-31 (25=32) and y ranges in value from 0-7 (23=8), i.e. the five (5) and three (3) bit portions.
One useful property of such an encoding scheme is that since 10-bit symbols are utilized to encode 8-bit words, some of the possible one-thousand twenty-four (210=1024) codes can be excluded in order to comply with the previously mentioned run-length limit of five (5) consecutive equal bits and a differential limit such that the difference of the count of 0s and 1s is no more than two (2) for a given twenty bit string of bits. In addition, some of the two-hundred fifty-six (256) possible 8-bit words can be encoded in two alternative ways. Using these alternative encodings, the scheme is able to affect long-term DC-balance on the transmission line.
This DC-balance is accomplished in part via a mechanism known as “running disparity” that keeps the number of 1s and 0s that are transmitted roughly equal. That is, for each 5b/6b and 3b/4b code with an unequal number of 1s and 0s, there are two (2) bit patterns that can be used to transmit it. For example, a first ten-bit with two more 1s then 0s can be represented as follows: 001011 1110. This first ten-bit pattern can also be represented by its inverse, thereby encoding two or more 0s than 1s as follows: 110100 0001. Accordingly, depending on the current running disparity of the signal, the encoding hardware selects which of the two possible 10-bit sequences to send for the given data.
In addition, 8B/10B encoding possesses what are known as a “special symbols”. They are typically referred to in the form “K.x.y” and have different encodings from any of the possible “D.x.y” symbols; i.e., they are symbols which cannot result via the encoding of an 8-bit data symbol. Table 1 below illustrates the format for these special symbols, which include a first 10-bit code for a running disparity of negative one (−1), along with its inverse for a running disparity of positive one (+1):
These special symbols are inserted into the data stream and accordingly, can be used for executing low-level control functions separate and apart from encoded data symbols. For example, the DisplayPort specification sets forth a number of control functions that can be mapped onto these so-called “K-codes” of the IBM 8B/10B encoder specification. These control functions include: (1) Blanking Start (BS); (2) Blanking End (BE); (3) Fill Start (FS); (4) Fill End (FE); (5) Secondary-data Start (SS); (6) Secondary-data End (SE); (7) Scrambler Reset (SR); (8) Content Protection BS (CPBS); and (9) Content Protection SR (CPSR).
Referring back to
G(X)=X16+X5+X4+X3+1 (Equation 1)
The resulting data can be represented by Equation (2).
D′[7:0]=D[7:0]XOR LFSR[8:15] (Equation 1)
Additionally, DisplayPort specifies certain rules for scrambler operation. The scrambling/descrambling LFSR advances on all symbols (both D and K), however some usages of the K symbols are not scrambled (DisplayPort versions 1.2 introduced “multistream” operation which scrambles certain K symbols). Data symbols (including null or “fill” data) is scrambled). Furthermore, certain special symbols can be used to reset the scrambling/descrambling LFSR. DisplayPort implements inter-lane skew on the data (each successive lane is offset from its predecessor by two (2) symbols), thus the data is scrambled first and the lane-to-lane skew is applied.
Apparatus—
Various embodiments of the present disclosure are directed to distinctly scrambling each lane of a multi-lane transceiver. Ideally (but not mandatorily), each lane is scrambled so as to produce uncorrelated outputs (as compared to the other scrambled lanes). Unlike correlated scrambling which results in EMI that constructively interferes (i.e., a direct sum), uncorrelated scrambling will result in EMI that adds according to a root mean square (which significantly improves overall EMI emissions). For example, with two (2) lanes, the overall EMI will be approximately 1.414 times (square root of two (2)) a single lane EMI.
LFSRs are advantageously used in exemplary implementations of the disclosure because the operation of the LFSR is deterministic, while also providing a sequence of bits that appears random. Accordingly, and as discussed previously herein, synchronization between transmitter and receiver can be maintained if the cycles between the LFSR at the transmitter and the LFSR at the receiver remains synchronized. In an exemplary embodiment, each LFSR is a 16-bit LFSR, although it is appreciated that other LFSR's (including those of other lengths, and/or tap configurations) could readily be substituted such as those described previously herein. When using an exemplary 16-bit LFSR, a subset of bits is used for symbol encoding.
Several distinct constructions are provided to illustrate the foregoing; however, those of ordinary skill in the related arts will readily appreciate that virtually any such scheme that results in uncorrelated scrambling for each lane of a multi-lane transceiver will result in reduced EMI emissions.
Referring now to
The receiver 400 and transmitter 450 include complementary LFSRs 402 which are used for each lane but each lane is further modified uniquely by a seed value. For example, in a first variant, the data is XOR'd (exclusively OR'd) with an LFSR and then is further XOR'd with the lane (or channel number) that it is associated with for transport. In a similar variant, a pre-agreed scrambler reset seed is associated with the lane, so that when scrambler reset occurs, the LFSRs on different lanes are set to different values. It should be further noted that these two (2) variants are not exclusive, in fact a different scrambler reset can be used for each lane as well as an XOR with the lane number. While both of the foregoing examples use seed values that are based on the lane, it is readily appreciated that virtually any seed value may be used.
Other examples of seed values may include e.g., randomly generated seed values, incrementing seed values, configurable seed values, etc. In systems where the seed is dynamically set (not an agreed upon value), the receiver and transmitter may be required to negotiate or coordinate operation based on e.g., out of band signaling, an initial exchange (e.g., via non-scrambled transactions, etc.).
Referring now to
In this example, the transmitter 460 and receiver 410 have matching LFSR bits XOR'd with the appropriate lanes. For example, as shown the first lane may use LFSR [8:15], the second lane may use LFSR[7:0], the third lane may use LFSR[0:3 . . . 8:11], and the fourth lane may use LFSR[15:12 . . . 7:4], etc. In other examples, a 32-bit LFSR can be used such that: the first lane uses [0:7], the second lane uses [8:15], the third lane uses 16:23], and the fourth lane uses [23:31]. Those of ordinary skill will recognize that the foregoing selection of bits is merely illustrative of the myriad of combinations that are possible.
Referring now to
As shown each lane is associated with a distinct LFSR. Those of ordinary skill in the related arts will recognize that significant research has been devoted to discovering LFSRs with desirable properties e.g., maximal length, self-synchronization, maximal run length, etc. Accordingly variants may select LFSRs based on any of such desirable properties. For example certain applications may be more interested in self-synchronizing LFSRs than LFSRs which have guarantee shorter maximal run lengths or vice versa.
Moreover, it is further appreciated that in some circumstances, it may be desirable to combine one or more of the foregoing schemes of
Still further, it is appreciated that since both the transmitter and receiver must agree on the multi-lane scrambling scheme, various systems may be configured to negotiate the multi-lane scrambling configuration and/or default to a specific configuration. In some variants, the default configuration is compatible with legacy systems.
Referring now to
While a specific device configuration and layout is shown and discussed, it is recognized that many other configurations may be readily implemented by one of ordinary skill given the present disclosure, the apparatus 500 of
The illustrated apparatus 500 of
The upstream plurality of ports and associated receiving elements 502 may comprise one or more upstream auxiliary channels, one or more upstream media ports, and receiver apparatus (e.g., multiplexing switches, reception logic, clock recovery circuitry, etc.). In one exemplary embodiment, the auxiliary channel is bi-directional and carries management and device control data, and the upstream media ports minimally comprise receivers for unidirectional data lanes, and use of an embedded clock. The receiver apparatus monitors and selectively enables and disables the auxiliary and media ports. In certain embodiments, the receiver apparatus may be adapted to utilize a packet-based unidirectional network protocol, such as the DisplayPort or HDMI protocol previously described herein.
Similarly, the downstream plurality of ports and associated receiving elements 504 comprise one or more downstream auxiliary channels, one or more downstream media ports, and transmitter apparatus (e.g. demultiplexing switches, transmission logic, clock embedding circuitry, etc.). In one exemplary embodiment, the auxiliary channel is bi-directional and carries management and device control data, and the downstream media ports minimally comprise transmitters for unidirectional data lanes, and inclusion of an embedded clock. The transmitter apparatus monitors and selectively enables and disables the auxiliary and media ports. As with the receiver, the transmitter apparatus may be adapted to utilize a packet-based unidirectional network protocol.
In an exemplary implementation, the downstream-facing ports may include a serializer adapted to receive an input word and output a bit stream. For example, in one configuration, the serializer may receive a 10-bit input word and output ten (10) serial bits. In addition, the serializer may also provide an optional corresponding clock.
Conversely, in another configuration, the upstream-facing ports may also include a de-serializer adapted to receive a serial bit stream and output a word. Furthermore, such de-serializing apparatus may additionally require clock recovery circuitry and boundary detection, as is well understood in the digital computing arts. For example, in one embodiment, the de-serializer may receive 10 (ten) serial bits, and convert it into one 10-bit word. When the de-serializer detects a misalignment of timing by one or more bits, the de-serializer accordingly skips or pads its rate accordingly. Furthermore, during initialization, the de-serializer may recognize an initiation sequence.
Also included are one or more storage devices (e.g., a memory subsystem) 510 used to store for example data for transmission or that has been received.
It will be appreciated that not all elements are required in a single device for operation within a “network”. For instance, a device only capable of “source” operation would not require upstream ports, or certain audio or video elements. Conversely, a “sink” device may not require downstream ports. Moreover, the “receiver” 502 and “transmitter” 504 elements may comprise transceivers capable of both transmission and reception if desired.
Note that as used herein, such network may be comprised of (without limitation) as few as two devices in communication with one another via an interface, or even two components in communication with one another within the same host apparatus.
The processing subsystem 506 may comprise one or more of central processing units (CPU) or digital processors, such as a microprocessor, digital signal processor, field-programmable gate array, RISC core, or plurality of processing components mounted on one or more substrates.
The processing subsystem is coupled to memory subsystem 510, which may include for example SRAM, FLASH and SDRAM components. As used herein, the term “memory” includes any type of integrated circuit or other storage device adapted for storing digital data including, without limitation, ROM. PROM, EEPROM, DRAM, SDRAM, DDR/2 SDRAM, EDO/FPMS, RLDRAM, SRAM, “flash” memory (e.g., NAND/NOR), and PSRAM.
The processing subsystem may also comprise additional co-processors, such as a dedicated graphics accelerator, network processor (NP), or audio/video processor. As shown processing subsystem 806 includes discrete components, however it is understood that in some embodiments they may be consolidated or fashioned in a SoC (system-on-chip) configuration.
The processing subsystem 506 is adapted to receive one or more media streams from an upstream apparatus 502 for processing for media displays such as a video display 512, or audio speakers 514. Processing subsystem 506 may preferentially comprise graphics processors, applications processors, and or audio processors. In “thin clients”, the processing subsystem 506 may be significantly reduced in complexity and limited to simple logic, or in extreme cases altogether non-existent.
It will be readily appreciated by those of ordinary skill that different combinations and/or variations of the foregoing can be made depending on the desired application and performance attributes.
Methods—
Referring now to
At step 602 of the method 600, a plurality of symbols are scrambled according to at least a corresponding plurality of scrambling values.
In one variant, the scrambling is based on a seed value. The seed value may be fixed or variable. For example, the seed value may be the lane number associated with the symbol. In other embodiments, the seed value may be set according to a pre-determined scheme (e.g., based on time, application, incrementing count, etc.). In certain scenarios, the seed value may be communicated, negotiated, or otherwise actively agreed upon between the transmitter and the receiver.
In another variant, the scrambling values are selected from various taps of a scrambling component. For example, the scrambling values may be any arrangement of bits, nibbles, bytes, word, etc. of an LFSR output. Moreover, the taps may be selected contiguously, non-contiguously, little endian, big endian, etc.
In still another variant, the scrambling values are selected from different scrambling components. For example, the receiver and transmitter may have an array of LFSRs which are assigned to individual lanes, etc.
In some embodiments, the scrambling component is a linear feedback shift register (LFSR). In other embodiments, the scrambling component is a memory with an appropriately randomized sequence of values. In still other embodiments, the scrambling component is an algorithm implemented within software.
Various LFSRs may be used according to design requirements. In some variants, the LFSR is a maximal length LFSR. Alternately, the LFSR may be a self-synchronizing LFSR. In still other scenarios, the LFSR may guarantee a maximum run length.
At step 604 of the method 600, the plurality of scrambled symbols are transmitted via a corresponding plurality of lanes to a receiver.
At step 606 of the method 600, the plurality of received scrambled symbols are descrambled. Descrambling is performed in the exemplary embodiment with an appropriately complementary descrambler.
It will be recognized that while certain aspects of the disclosure are described in terms of a specific sequence of steps of a method, these descriptions are only illustrative of the broader methods, and may be modified as required by the particular application. Certain steps may be rendered unnecessary or optional under certain circumstances. Additionally, certain steps or functionality may be added to the disclosed embodiments, or the order of performance of two or more steps permuted. All such variations are considered to be encompassed within the disclosure and claims herein.
While the above detailed description has shown, described, and pointed out novel features of the disclosure as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the art. The foregoing description is of the best mode presently contemplated. This description is in no way meant to be limiting, but rather should be taken as illustrative of the general principles, and the scope of the various aspects of the disclosure should be determined with reference to the claims.
This application is a continuation of and claims priority to co-owned and co-pending U.S. patent application Ser. No. 13/841,897 of the same title, filed Mar. 15, 2013, which is incorporated herein by reference in its entirety. This application is also related to co-owned, co-pending U.S. patent application Ser. No. 13/747,264 filed on Jan. 22, 2013 and entitled “METHODS AND APPARATUS FOR THE INTELLIGENT SCRAMBLING OF CONTROL SYMBOLS”; Ser. No. 13/747,383 filed Jan. 22, 2013 and entitled “METHODS AND APPARATUS FOR ERROR RATE ESTIMATION”; and Ser. No. 12/976,274 filed Dec. 22, 2010 and entitled “Methods and Apparatus for the Intelligent Association of Control Symbols”, each of the foregoing being incorporated herein by reference in its entirety.
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| Child | 14961501 | US |
