METHODS AND APPARATUS FOR STORING AND DELIVERING COMPRESSED DATA

Abstract

Methods and apparatus for storing and delivering compressed data are disclosed. In one embodiment, a direct memory access (DMA) unit with a lossless coder/decoder (CODEC) receives uncompressed data. The direct memory access unit then compresses the uncompressed data to produce lossless compressed data, and stores the lossless compressed data in a memory, wherein the compressing operation and the storing operation are each part of a direct memory access (DMA) write operation. In another embodiment, the direct memory access (DMA) unit receives lossless compressed data. The direct memory access unit then decompresses the compressed data to produce lossless decompressed data, and delivers the decompressed data to an output device, wherein the decompressing operation and the receiving operation are each part of a direct memory access (DMA) read operation.

Description

BACKGROUND

In order to store and transmit large amounts of data, the data is often compressed. As a result, many electronic devices must compress and decompress large amounts of data. For example, a digital video may be more efficiently stored and transmitted in a compressed form. However, in order to display the digital video on a high definition television or monitor, the video data may need to be decompressed.

Compression and decompression are computationally intensive tasks. Accordingly, many electronic devices have a dedicated hardware coder/decoder (CODEC). In addition, moving large amounts of memory from one location to another location often requires a significant amount of time. Accordingly, many electronic devices have a dedicated direct memory access (DMA) unit.

However, even with a dedicated hardware coder/decoder (CODEC) and a dedicated direct memory access (DMA) unit, a large amount of central processing unit cycles are consumed managing the interaction between these two devise when a large amount of data needs to be moved and compressed or decompressed (e.g., digital video and/or digital audio).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an example network communication system.

FIG. 2 is a block diagram of an example electronic device incorporating a direct memory access unit with a lossless coder/decoder (DMA/CODEC).

FIG. 3 is a block diagram of an example processing unit employing a direct memory access unit with a lossless coder/decoder (DMA/CODEC).

FIG. 4 is a block diagram of an example direct memory access unit with a lossless coder/decoder (DMA/CODEC).

FIG. 5 is a flowchart of an example process for storing data using a direct memory access unit with a lossless coder/decoder (DMA/CODEC).

FIG. 6 is a flowchart of an example process for delivering data using a direct memory access unit with a lossless coder/decoder (DMA/CODEC).

FIG. 7 is a flowchart of another example process for storing data using a direct memory access unit with a lossless coder/decoder (DMA/CODEC).

FIG. 8 is a flowchart of another example process for delivering data using a direct memory access unit with a lossless coder/decoder (DMA/CODEC).

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Briefly, methods and apparatus for storing and delivering compressed data are disclosed. In an embodiment, the apparatus includes a direct memory access (DMA) engine operatively coupled to a lossless compression engine. The direct memory access (DMA) engine is structured to perform a direct memory write operation of lossless compressed data, and the lossless compression engine is structured to produce the lossless compressed data as part of the direct memory write operation.

Among other features, electronic devices employing the disclosed direct memory access (DMA) engine with integrated coder/decoder (CODEC) are able to perform large memory transfers where compression and/or decompression are used (e.g., retrieving compressed video from memory and sending the uncompressed version of the video to a graphics processing unit) with minimal intervention from the central processing unit. As a result, the central processing unit is free to perform other tasks.

In one example, the direct memory access (DMA) engine is structured to (a) cause the lossless compressed data to be produced in response to an initiation by a central processing unit (CPU) and (b) perform the direct memory storage operation without further interaction by the central processing unit (CPU). In one example, the lossless compression engine is structured to segment uncompressed data and reassemble corresponding lossless compressed data. In one example, the lossless compression engine is structured to send the lossless compressed data via a communication channel.

Turning now to the figures, in general, a direct memory access (DMA) unit includes a lossless compression engine and/or a lossless decompression engine (CODEC). In one mode of operation, the direct memory access (DMA) unit compresses uncompressed data and stores the compressed data in a memory as part of a direct memory access (DMA) write operation. For example, the direct memory access (DMA) unit may compress and store video information as the video information is received from a video camera (i.e., “on the fly”). In another mode of operation, the direct memory access (DMA) unit decompresses compressed data and delivers the decompressed data to an output device as part of a direct memory access (DMA) read operation. For example, the direct memory access (DMA) unit may decompress and deliver video information to a display via a graphics processing unit (GPU). In both modes of operation, the operation may be initiated by a central processing unit (CPU). However, the operation is typically performed without further interaction by the central processing unit (CPU).

The direct memory access (DMA) unit with integrated coder/decoder (CODEC) may be part of a wide variety of devices. For example, the DMA/CODEC may be part of networked video game console. A block diagram of certain elements of an example network communications system 100 is illustrated in FIG. 1. The illustrated system 100 includes one or more client devices 102 (e.g., computer, television, camera, phone), one or more web servers 106, and one or more databases 108. Each of these devices may communicate with each other via a connection to one or more communications channels 110 such as the Internet or some other wired and/or wireless data network, including, but not limited to, any suitable wide area network or local area network. It will be appreciated that any of the devices described herein may be directly connected to each other instead of over a network.

The web server 106 stores a plurality of files, programs, and/or web pages in one or more databases 108 for use by the client devices 102 as described in detail below. The database 108 may be connected directly to the web server 106 and/or via one or more network connections. The database 108 stores data as described in detail below.

One web server 106 may interact with a large number of client devices 102. Accordingly, each server 106 is typically a high end computer with a large storage capacity, one or more fast microprocessors, and one or more high speed network connections. Conversely, relative to a typical server 106, each client device 102 typically includes less storage capacity, a single microprocessor, and a single network connection.

Each of the devices illustrated in FIG. 1 (e.g., client 102 and/or server 106) may include certain common aspects of many electronic devices such as microprocessors, memories, direct memory access units, peripherals, etc. FIG. 2 is a block diagram of an example electronic device incorporating a direct memory access unit with a lossless coder/decoder (DMA/CODEC). For example, the electrical device 200 may be a client, a server, a camera, a phone, and/or a television.

The example electrical device 200 includes a main unit 202 which may include, if desired, one or more processing units 204 electrically coupled by an address/data bus 206 to one or more memories 208, other computer circuitry 210, and one or more interface circuits 212. The processing unit 204 may include any suitable processor or plurality of processors. In addition, the processing unit 204 may include other components that support the one or more processors. For example, the processing unit 204 may include a central processing unit (CPU), a graphics processing unit (GPU), and/or a direct memory access (DMA) unit.

The memory 208 may include various types of non-transitory memory including volatile memory and/or non-volatile memory such as, but not limited to, distributed memory, read-only memory (ROM), random access memory (RAM) etc. The memory 208 typically stores a software program that interacts with the other devices in the system as described herein. This program may be executed by the processing unit 204 in any suitable manner. The memory 208 may also store digital data indicative of documents, files, programs, web pages, etc. retrieved from a server and/or loaded via an input device 214.

The interface circuit 212 may be implemented using any suitable interface standard, such as an Ethernet interface and/or a Universal Serial Bus (USB) interface. One or more input devices 214 may be connected to the interface circuit 212 for entering data and commands into the main unit 202. For example, the input device 214 may be a keyboard, mouse, touch screen, track pad, isopoint, camera, voice recognition system, accelerometer, global positioning system (GPS), and/or any other suitable input device.

One or more displays, printers, speakers, monitors, televisions, high definition televisions, and/or other suitable high bandwidth output devices 216 may also be connected to the main unit 202 via the interface circuit 212. High bandwidth output devices 216 typical consume uncompressed data, such as uncompressed audio and/or video data. For example, a display for displaying decompressed video data may be a cathode ray tube (CRTs), liquid crystal displays (LCDs), electronic ink (e-ink), and/or any other suitable type of display.

One or more storage devices 218 may also be connected to the main unit 202 via the interface circuit 212. For example, a hard drive, CD drive, DVD drive, and/or other storage devices may be connected to the main unit 202. The storage devices 218 may store any type of data used by the device 200.

The electrical device 200 may also exchange data with one or more low bandwidth input/output (I/O) devices 220. Low bandwidth I/O devices 220 typical produce and/or consume compressed data, such as compressed audio and/or video data. For example, low bandwidth I/O devices 220 may include network routers, camera, audio players, thumb drives etc.

The electrical device 200 may also exchange data with other network devices 222 via a connection to a network 110. The network connection may be any type of network connection, such as an Ethernet connection, digital subscriber line (DSL), telephone line, coaxial cable, wireless base station 230, etc. Users 114 of the system 100 may be required to register with a server 106. In such an instance, each user 114 may choose a user identifier (e.g., e-mail address) and a password which may be required for the activation of services. The user identifier and password may be passed across the network 110 using encryption built into the user's browser. Alternatively, the user identifier and/or password may be assigned by the server 106.

In some embodiments, the device 200 may be a wireless device 200. In such an instance, the device 200 may include one or more antennas 224 connected to one or more radio frequency (RF) transceivers 226. The transceiver 226 may include one or more receivers and one or more transmitters operating on the same and/or different frequencies. For example, the device 200 may include a blue tooth transceiver 216, a Wi-Fi transceiver 216, and diversity cellular transceivers 216. The transceiver 226 allows the device 200 to exchange signals, such as voice, video and data, with other wireless devices 228, such as a phone, camera, monitor, television, and/or high definition television. For example, the device 200 may send and receive wireless telephone signals, text messages, audio signals and/or video signals directly and/or via a base station 230. A receive signal strength indicator (RSSI) associated with each receiver generates an indication of the relative strength or weakness of each signal being received by the device 200.

FIG. 3 is a block diagram of an example processing unit 204 employing a direct memory access unit with a lossless coder/decoder (DMA/CODEC) 304. In this example, the DMA/CODEC 304 is operatively coupled to a central processing unit (CPU) 302 and a graphics processing unit (GPU) 306. The central processing unit 302 initiates a data transfer via the DMA/CODEC 304 by sending data transfer instructions. The data transfer instructions may be indicative of a read operation and/or a write operation. Once the central processing unit 302 initiates the data transfer by sending the instructions to the DMA/CODEC 304, the DMA/CODEC 304 carries out the memory transfer operation without further intervention needed from the central processing unit 302. Once the DMA/CODEC 304 completes the data transfer operation, the DMA/CODEC 304 notifies the central processing unit 302 that the data transfer is complete by asserting an interrupt line.

For example the central processing unit 302 may send data transfer instructions to the DMA/CODEC 304 indicating that the DMA/CODEC 304 should retrieve a certain section of memory 208, decompress the data from the memory 208 and send the decompressed data to the graphics processing unit 306. In this example, the graphics processing unit 306 may then transmit the decompressed data to a high bandwidth output device 216, such as a display or television.

In another example, the central processing unit 302 may send data transfer instructions to the DMA/CODEC indicating that the DMA/CODEC should receive uncompressed data, compress that data and send the compressed data to some destination without further intervention by the central processing unit 302. For example, a high bandwidth input device 214 such as a video camera and/or microphone interfaced via interface circuit 212 may send uncompressed video data to the DMA/CODEC 304. The DMA/CODEC 304 may then compresses the uncompressed data and store the compressed data in memory 208 and/or send the compressed data to one or more low bandwidth I/O devices 220 via interface circuit to 212. For example, the DMA/CODEC 304 may send the compressed data to a network router and/or an audio player.

FIG. 4 is a block diagram of an example direct memory access unit with a lossless coder/decoder (DMA/CODEC). In this example the DMA/CODEC 304 includes a DMA engine 402, a lossless compression engine 404, and a lossless decompression engine 406. In an example, a CPU 302 and/or a GPU 306 sends data transfer instructions to the DMA engine 402. A high bandwidth input device may then send uncompressed data to the DMA engine 402 without further intervention from the CPU 302 or GPU 306. For example, a high definition video recorder may send a long stream of uncompressed video data to the DMA engine 402. The DMA engine 402 then sends the uncompressed data in segments to the lossless compression engine 404, and the lossless compression engine 404 returns the data to the DMA engine 402 in compressed form. The DMA engine 402 then stores the compressed data to a data storage device such as memory 208.

In another example, CPU 302 and/or a GPU 306 may send data transfer instructions to the DMA engine 402 to retrieve compressed data from memory 208 and transfer the data in uncompressed form to a high bandwidth output device. For example, the DMA engine 402 may retrieve compressed video data from memory 208, and send the compressed video data to lossless decompression engine 406, which returns the data in decompressed segments to the DMA engine 402. The DMA engine 402 may then send the decompressed data to the high-bandwidth output device. For example, the DMA engine 402 may send uncompressed video data to a high-definition display 216. As discussed in more detail below with reference to FIG. 5 and FIG. 6, each of these data storage and retrieval operations perform the lossless compression or decompression on the fly. Accordingly, segments of data are processed in parallel.

FIG. 5 is a flowchart of an example process 500 for storing data using a direct memory access unit with a lossless coder/decoder (DMA/CODEC). Although the process 500 is described with reference to the flowchart illustrated in FIG. 5, it will be appreciated that many other methods of performing the acts associated with process 500 may be used. For example, the order of many of the operations may be changed, and some of the operations described may be optional.

In general, a DMA engine 402 receives uncompressed data, segments the uncompressed data, and forwards each uncompressed data segment to the lossless compression engine 404. After the lossless compression engine 404 returns the compressed data to the DMA engine 402, the DMA engine 402 reassembles the compressed data segments into the overall compressed data stream and then stores and/or sends the compressed data to a memory device and/or a low bandwidth I/O device 220.

More specifically, in this example, the process 500 begins when the DMA engine 402 receives or retrieves uncompressed data (block 502). For example, the DMA engine 402 may receive or retrieve uncompressed audio and/or video data from one or more input devices such as a microphone or camera. The DMA engine 402 then segments the uncompressed data as the uncompressed data is being received or retrieved (block 504). The DMA engine 402 then forwards each uncompressed data segment to the lossless compression engine 404 (block 506). The lossless compression engine 404 then compresses that data segment (block 508).

After the lossless compression engine 404 returns the compressed data to the DMA engine 402, the DMA engine 402 reassembles the compressed data segments into the overall compressed data stream (block 510). For example, the DMA engine 402 may be reassembling a compressed video stream. The DMA engine 402 then stores and/or sends the compressed data to a memory device and/or a low bandwidth I/O device 220 (block 512). For example, the DMA engine 402 may store the compressed data in memory 208, and/or the DMA engine 402 may send the compressed data to a network router, camera, audio player, thumb drive, and/or any other suitable device.

Each of these steps in process 500 may be executed in parallel with one or more of the other steps in 500. For example, after uncompressed data is received, the uncompressed data may be segmented and compressed at the same time that new data is being received. Similarly, as compressed data is produced, the compressed data may be reassembled and stored on the fly at the same time as new data is being received, segmented and compressed.

FIG. 6 is a flowchart of an example process 600 for delivering data using a direct memory access unit with a lossless coder/decoder (DMA/CODEC). Although the process 600 is described with reference to the flowchart illustrated in FIG. 6, it will be appreciated that many other methods of performing the acts associated with process 600 may be used. For example, the order of many of the operations may be changed, and some of the operations described may be optional.

In general, a DMA engine 402 receives compressed data, segments the compressed data, and forwards each compressed data segment to the lossless decompression engine 406. After the lossless decompression engine 406 returns the decompressed data to the DMA engine 402, the DMA engine 402 reassembles the decompressed data segments into the overall decompressed data stream and then stores and/or sends the decompressed data to a memory device and/or a high bandwidth output device 216.

More specifically, in this example, the process 600 begins when the DMA engine 402 receives or retrieves compressed data (block 602). For example, the DMA engine 402 may receive or retrieve compressed audio and/or video data from one or more memories 208 and/or one or more low bandwidth I/O devices 220 such as a network router, camera, audio player, etc. The DMA engine 402 then segments the compressed data as the compressed data is being received or retrieved (block 604). The DMA engine 402 then forwards each compressed data segment to the lossless decompression engine 406 (block 606). The lossless decompression engine 406 then decompresses that data segment (block 608).

After the lossless decompression engine 406 returns the decompressed data to the DMA engine 402, the DMA engine 402 reassembles the decompressed data segments into the overall decompressed data stream (block 610). For example, the DMA engine 402 may be reassembling a decompressed video stream. The DMA engine 402 then stores and/or sends the decompressed data to a memory device and/or a high bandwidth output device 216 (block 612). For example, the DMA engine 402 may store the decompressed data in memory 208, and/or the DMA engine 402 may send the decompressed data to a display and/or amplifier/speaker.

Each of these steps in process 600 may be executed in parallel with one or more of the other steps in 500. For example, after compressed data is received, the compressed data may be segmented and decompressed at the same time that new data is being received. Similarly, as decompressed data is produced, the decompressed data may be reassembled and transmitted on the fly at the same time as new data is being received, segmented and decompressed.

FIG. 7 is a flowchart of another example process for storing data using a direct memory access unit with a lossless coder/decoder (DMA/CODEC). Although the process 700 is described with reference to the flowchart illustrated in FIG. 7, it will be appreciated that many other methods of performing the acts associated with process 700 may be used. For example, the order of many of the operations may be changed, and some of the operations described may be optional.

In this example, the process 700 begins when the DMA engine 402 receives uncompressed data (block 702). For example, the DMA engine 402 may receive uncompressed audio and/or video data. The DMA engine 402 then sends the uncompressed data to the lossless compression engine 404. The lossless compression engine 404 compresses the uncompressed data and stores the resulting lossless encoded data as part of a direct memory access write operation via the DMA engine 402 (block 704).

FIG. 8 is a flowchart of another example process for delivering data using a direct memory access unit with a lossless coder/decoder (DMA/CODEC). Although the process 800 is described with reference to the flowchart illustrated in FIG. 8, it will be appreciated that many other methods of performing the acts associated with process 800 may be used. For example, the order of many of the operations may be changed, and some of the operations described may be optional.

In this example, the process 800 begins when the DMA engine 402 receives compressed data (block 802). For example, the DMA engine 402 may receive compressed audio and/or video data. The DMA engine 402 then sends the compressed data to the lossless decompression engine 406. The lossless decompression engine 406 decompresses the compressed data and sends the resulting unencoded data as part of a direct memory access read operation via the DMA engine 402 (block 804).

In summary, persons of ordinary skill in the art will readily appreciate that methods and apparatus for storing and delivering compressed data have been provided. Among other features, electronic devices employing the disclosed direct memory access (DMA) engine with integrated coder/decoder (CODEC) are able to perform large memory transfers where compression and/or decompression are used (e.g., retrieving compressed video from memory and sending the uncompressed version of the video to a graphics processing unit) with minimal intervention from the central processing unit. As a result, the central processing unit is free to perform other task.

The foregoing description has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the exemplary embodiments disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the invention be limited not by this detailed description of examples, but rather by the claims appended hereto.

Claims

1. A method of storing compressed data, the method comprising: compressing uncompressed data to produce compressed data; andstoring the compressed data, wherein the compressing operation and the storing operation are each part of a direct memory access (DMA) write operation.

2. The method of claim 1, wherein compressing and storing the compressed data is (a) initiated by a central processing unit (CPU) and (b) performed without further interaction by the central processing unit (CPU).

3. The method of claim 1, wherein the compressing the uncompressed data to produce compressed data includes compressing the uncompressed data to produce lossless compressed data.

4. The method of claim 1, further comprising segmenting the uncompressed data and reassembling corresponding compressed data.

5. The method of claim 1, further comprising sending the compressed data via a communication channel.

6. A method of delivering decompressed data, the method comprising: receiving compressed data;decompressing the compressed data to produce decompressed data, wherein the decompressing operation and the receiving operation are each part of a direct memory access (DMA) read operation.

7. The method of claim 6, wherein decompressing and delivering the decompressed data is initiated by a central processing unit (CPU) and performed without further interaction by the central processing unit (CPU).

8. The method of claim 6, wherein the decompressing the compressed data to produce decompressed data includes decompressing lossless compressed data to produce decompressed data.

9. The method of claim 6, further comprising segmenting the compressed data and reassembling corresponding decompressed data.

10. The method of claim 6, further comprising delivering the decompressed data to an output device

11. The method of claim 10, wherein delivering the decompressed data to the output device includes sending the decompressed data to display via a graphics processing unit (GPU).

12. An apparatus for storing compressed data, the apparatus comprising: a direct memory access (DMA) engine structured to perform a direct memory write operation of compressed data; anda compression engine, operatively coupled to the direct memory access (DMA) engine, wherein the compression engine is structured to produce the compressed data as part of the direct memory write operation.

13. The apparatus of claim 12, wherein the direct memory access (DMA) engine is structured to (a) cause the compressed data to be produced in response to an initiation by a central processing unit (CPU) and (b) perform the direct memory storage operation without further interaction by the central processing unit (CPU).

14. The apparatus of claim 12, wherein the compression engine is structured to segment uncompressed data and reassemble corresponding compressed data.

15. The apparatus of claim 12, wherein the compression engine is structured to send the compressed data via a communication channel.

16. An apparatus for delivering decompressed data, the apparatus comprising: a direct memory access (DMA) engine structured to perform a direct memory read operation of decompressed data; anda lossless decompression engine, operatively coupled to the direct memory access (DMA) engine, wherein the lossless decompression engine is structured to produce the decompressed data as part of the direct memory read operation.

17. The apparatus of claim 16, wherein the direct memory access (DMA) engine is structured to (a) cause the decompressed data to be produced in response to an initiation by a central processing unit (CPU) and (b) perform the direct memory read operation without further interaction by the central processing unit (CPU).

18. The apparatus of claim 16, wherein the lossless decompression engine is structured to segment the lossless compressed data and reassemble corresponding decompressed data.

19. The apparatus of claim 16, further comprising a graphics processing unit (GPU) operatively coupled to the direct memory access (DMA), wherein the direct memory access (DMA) engine is structured to send the decompressed data to a display via the graphics processing unit (GPU).

20. A method of storing and delivering data, the method comprising: receiving uncompressed data;compressing the uncompressed data to produce lossless compressed data;storing the lossless compressed data in a memory, wherein the compressing operation and the storing operation are each part of a first direct memory access (DMA) write operation;reading the lossless compressed data from the memory;decompressing the lossless compressed data to produce decompressed data, wherein the decompressing operation and the reading operation are each part of a direct memory access (DMA) read operation; anddelivering the decompressed data to an output device.

21. The method of claim 20, wherein compressing and storing the lossless compressed data is (a) initiated by a central processing unit (CPU) and (b) performed without further interaction by the central processing unit (CPU).

22. The method of claim 21, wherein decompressing and delivering the decompressed data is (c) initiated by the central processing unit (CPU) and (d) performed without further interaction by the central processing unit (CPU).

23. The method of claim 20, further comprising segmenting the uncompressed data and reassembling corresponding lossless compressed data.

24. The method of claim 23, further comprising segmenting the lossless compressed data and reassembling corresponding decompressed data.

25. The method of claim 20, wherein delivering the decompressed data to an output device includes delivering the decompressed data to a display via a graphic processing unit (GPU).

26. An apparatus for storing and delivering data, the apparatus comprising: a direct memory access (DMA) engine structured to perform (a) a direct memory write operation of lossless compressed data and (b) a direct memory read operation of decompressed data; anda lossless compression engine, operatively coupled to the direct memory access (DMA) engine, wherein the lossless compression engine is structured to (c) produce the lossless compressed data as part of the direct memory write operation and (d) produce the decompressed data as part of the direct memory read operation.

27. The apparatus of claim 26, wherein the direct memory access (DMA) engine is structured to (e) cause the lossless compressed data to be produced in response to a first initiation by a central processing unit (CPU) and (f) perform the direct memory storage operation without further interaction by the central processing unit (CPU).

28. The apparatus of claim 27, wherein the direct memory access (DMA) engine is structured to (g) cause the decompressed data to be produced in response to a second initiation by a central processing unit (CPU) and (h) perform the direct memory read operation without further interaction by the central processing unit (CPU).

29. The apparatus of claim 26, wherein the lossless compression engine is structured to segment uncompressed data and reassemble corresponding lossless compressed data.

30. The apparatus of claim 29, wherein the lossless decompression engine is structured to segment the lossless compressed data and reassemble corresponding decompressed data.

31. The apparatus of claim 26, further comprising a graphics processing unit (GPU) operatively coupled to the direct memory access (DMA) engine, wherein the direct memory access (DMA) engine is structured to send the decompressed data to a display via the graphics processing unit (GPU).