Patent Application
20160112069
The present invention relates to apparatus and methods for coding and for decoding. In particular it relates to methods and apparatus for coding and for decoding that apply an implementation of at least an n-state addition over an alternate finite field GF(n) and at least one n-state inverter defined by a multiplication over the alternate finite field GF(n) or an implementation of a truth table defined by said addition and inverter, with n>2, with n>3 or with n>4.
Finite fields GF(n), including classical extension fields are known. Presently certain type of coders apply additions and multiplications over a classical finite field GF(n). This makes certain elements of an encoder and/or decoder relatively predictable. It would make a coded signal of n-state symbols with n>2, n>3 or n>4, including certain check symbols generated as part of a code word less predictable if novel functions with attractive properties as defined in an alternate and currently unknown finite field would be used.
Accordingly novel and improved methods and apparatus for encoding and decoding n-state symbols with functions defined over an alternate finite field are required.
As an aspect of the present invention methods and apparatus for encoding and decoding n-state symbols with n>1, n>2, n>3 and n>4 are provided wherein a single truth table is implemented which is a truth table of an addition over an alternate finite field or a truth table of an addition over the alternate finite field that is modified in accordance with at least one inverter defined by a multiplication over an alternate finite field, wherein an alternate finite field has a neutral element that is not 0.
In accordance with a further aspect of the present invention an apparatus is provided for encoding a first sequence of n-state symbols, each symbol being represented by a signal, comprising an input enabled to receive the first sequence of n-state symbols, a device implementing an addition over an alternate finite field GF(n) with n≧3, and an output that provides a second sequence of encoded symbols.
In accordance with an aspect of the present invention coders, decoders, encryption devices and decryption devices are provided that process a sequence of a plurality of n-state symbols or of a plurality of blocks of n-state symbols by applying at least two different finite fields GF(p) with p≦n.
In accordance with an aspect of the present invention one of the two finite fields GF(p) is an alternate finite field of the other finite field.
The term n-valued or n-state herein is used generally as non-binary wherein n>2, unless the binary case is included. Herein also the term n-state symbol is used. An n-state symbol is a symbol that has one of n states. A symbol or an n-state symbol is a single entity. A symbol herein is being generated or processed as a signal by an apparatus. A symbol such as an n-state symbol can be represented by a single n-state signals that can have one of n states; it can also be represented and processed as a plurality of signals such as binary signals.
Herein also the term check symbol is used. In binary applications one generally uses the term parity bit or symbol. Because the binary check function is the XOR function a check symbol generated by the XOR function is a 0 if there was an even number of 1 s and a 1 if there was an odd number of 1 s. Hence the name parity. The name parity has no such meaning in n-valued functions. Accordingly the name check symbols will be used.
Parity calculation in binary error correction is the process wherein a number of bits in a codeword or sequence or block have for instance an even parity or even number of 1s, including the parity bit. Assume one has an 8 bit code word [a b c d e f g h] and a parity bit p is added. For instance a rule for determining a parity symbol could be: the number of 1 s in [a b c d e f g h p] should always be even.
This can be expressed in the equation a+b+c+d+e+f+g+h+p=0. The operation ‘+’ in this equation is the modulo-2 addition or XOR function.
It is one aspect of the present invention to create a check symbol for a codeword comprised of k n-valued symbols by using a reversible n-valued operation sc1. In n-valued logic one may use different ways or functions to create a ‘parity’ or check symbol. One may use reversible and non-reversible operations. For instance a non-reversible parity n-valued operation is one wherein a 1 is added (modulo-n) to a sum when a symbol is not 0, and a 0 when a symbol is zero. The reversibility is related to determining the original value of the symbols of which a parity symbol is determined.
One method as an aspect of the present invention is to apply reversible n-valued logic operations to calculate the ‘check’ or parity symbol of a sequence of n-valued symbols. The advantage of a reversible operation is that an equation can be solved. For instance two n-valued symbols x1 and x2 combined by a function sc1 will generate a symbol p1 according to the equation: x1 sc1 x2=p1.
Assume that sc1 is self reversing and commutative. In that case (as is for instance explained in U.S. patent application Ser. No. 10/912,954 filed Aug. 6, 2004 entitled: Ternary and higher multi-value digital scramblers/descramblers, which is incorporated herein in its entirety): x1=p1 sc1 x2. For calculation and notation purposes it is sometimes preferred to write the parity symbol equations with a result 0. In that case (x1 sc1 x2=0) can be written for instance as: (x1 sc1 x2 sc1 p1)=0. This is the result of (x1 sc1 x2)=(p1 sc1 0) again with sc1 assumed to be a commutative self-reversing n-valued function.
It should be clear that p1 can also be calculated in a different fashion. For instance by: (x1 sc1 x2)=(p1 sc2 0) so that ((x1 sc1 x2) sc3 p1)=0. Herein the function sc3 is the reverse of sc2. If sc2 is self-reversing then:
((x1 sc1 x2) sc2 p1)=0.
The n-valued self-reversing functions are in general not associative. This means that even though a function may be commutative, the order of variables in a multi-variable equation does matter. The expression (x1 sc1 x2 sc2 p1) should be evaluated as {(x1 sc1 x2) sc2 p1}. In words: first evaluate (x1 sc1 x2) as ‘term’ and then {term sc2 p1}. Assuming sc1 and sc2 being commutative one will get the same results by evaluation {p1 sc2 (x1 sc1 x2)} or {p1 sc2 (x2 sc1 x1)} or {(x2 sc1 x1) sc2 p1}.
To demonstrate the above one may apply two functions: sc1 and sc2, which are self-reversing and commutative. For instance one can use two 4-valued switching functions sc1 and sc2 of which the truth tables are provided below.
Assume x1=1 and x2=2. Then (x1 sc1 x2)=0 according to the truth table of sc1. If one wants (x1 sc1 x2)=(p1 sc1 0) then p1=3. Or (x1 sc1 x2 sc1 p1)=0. For instance (x1 sc1 p1) in this case is (1 sc1 3)=3. And (x2 sc1 3)=(2 sc1 3)=2 which is different from 0. So the expression is not associative. However the expression is reversible when one observes the order of the variables.
For illustrative purposes the associative 4-valued function sc3 is also provided in the following truth table.
It is easy to check that (x1 sc3 x2 sc3 p1)=0 will apply if (x1 sc3 x2)=p1.
Alternate Extension Fields
Binary extension fields or Galois Fields represented as GF(n=2p) with p≧2 are applied in generating n-state check symbols from 2 or more n-state symbols. An n-state or n-valued symbol is a symbol which assumes one of n possible states. One may also use the term n-valued. An n-state or n-valued symbol for processing in an apparatus or a device is represented by a signal. Such a signal may be a single signal, which has one of n states. For instance a 4-state symbol has one of 4 states or values. A 4-state symbol may have the values or states 0, 1, 2 and 3. Each state is represented by a single n-valued signal. For instance the value or state of a signal may be determined by a voltage. It should be clear that it is not required that the states 0, 1, 2 and 3 are represented by 0, 1, 2 and 3 Volt respectively. The 4 different states may be represented by for instance 0.5 V, 1 V, 1.25 V and 1.75 V. Or a state in an n-state signal may be represented by an optical signal of a particular wavelength which in certain cases are considered independent instances of a physical phenomenon. Linear combinations of these independent instances will just mix the states but will not create a signal of a different state. Circuitry or apparatus that processes these type of n-state signals are in general non-linear.
Furthermore, an n-state symbol may be represented by 2 or more signals. For instance, each possible state of a 4-state symbol may be represented by 2 binary signals. To emphasize that a value in an n-valued symbol is a distinguishing property and not a true value the term n-state symbol is preferred.
Extension fields GF(qp) with q≧2 and p≧2 as applied in for instance error correction are in general binary extension field. These extension fields are defined by a finite (n) number of field elements, by a first operation usually called an addition, its reverse being a subtraction, by a function called a multiplication and its reverse called a division all over GF(n). The addition over GF(n=2p) is self reversing, which means that addition and subtraction over GF(n) have the same truth table. Furthermore, the addition is commutative (which means that a+b=b+a over GF(n)) and the addition is associative (which means that (a+b)+c=a+(b+c)=(a+c)+b etc. over GF(n)). The field also has an operation multiply, which is also commutative and associative. And the addition and multiplication are distributive (which means that c*(a+b)=c*a+c*b.) Furthermore there is a neutral element e or a zero element in the field so that an addition a+e=a, wherein a and e both belong to the field. There is a neutral element i (or identity or the one element) so that a*1=a wherein a and i both belong to the field. Furthermore each multiplication a has an inverse a−1 that is also part of the field (except the zero element perhaps). Addition ‘scn’ and multiplication ‘mn’ can be represented as + and *. One should keep in mind that these operations are defined by a truth table and in many cases are different from the standard addition and multiplication.
In general elements of an extension field GF(qp) are generated by a primitive polynomial in q of order p or by a p-state LFSR expressing such a polynomial. Such polynomials are provided for the binary extension fields in for instance the earlier mentioned book of Lin and Costello in appendix A. However, there is more than one minimal polynomial for larger values of n. While there is only one minimal polynomial for GF(4), there are 2 minimal polynomials for GF(8) and 4 for GF(16).
For instance the adder sc81 over GF(8) of paragraph [0113] is created from elements in GF(8) generated by the binary LFSR 1400 of
The state [0 0 0] is the forbidden or degenerative state of the LFSR and represents GF(8) state 0. By modulo-2 addition of the individual binary elements of a GF(8) state one gets the GF(8) addition result. For instance [1 0 0] XOR [0 1 0] →>[1 1 0] which is GF(8) state 4 in accordance with the state diagram. One may run the LFSR with starting state [0 1 0] as initial state (which may be called element 1 in GF(8)). Every element in GF(8) except 0 moves up one place and [0 1 0] is GF(8) 1 and [0 0 1] is GF(8) 2. Then [0 1 0] is GF(8) 4. [0 1 0] XOR [0 0 1] →>[0 1 1] which is the new representation of GF(8). So changing the initial state of the LFSR does not change the addition or the related multiplication.
Another minimal polynomial to generate elements of GF(8) is implemented by the LFSR 1500 of
Herein the XOR addition of GF(8) states 1 and 2 is [1 0 0] XOR [0 1 0] →>[1 1 0] which is GF(8) state 6. Accordingly, a different addition over GF(8) is created. The truth table for this addition over GF(8) is provided by the following truth table:
This function is also self reversing and associative and is distributive with the multiplication of paragraph [0113]. Let's call the addition of paragraph [0113] sc81 and the just created addition sc82. One can create a symbol c1=a1*x1 sc81 b1*x2 by using function sc81 and a different symbol c2=a1*x2 sc82 b1*x2. For instance create the symbols c1 and c2 from x1=2 and x2=6 with a1=3 and b1=5. The two expressions then generate:
c1=3*2 sc81 5*6
and
c2=3*2 sc82 5*6.
Remember that in both expressions the same multiplication m81 of paragraph [0113] is used. This will generate:
c1=4 sc81 3=6
and
c2=4 sc82 3=1.
Assume that in a coder one has to determine x2 from c1 or c2 and x1.
Using c1: c1=3*x1 sc81 b1*x2 which leads to x2=b1−1*(c1 sc81 3*x1) wherein b1−1 is the reverse of b1. (the reverse of multiplier 5 is 5−1 or multiplier 4 as one can derive from the multiplication table.) This leads to x2=4*(6 sc81 3*2)=4*(6 sc81 4)=6. If one would have used the wrong function sc82 one would have as result x2=4*(6 sc82 3*2)=4*(6 sc82 4)=4*7=3.
Using c2: c2=3*x1 sc82 b1*x2 which leads to x2=b1−1*(c2 sc82 3*x1) wherein b1−1 is the reverse of b1. (the reverse of multiplier 5 is 5−1 or multiplier 4 as one can derive from the multiplication table.) This leads to x2=4*(1 sc82 3*2)=4*(1 sc82 4)=4*3=6. If one would have used the wrong function sc81 one would have as result x2=4*(1 sc81 3*2)=4*(1 sc81 4)=4*2=5.
Accordingly, using different adder functions wherein the functions are distributive with the same multiplier. Because there is a limited number of these functions, one may try a limited number of functions to apply the correct one. To further confuse an unauthorized decoder one may create an expression using more than 2 variables and at least 2 different functions. For instance c=a1 sc81 a2 sc82 a3. Herein the order of execution will become an issue. However, solving equations also may become more involved.
One easy generation of an adder over GF(n) such as GF(8) is using consecutive binary representation and adding the elements as before by XORing all bits. This generates the following states over aGF(8) as an example wherein aGF(8) stands for alternate Galois Field.
This will create the following adder sc83 over aGF(8) (by XORing the bits of an element in aGF(8)).
One can apply the multiplication m81 as described herein to the function sc83 for checking if the functions are distributive. This means checking if x1 m81 (x2 sc83 x3)=(x1 m81 x2) sc83 (x1 m81 x3). The functions sc83 is not distributive for m81. However, it turns out sc83 is distributive for a multiplication function m82 which is defined by the following truth table.
Checking if x1 m82 (x2 sc83 x3)=(x1 m82 x2) sc83 (x1 m82 x3) for all possible states of x1, x2 and x3 demonstrates that the combination of sc83 and m82 is distributive.
There are actually several other distributive combinations of self reversing additions over aGF(n) which cannot be generated by an LFSR with multipliers which are not the multiplier m81.
Different classes of adders over GF(n) with n>1 and GF(pq) with p>1 and q>1 wherein n, p and q are integers.
In general a field like GF(4) or GF(8) or GF(2q) cannot be generated from modulo-4 or modulo-8 addition and modulo-4 or modulo-8 multiplication. In order to generate a finite field GF(8) one defines GF(8) as an extension field, such as GF(n=23) by using the earlier shown LFSR methods. However, especially for n>2 there are more reversing and even self-reversing two-input n-state functions than those defined by the classical LFSR methods. First of all, for values greater than 4, there are several different primitive or minimal polynomials of degree q in n=pq of which each will define an addition over GF(pq) as was shown in the case of GF(8). Each of these additions based on a primitive or minimal polynomial has the same multiplier over GF(pq) over which the operation c*(a+b) is distributive. Each of the multipliers has an inverse in the field.
The field generated by XORing, for instance for binary words of 5-bits, over all 32 binary words ranging from [0 0 0 0 0] to [1 1 1 1 1] will create a proper 32-state addition function that is associative. However, as was already shown in the 8-state case, this 32-state addition and the ‘standard’ GF(25) combination are not distributive. In accordance with an aspect of the present invention different adders and reversible multipliers over GF(n) and especially over GF(2q) will be provided that constitute a field which allows these to be applied in n-state coders, n-state decoders, n-state sequence generators, n-state LFSRs and n-state polynomial and arithmetical circuits. Any n-state switching function herein be it an n-state function with at least two inputs and an output or an n-state inverter can be implemented in a switching device. The switching device can be a true n-state switching device wherein an n-state symbol having one of n-states is represented by an n-state signal. In the alternative an n-state switching function, be it an n-state function with at least two inputs and an output or an n-state inverter, can be implemented in a memory device, wherein the corresponding truth table of an n-state function is implemented in a memory. A memory can be a true n-state memory. It can also be a binary memory, wherein an n-state symbol is represented as a binary word, and inputted, stored and outputted as a binary word of binary signals. An analog/digital (A/D) and digital/analog (D/A) converter can be used to generate a true n-state signal from a binary word.
The extension field GF(4) which is a traditional field is defined by the following addition and multiplication over GF(4) sc4 and m4 respectively of which the truth tables are provided in the following tables.
In this case a 4-state symbol can be represented by a 2-bit word. By adding (with XOR) the corresponding bits of two two-bits word one will get the above addition. The functions are associative and distributive. The addition is also commutative and self-reversing. The multiplication is reversible with elements of the field. It is again noted that a multiplication with a constant (or element) of the field is applying an n-state inverter with an input and an output of which the function is defined by a column or a row in the truth table of m4.
A first alternate or not traditional addition over alternate field GF(4) is provided in the following truth table.
This addition is self reversing, it has a ‘zero’ element (symbol 3) and it is commutative and associative. There is a corresponding multiplier which combined with the above adder will be distributive, which means [a m4 (b sc4 c)=(a m4 b) sc4 (a m4 c)]. The truth table of this multiplier is provided in the following table.
The ‘zero’ element is again 3 (any multiplication with 3 results in 3) and the ‘1’ element (multiplying a symbol ‘a’ with this element will again create ‘a’) is ‘0’. Furthermore, a division is defined within this field as each factor of multiplication ‘b’ has a reverse ‘b−1’ which is also an element of the field. (element 0 has 0 as inverse; element 1 has element 2 as inverse; and element 2 has element 1 as inverse. Furthermore, element 3 is the ‘zero’ element).
A multiplier over GF(4) in this case is actually a 4-state inversion. The inversion is indicated by [0 1 2 3] →>[a b c d]. This means that the elements in the vector [0 1 2 3] are transformed into the elements of vector [a b c d] in their corresponding positions or: 0→a; 1→b; 2→c; and 3→d, wherein a, b, c and d are elements of GF(4). The multipliers 0, 1, and 2 are defined by the 4-state inversion [0 1 2 3] →[0 1 2 3] for multiplier 0; [0 1 2 3] →[1 2 0 3] for multiplier 1; and [0 1 2 3] →[2 0 1 3] for multiplier 2. One can easy check that each multiplier has an inverse: 0−1=0; 1−1=2; and 2−1=1. One proof is to multiply for instance 1*2=0 or invert [1 2 0 3] with [2 0 1 3] which will generate [0 1 2 3].
At least one implementation of sc4 and m4 is shown in
In device 2102 input ‘a’ to a device 2100 which implements sc4 is provided with an inverter (or multiplier) inv12110, which may be a multiplier which is defined by a row or column in m4. Assume that inv1 is a multiplier. The resulting symbol on d1 is then determined by {d1=(inv1(a) sc4 b)}. Assume that inv1 is the inverter representing multiplier 2. One can then write the relationship between a, b and d1 as d1=(2 m4 a) sc4 b. It is more common to name m4 as * and sc4 as +. This will create the expression d1=2*a+b, keeping in mind that * and + have a special meaning.
Assume that the top input ‘a’ to a device 2100 determines the rows of the truth table. The truth table of 2100 (sc4) with a multiplier [2 0 1 3] at the top input can be reduced to the single truth table sc41 as provided in the following table.
The circuit of 2102 can thus be replaced by equivalent circuit 2103 which implements a single truth table defined by sc41 and by an expression d1=a sc41 b. It is noted that sc41 is non-commutative.
A similar approach can be taken with circuit 2104 which has an inverter inv12110 in input a and an inverter inv22111 in input b and output d2 is defined by d2=inv1(a) sc4 inv2(b). Assume that inv1 is multiplier 2 and inv2 is multiplier 1. We can then replace the combination of 2100 with the two inverters inv1 and inv2 with the equivalent circuit 2105 with no inverters on the inputs, wherein 2105 implements the single truth table of sc42 which is provided in the following table.
The input b of 2100 is determined by the columns of a truth table. Accordingly, one has to modify the rows of sc4 in accordance with inv1 and the columns of that transformation in accordance with inv2 to arrive at sc42. One can also say that sc4 is modified in accordance with inv1 and inv2. In circuit 2405 the output d2 can be expressed as d2=a sc42 b, noting that if inv1 and inv2 are not identical then sc42 is non-commutative.
Circuit 2106 has an inverter inv32113 at the output. This means that d3=inv3 (a sc4 b), which is a commutative function if sc4 is commutative. The circuit 2106 can be replaced by the circuit 2107 with no inverter at the output and that implements sc43 wherein d3=a sc43 b.
The same approach is applied to reduce 2108 to 2109. One can also say that d4=inv3 (inv1(a) sc4 inv2(b)) is reduced to d3=a sc44 b, wherein sc44 is created by modifying sc4 in accordance with inv1, inv2 and inv3.
The reduction examples have been shown for 4-state fields. These reductions of at least 2 input/1 output truth tables by their applied inverters apply to an n-state truth table with n>2 of a function in a field.
In a further embodiment of the present invention a sequence generator for generating a sequence of n-state symbols, using implementations of the addition and multiplier or the inverter reduced form thereof is provided. In yet a further embodiment the sequence generator generates an n-state pseudo-noise or maximum length sequence of n-state symbols. An n-state sequence generator can be implemented by an n-state Feedback Shift Register (FSR), either in Galois or Fibonacci configuration. An n-state FSR based sequence generator in Galois configuration is shown in
The sequence generator provides a sequence ‘outg’ on an output. In one embodiment of the present invention one has to determine the actual inverters inv1, inv2 and inv3 to generate an n-state m-sequence. In the example a 4-state inverter will be selected from m4 and being [0 1 2 3] which is the identity, [1 2 0 3] and [2 0 1 3]. The inverter [3 3 3 3] is effectively a 0 inverter or open connection. (Keep in mind that ‘0’ herein is merely one of n n-state symbols. What ‘0’ does is determined by a truth table, not by the common interpretation that 0 is nothing and does nothing. The truth tables of sc4 and m4 show that the ‘0’ role is assumed by ‘3’).
A relatively simple method to determine if a sequence is a m-sequence has been developed by the inventor of the present invention for instance in U.S. Pat. No. 7,580,472 to Lablans issued on Aug. 25, 2009 and in U.S. Pat. No. 7,725,779 to Lablans issued on May 25, 2010, which are both incorporated herein by reference. An auto-correlation graph of an n-state sequence can determine if a sequence is an m-sequence or a pseudo-noise sequence. However, the standard method of calculating an n-state auto-correlation graph will show side-peaks. Some sequences, which are not m-sequences, also have side-peaks. This sometimes makes it difficult to determine if an n-state sequence is pseudo-noise. The novel method determines a correlation value by adding a constant value to a sum if corresponding symbols in two sequences are identical and subtracting a constant or nothing when the two symbols are different. This will create a single peak correlation graph for any n-state m-sequence.
By applying this correlation method to the generator 2201 of
The two functions sc in 2201 have inv2 and inv3 respectively at an input. These functions can be reduced to scv12215 and scv22216 respectively by modifying the first function sc in accordance with inv2 and the second sc in accordance with inv3 in accordance with the method as was described earlier herein. Because sc is commutative, the functions scv1 and scv2 will be non-commutative.
The two functions sc in 2301 have inr2 and inr3 respectively at an input. The first function sc also has inr1 at an output. These functions sc can be reduced to scr1 and scr2 respectively by modifying the first sc in accordance with inr1 and inr2 and the second sc in accordance with inr3 as is shown in 2302 and according to the method as was described earlier. Because sc is commutative, the functions scr12316 and scr22317 will be non-commutative.
It is noted that there are other ways to generate an m-sequence equivalent to the m-sequence generated by an FSR based sequence generator. All states of an FSR are deterministic. If an initial state of the 4-state FSR 2301 with elements 2305, 2306 and 2307 of
A sequence generator as provided in
In one embodiment of the present invention a sequence generator applying functions over an alternate field GF(n) such as alternate field GF(4), be it a Gold sequence generator or an m-sequence generator or any other sequence generator, is applied to generate a ‘known’ sequence to be applied in a scrambler in one of the configurations as shown in
It should be clear that the scrambler or coder of
FSR based encoders such as FSR based scramblers are known as streaming ciphers or streaming encoding as they work continuously generating a coded symbol after an input symbol has been entered.
Yet another coder provided in accordance with an aspect of the present invention is a reversible transposition coder wherein symbols in a sequence of symbols are transposed in accordance in part at least with an n-state pseudo-noise or maximum-length sequence generated by using at least an n-state addition and one n-state inverter that are defined over an alternate finite field GF(n) as provided herein. Yet another coder is a coder with a hopping rule based on an n-state pseudo-noise or maximum-length sequence generated by using at least an n-state addition and one n-state inverter that are defined over an alternate finite field GF(n) as provided herein. How to create these transposition encoders and hopping rules and their corresponding decoders is disclosed in U.S. patent application Ser. No. 11/534,777 to Lablans filed on Sep. 25, 2006 which is incorporated herein by reference. This type of encoder can also be applied for hopping type of communication system, wherein a transposition rule determines a hopping rule.
Another coder provided in accordance with an aspect of the present invention is an n-state FSR based scrambler and a corresponding self synchronizing descrambler in Fibonacci configuration using at least an addition function over an alternate field GF(n) and preferably with an addition and an inverter defined by a multiplication over the alternate field GF(n). An illustration of such a scrambler 2500 is shown in
N-state functions and inverters in one embodiment of the present invention are tables stored in addressable memories. Input symbol(s) determine a memory location of an output symbol that, if addressed, is provided on an output as a signal or one or more binary signals. By using A/D and D/A converters the storage and processing of n-state symbols can take place in binary form. For instance for display a converter is used that allows the display of an n-state symbol on a screen as is known in the art. In one embodiment of the present invention the n-state symbols are processed as binary signals by combinational binary circuitry as known in the art. Translation from n-state to binary and binary to n-state signals is achieved by A/D and D/A converters as known in the art.
In accordance with an aspect of the present invention at least one implemented truth table to realize an n-state FSR based scrambler is an n-state truth table of an addition over an alternate field GF(n). Preferably, such a scrambler also implements at least one n-state inverter being defined by the multiplication over the alternate field GF(n). This means that
The self-reversing descrambler 2600 corresponding to the scrambler of
As an example, assume that
Assume that a sequence in =[1 3 0 2 0 2 3 1 3] is inputted on the scrambler of
It is again pointed out that any of the coders and decoders described herein may be implemented in true n-state devices, as disclosed for instance in U.S. Pat. No. 7,218,144 to Lablans issued on May 15, 2007 and U.S. Pat. No. 7,002,490 to Lablans issued on Feb. 21, 2006 and U.S. Pat. No. 7,548,092 to Lablans issued on Jun. 16, 2009 and in U.S. Pat. No. 7,643,632 to Lablans issued on Jan. 5, 2010, which are all incorporated herein by reference in their entirety. N-state memory devices are disclosed in U.S. Pat. No. 7,397,690 issued on Jul. 8, 2008 to Lablans and in U.S. Pat. No. 7,656,196 to Lablans on Feb. 2, 2010 which are incorporated herein by reference. A memory device or a dual memory device with appropriate clocking acts as a shift register element as is known to one of ordinary skill. A shift register and in particular an n-state LFSR can also be implemented in an addressable memory, which may be an addressable n-state memory as is disclosed in U.S. Patent Application Publication Ser. No. 20070088997 to Lablans published on Apr. 19, 2007 and in U.S. Patent Application Publication Ser. No. 20070098160 to Lablans published on May 3, 2007 which are all incorporated herein by reference.
An n-state symbol with n>2 is a designation of a processing unit which is processed by an implementation of an n-state truth table with n>2. An n-state truth table can be a one dimensional truth table that defines an n-state inverter having one input and one output. It is a vector (which may be represented as a column or a row vector) that defines how each of n possible input states of an input symbol is transformed into a state of an output symbol. A reversible n-state inverter transforms one of n states of an input symbol into one of n states of an output symbol, wherein each of n input states is transformed into a unique output state. An inverter can also be non-reversible in which case n input states or transformed into less than n output states. An n-state truth table can also be 2-dimensional wherein an output n-state symbol is determined by 2 n-state input symbols.
An implementation of a 2 dimensional n-state truth table can be an actual active switching device. It can also be a memory device. In that case an n-state output symbol may be addressed by 2 n-state input symbols. Or in other words: an n-state output symbol has an address that is determined by 2 n-state input symbols. Such an n-state truth table can be implemented as for instance a 2 by 2 matrix in a computer program running on a processor with memory such as an Intel® microprocessor with memory running a language such as MatLab® of The MathWorks, Inc. of Natick, Mass. or FreeMat, an open source computer programming language, available from <URLwww.sourceforge.net>. The following truth table of sc4 can be implemented and the function sc4 can be executed in such a processor system.
The following is a listing of a program in MatLab performing all possible 4-state input combinations and the resulting output 4-state symbol of sc4.
The possible states of a 4-state symbol in this program are 1, 2, 3 and 4. Each n-state symbol in this implementation sample is represented by a plurality of binary symbols, wherein a binary symbol or a bit is represented by a binary signal. An n-state symbol is thus represented by a word of binary signals. An illustrative system that implements a truth table and transforms an input to an output is shown in
The following demonstrates the difference between an implementation of sc4 with an inverter [3 1 2 4] at the input that determines a row in the truth table and applying the reduced single truth table sc41 as provided in the following table.
The following is a listing of a program in MatLab performing all possible 4-state input combinations and the resulting output 4-state symbol of sc4 with the inverter [3 1 2 4] at the input that determines a row in the truth table.
The execution takes an extra step for inversion, requiring at least an additional clock pulse.
The following is a listing of a program in MatLab performing all possible 4-state input combinations and the resulting output 4-state symbol of sc41 which is sc4 modified in accordance with inverter [3 1 2 4] at the input that determines a row in the truth table.
The execution of this does not require an extra step for inversion, and does not require an additional clock pulse and is faster than using an implementation of the inverter.
A signal be it binary or n-state with n>2 may be an electric signal, an optical signal, a magnetic signal, a radiation, an magneto-optical signal, an electro-magnetic signal, a mechanical signal or a mechanical impulse, a presence of a material or a quantum-mechanical state or any other physical state of a material that will represent at least one of 2 states in one embodiment of the present invention or at least 1 of 3 states in a further embodiment of the present invention or at least 1 of 4 states in yet a further embodiment of the present invention. In yet a further embodiment an implementation of an n-state truth table, of which an example is provided in
The n-state symbols are representations of actual signals, which may be binary words or any other signals or plurality of n-state signals. Signals have actual values, usually with an intensity or amplitude and other properties such as a wavelength or frequency or any other property. For convenience the n-state symbols are named either [0, 1, . . . , n−1] or [1, 2, . . . , n]. These states or symbols are merely characters that each correspond to a unique signal as known in the art. One should not assume that the symbol 3 for instance corresponds to a signal of 3 Volt.
In accordance with an embodiment of the present invention an n-state scrambler with an n-state FSR in Galois configuration is provided and a corresponding self synchronizing descrambler. Illustrative embodiments are shown in
Galois configuration means a shift register with at least two adjacent shift register elements connected through an implementation of an n-state truth table from an output of a first shift register element to an input of a directly adjacent shift register element in the signal flow direction as is shown in
In one embodiment an FSR with register elements 3003, 3004, 3001 and 3002 is provided wherein two adjacent shift register elements are connected through an inverter as is shown in
In accordance with a further aspect of the present invention a convolutional n-state encoder and decoder is provided for n>2, including a forward encoder, a recursive encoder and a systematic encoder and corresponding decoders. These n-state encoders and corresponding decoders are disclosed in U.S. patent application Ser. No. 11/566,725 with Lablans as named inventor and filed on Dec. 5, 2006 which is incorporated herein by reference. These encoders may be forward coders, recursive coders and systematic coders or any combination thereof and their corresponding decoders. In one embodiment of the present invention the functions and inverters applied in these coders and decoders include at least one addition and one inverter derived from a multiplication over an alternate finite field GF(n).
The coder 3100 is shown in its two component coders 3201 and 3202. Each of the coders is provided with an input sequence of n-state symbols ‘in’. The coders 3201 and 3202 both use a forward connected shift register. Because both shift registers are provided with the same sequence their shift register states will be identical. Coder 3201 has four taps including the start tap with inverters inv113104, inv123105, inv133106 and inv143107 respectively connected to the function ‘sc’ 3113, 3114 and 3115 which for illustrative purposes will all be the addition over alternate finite field GF(n). The output sequence is inverted by inverter inv153108 to create output sequence out1. All inverters herein for illustrative purposes are assumed to be derived from the multiplication over alternate finite field GF(n).
The coder 3202 is similar to 3201, but has one less tap and thus function sc 3116 and 3117 and has inverters inv213109, inv223110, inv233111 and inv243112 to generate sequence out2. All inverters and functions are again defined over alternate finite field GF(n).
The corresponding decoders 3301 and 3302 are illustrated in
To ease the burden of notation in inverters, an equation of a first n-state symbol in1 inputted on an n-state inverter that is defined by a multiplication over an alternate finite field GF(n) can be written as m1*in1, wherein m1 is the position of the column or row in the truth table of the multiplication. Accordingly, the inverter [0 1 2 3] in m4 of the alternate finite field corresponds with ‘0’; [1 2 0 3′ corresponds with ‘1’; [2 0 1 3] corresponds with ‘2’ and [3 3 3 3] corresponds with ‘3’. One should keep in mind that the ‘*’ operation then is different from the commonly used meaning of *. Furthermore, the function sc4 can be replaced with ‘+’. A function ‘sc’ with a first inverter ‘1’ provided with input n-state symbol ‘x1’ and with a second inverter ‘2’ provided with input n-state symbol ‘x2’ to generate n-state symbol y, can be expressed as: y=1*x1+2*x2.
x1=n1+s1+s2+s3
x2=n2+x1+s1+s2
x3=n3+x2+x1+s1
x1=m1+s2+s3
x2=m2+s1+s2
x3=m3+x1+s1
Solving by substitution leads to:
s1=n1+m1 (1)
s2=n1+m1+m2+n3+m3 (2)
s3=n1+n2+n3+m3 (3)
The above equations show that, when the 3 consecutive symbols inputted into the decoders are error free, then the content of shift register is determined. The content of the shift register also reflect the 3 previous correctly generated decoded symbols. Thus if the symbols [n1 n2 n3] and [m1 m2 m3] have been preceded with symbols in error then one can correct some of these errors as is explained in detail in U.S. patent application Ser. No. 11/566,725.
The above equations show [x1 x2 x3] and [s1 s2 s3] as unknowns, while [n1 n2 n3] and [m1 m2 m3] are known entities. This means there are 6 equations with 6 unknowns, which can be resolved with for instance Cramer's rule, wherein ‘*’ and ‘+’ have a meaning as defined by the truth tables of sc4 and m4. Furthermore a division by ‘a’ in a finite field is a multiplication with ‘a−1’. Accordingly, one can solve the above equations also when the inverters in the decoders are not identity inverters ‘0’ or [0 1 2 3].
In a further illustrative example the inverters in
The above establish the following equations for the decoders 3301 and 3302:
For 3301:
2*x1+2*s1+2*s2+s*s3=1*n1;
2*x1+2*x2+2*s1+2*s2=1*n2;
2*x1+2*x2+2*x3+2*s1=1*n3;
For 3302:
1*x1+1*s2+1*s3=2*m1;
1*x2+1*s1+1*s2=2*m2;
1*x1+1*x3+1*s1=2*m3.
The above equations establish 6 equations with 6 unknowns (the generated x1, x2 and x3 and the shift register state s1, s2 and s3). One can resolve the set by substitution and by Cramer's rule for instance. Cramer's rule establishes the determinant for the coefficients of the unknown and unknowns as:
In calculating the corresponding value of the determinants one should keep all the rules of the alternate field GF(4) in mind. When an unknown does not have a coefficient in an equation its coefficient is actually ‘3’ which is the zero-element in the finite field. The value of D is ‘0’, which is the neutral element. The inverse of ‘0’ is also ‘0’.
The unknown ‘s1’ for instance under Cramer's rule is then:
A similar approach is applied to determine s2 and s3.
Accordingly, after receiving a sequence of coded n-state symbols out1 and a sequence of coded n-state symbols out2, one can determine the state of the shift register [s1 s2 s3] that corresponds to these sequences. Using [s1 s2 s3] as the initial state of the shift register in decoders 3301 and 3302 one can determine if these decoders will generate identical output symbols ‘in’ for the next two clock cycles. If that is the case, the sequences out1 and out2 may be considered error free, and previous errors can be corrected by using the calculated state [s1 s2 s3].
A similar approach can be applied to coders that include a recursive shift register and an encoder that includes an uncoded sequence which is usually called a systematic encoder. As an aspect of the present invention a similar approach using the functions over an alternate finite field GF(n) is applied to encoders with at least one shift register in Galois configuration as is disclosed in U.S. patent application Ser. No. 12/774,092 to Lablans filed on May 5, 2010 and which is incorporated herein by reference.
In accordance with an aspect of the present invention an encoder is provided that creates one or more n-state check symbols from one or more n-state data symbols generated by using at least an n-state addition and one n-state inverter that are defined over an alternate finite field GF(n) as provided herein, and that in one embodiment provides an error detection capability in a sequence containing an n-state data symbol and an n-state check symbol and that in a further embodiment provides an error correction capability in a sequence containing an n-state data symbol and an n-state check symbol.
An example is provided using the function addition and at least one inverter based on a multiplication over alternate finite field GF(n) and the following relations in a (7,4) n-state Hamming code to generate 3 n-state check symbols from 4 n-state data symbols
p1=(inv1(x1) sc x2) sc inv2(x3);
p2=(x1 sc x3) sc x4;
p3=(x2 sc x3) sc x4.
Assume that inv1 is multiplier ‘1’ in the alternate finite field GF(4) and inv2 is multiplier ‘2’. The function ‘sc’ is ‘+’ in the alternate finite field. The above equations can then be written as:
p1=1*x1+x2+2*x3;
p2=x1+x3+x4;
p3=x2+x3+x4.
The expression (1*x1+x2) in one embodiment is replaced by an implementation of a non-commutative n-state function. This aspect has been explained earlier above.
It is assumed that only one symbol in the 7 n-state symbols is in error. One can run through all possible error situations with only one data symbol or check symbol in error. One recalculates all check symbols from the received data symbols and then compares the calculated and the received check symbols. The requirements for an n-valued (n,k) code then may be: each of the k data symbols in a n-valued Hamming codeword should be a function of at least 2 check symbols. There are (n-k) check symbols. One check symbol in error should mean just that: only one check symbol and no data symbol is in error. No check symbol in error means that no single error has occurred. What one does with a Hamming code is mapping each state of a codeword into a unique word formed by check symbols. For a (7,4) n-valued Hamming code:
x1=p1, p2,˜p3;
x2=p1, ˜p2, p3;
x3=p1, p2, p3;
x4=˜p1, p2, p3;
no error=˜p1, ˜p2, ˜p3;
p1 in error=p1, ˜p2, ˜p3;
p2 in error=˜p1, p2, ˜p3;
p3 in error=˜p1, ˜p2, p3;
Accordingly all 8 combinations of p1, p2 and p3 are used.
If it is determined that x1 is in error x1 has to be reconstructed from x2, x3, x4, p1, p2 and p3 which are not in error. The equation p2=x1+x3+x4 provides that x1=p2+x3+x4 which establishes the correct value for x1. One can perform a similar calculation to determine x2, x3 and x4 when one of these symbols is in error. The check symbol can also be corrected if desired.
The aspects of determining n-state check symbols and error detection and error correction of an n-state symbol in error based on the check symbols including an n-state Hamming code have been disclosed in U.S. patent application Ser. No. 11/680,719 to Lablans filed on Mar. 1, 2007 which is incorporated herein by reference.
N-state check symbols can be determined from at least 2 n-state data symbols by applying an addition and at least one inverter based on a multiplication over an alternate finite field as disclosed herein. The symbols in one embodiment are arranged in a matrix to determine at least a location of an error which may be called an erasure. Errors can be located by re-calculating the check symbols. Once errors are located one can use the expressions or equations that have been used to determine the check symbols and by using check symbols and data symbols that are known to be error free to create an expression that determines a correct state of a symbol in error. To prevent that multiple errors in a column or a matrix prevent calculating a correct state 2 check symbols can be determined by arranging data symbols in a first matrix and determine a check symbol from a row or a column and arrange data symbols in a second matrix and determine a check symbol from a row or a column from the second matrix. The equations that determine a correct state of a symbol in error are derived from the equations or expressions that generate the check symbols.
The above matrix approach is explained in U.S. patent application Ser. No. 11/969,560 to Lablans filed on Jan. 4, 2008 and in U.S. patent application Ser. No. 12/400,900 to Lablans filed on Mar. 10, 2009 which are both incorporated herein by reference.
An illustrative example is provided using
In a further embodiment also a set of equations is resolved. For instance the following equations apply:
r2=a1*d5+a2*m5+a3*d6+a4*m6;
and
p2=b1*d5+b2*m5+b3*d6+b4*m6.
Herein d6 and m6 are in error and can be resolved from the set of two equations, for instance by applying Cramer's rule. The equations in one embodiment are again implemented by using the function addition and at least one inverter based on a multiplication over alternate finite field GF(n).
In one embodiment of the present invention at least two check symbols are generated by using the function addition and at least one inverter based on a multiplication over alternate finite field GF(n) with two expressions which have at least one n-state data symbol in common as a variable and wherein each check symbol is achieved by arranging n-state data symbols in different matrices. This embodiment is illustrated in
It is noted that in accordance with an aspect of the invention an expression or equation (a*x1+b*x2+c*x3+ . . . m*xk) can be modified to {(x1 sc41 x2)+ . . . } wherein sc41 is an implementation of a single non-commutative n-state function which is created by modifying ‘+’ in accordance with inverters ‘a’ and ‘b’ and wherein the addition ‘+’ function and at least one inverter based on a multiplication are defined over alternate finite field GF(n).
In one embodiment a coder is provided which is based on an n-state Feedback Shift Register (FSR) or expressions that evaluate the states and/or outputs of such an FSR, wherein the FSR through a function is provided with n-state data symbols and one output is a final state of the shift register as a plurality of check symbols, which can be applied to determine if an error has occurred in a sequence containing the data symbols and the final shift register content of the FSR and wherein the FSR and/or the expressions apply the addition ‘+’ function 7605 and 7606 in
In a further embodiment, one may take as a codeword generated by 3600 the word formed by [x1 x2 x3 x4 s1], for instance when both inv1 and inv2 are the multiplier ‘2’ over the alternate finite field GF(4). In that case the distance between all codewords is still 2, thus allowing to determine if a symbol was in error. As an example a word [1 0 3 2 0] is received. The check symbol is re-calculated from [1 0 3 2] to generate codeword [1 0 3 2 3] which is different from the received word, which indicates that an error had occurred.
In one embodiment at least one erasure can be corrected in a coder as shown in
This approach uses the associative a distributive properties of the addition and multiplication. One may replace [0 3 3] with [0*s1 3 3] which is of course [s1 3 3] and means that all states in the first position of a shift register content have to be multiplied with s1, etc. The table shows only the first 10 results of the content of the shift register. One can expand that to any length. It should be clear that after 63 cycles the content will return to the original initial content. The above also means that if an initial state of a shift register is known one can determine the actual content (and the generated symbol) at any time after and before the initial time without having to run the FSR.
The following table shows the content of the shift register of the FSR of
As was described above, the check symbol in a codeword is the content of the first shift register element after 4 cycles and thus entering x1, x2, x3 and x4. From the above one can see that after 4 cycles s1=2*x1+2*x2+1*x3+2*x4. In the earlier example it was shown that [1 0 3 2 0] was received with one symbol in error. Assume that it was decided that x2 is an erasure and that thus s1 was correct. This means that: 2*x2=2*x1+1*x3+2*x4+s1 or x2=x1+2*x3+x4+1*s1 or x2=2. This demonstrates that in one embodiment of the present invention one can determine the correct state of a symbol in error from an expression that determines a state of a check symbol. This approach can be applied for all type of expressions. However, it has here been shown to apply to a coder using at least an addition and an inverter defined by a multiplication over an alternate finite field GF(n) with n=4.
In one embodiment of the present invention the combination of an addition and an inverter defined by a multiplication over alternate finite field GF(n) as applied in coders and decoders as shown in
The addition over an alternate finite field GF(n) and inverters defined over a multiplication defined over an alternate finite field GF(n) as disclosed herein can be used in any reversible coder. For instance it can be applied in a scrambler as disclosed by Kuhlman et al. in U.S. Pat. No. 7,099,469 issued on Aug. 29, 2006 which is incorporated herein by reference. The methods can also be used in for instance the S-box of Feistel ciphers or Feistel networks.
The Feistel network is illustrated in
Word 3703 is modified by an n-state function 3704 against a word K0. The n-state functions implemented in 3704, 3706 and 3708 may be reversible or non-reversible. They have as input a known signal such as a key word K0, K1, . . . Kn or apply some known confusion scheme. These functions have to be applied with the same corresponding key in the coder 3721 and in reversed order in decoder 3722. The n-state functions 3705, 3707 and 3709 in coder 3721 have to be reversible n-state functions and have to be applied in reversed order in their corresponding reversing function in 3722. The reversible n-state functions may be commutative or non-commutative but at least one of them is an addition over alternate finite field GF(n) or is an addition over alternate finite field GF(n) with at least one n-state inverter at an input or an output which is defined by a multiplication over the alternate finite field GF(n) or is an addition over alternate finite field GF(n) that is modified in accordance with an inverter which is defined by a multiplication over the alternate finite field GF(n) and is implemented as a single n-state truth table for instance in a memory device, wherein the truth table may be a non-commutative truth table.
Assume that function 3709 can be represented as sc1 and function 3708 as sc2. Further assume that the reverse of function sc1 is function ds1. This can be illustrated by the expressions c=a sc1 b and a=c ds1 b. In general one applies the adder over GF(2n) as the reversible n-state function. This adder is self-reversing and commutative and can be implemented in a binary logic circuit or a memory device.
The last stage of 3721 can be expressed as Cn=S sc1 Kn and R=An sc2 Cn. The first stage of 3722 has a function 3713 which reverses sc2 and can be called ds2. The first stage of the decoder 3722 can be expressed as Cn=S sc1 Kn and An=R ds2 Kn. This demonstrates that the decoder 3722 reverses the coder 3721. One has to make sure that the generated codeword 3710 which is formed from 3711 and 7312 is entered in the proper way as the to be decoded codeword into decoder 3722. The function 3713 reverses 3709; 3714 reverses 3707 and 3715 reverses 3705.
The structure of a Feistel network, wherein coding includes “rounds” of confusion and substitution are also applied in advanced codes such as Rijndael and the related Advanced Encryption Standard (AES) coding scheme. The rounds herein apply what is called herein a Feistel-like network. This means that a word of k n-state symbols (with n≧2, or n>2, or n>3) and k≧2, is split at least in two sub-words of at least one symbol and wherein at least one of the sub-words is being processed by either an implementation of an addition over an alternate finite field or by an addition over an alternate finite field and an inverter defined by a multiplication over a finite field or by an implementation of a truth table of an addition over an alternate finite field that is modified in accordance with an inverter defined by an alternate finite field. At least the reversible part of for instance DES and AES in one embodiment of the present invention apply functions and inverters defined by the alternate finite fields as defined and explained herein.
How to generate and decode an AES code is for instance provided in U.S. Pat. No. 7,421,076 issued on Sep. 2, 2008 to Stein et al. and U.S. Pat. No. 7,383,435 to Fellerer issued on Jun. 3, 2008 which are both incorporated herein by reference.
Feistel-like or Feistel network based encoders generally work in blocks of n-state symbols. A plurality of symbols that is received sequentially, rather than in parallel are thus considered words or blocks of symbols. These codes are generally called block codes as a coder can operate only after a block of symbols has been entered. The same applies to error correcting coders wherein check symbols are determined over a block of n-state symbols. A decoder cannot complete decoding until all symbols of a block have been entered into the decoder and can be processed.
In accordance with an embodiment of the present invention a two input n-state function of
One may implement an n-state function by using a device 3804 that implements an adder over alternate finite field GF(n) with inverters 3805 and 3806 at the inputs and inverter 3807 at the output wherein at least one of the inverters is defined by a multiplication over the alternate finite field GF(n). An inverter may be identity, which is a direct connection, which may is called a multiplier ‘0’ in the alternate finite field GF(4) as was developed above. In one illustrative example the device 3804 implements the 4-state adder:
In a further example one of the inverters 3805, 3806 and 3807 is 4-state inverter [2 0 1 3] while the other 2 inverters are [0 1 2 3] or identity. Inverter 3805 has input 3802, inverter 3806 has input 3802 while inverter 3807 has an output 3803.
Case 1: inverter 3805 is [2 0 1 3]. The device of
This is clearly a non-commutative truth table. However, the device of
Case 2: In the second example invert 3806 is [2 0 1 3] while the other inverters are identity. This results in a device 3900 that implements a single truth table:
This is also a non-commutative truth table. The device of
Case 3: inverter 3807 is [2 0 1 3]. The device of
This is a commutative truth table. The device of
Case 4: inverter 3805 is [2 0 1 3], inverter 3806 is [1 2 0 3] and inverter 3807 is [2 0 1 3]. The device of
This is again a non-commutative truth table. The device of
It is noted that all of the truth tables after reduction are still reversible. The reduced function can be called scnm.
It has been noted before that in alternate finite field GF(4) that the inverse of inverters are 0→inv 0−1; 1→inv 2−1; and 2→inv 1−1.
For instance, the function device of
In one embodiment of the present invention the device or implementation of
In one embodiment of the present invention a coding device performs a polynomial arithmetical calculation over the alternate finite field GF(n). This means that additions, multiplications and divisions are all performed over the alternate finite field GF(n). The division over such a field is the reverse of the multiplication as was explained earlier. Calculations over finite fields are known. In general one performs these calculations over the classical fields GF(2m). One reason to apply GF(2m) is that symbols over GF(2m) can be represented in binary form as binary words using mainly XOR and AND operations. By using functions over an alternate finite field GF(n) the results become less predictable and hard to analyze for an unauthorized or uninformed receiver of n-state symbols coded or generated over an alternate finite field.
The following patents disclose n-state arithmetic over a finite or Galois field GF(n=2m). U.S. Pat. No. 4,745,568 to Onyszchuk et al. issued on May 17, 1988; U.S. Pat. No. 7,372,960 to Lambert issued on May 13, 2008; U.S. Pat. No. 7,506,015 to Graham issued on May 17, 2009; U.S. Pat. No. 7,711,763 issued on May 4, 2010 which are all incorporated herein by reference. In one embodiment these Galois field calculators apply a shift register to determine a multiplication or division of polynomials or a remainder thereof, such as in U.S. Pat. No. 4,797,848 to Walby issued on Jan. 10, 1989 and U.S. Pat. No. 5,999,959 to Weng et al. issued on Dec. 7, 1999 which are also incorporated herein by reference. While in one embodiment a calculator over an alternate finite field has an implementation of an addition and an inverter both over an alternate finite field GF(n), an implementation may also be an implementation of a single truth table which is a truth table of an addition over an alternate finite field GF(n) modified in accordance of at least inverter which is defined by a multiplication over an alternate finite field GF(n).
Above, at least one alternate finite field GF(4) has been provided. While GF(4) has not many alternate finite fields it still has at least 3 alternate finite fields. It will be shown that for instance GF(8) has many more alternate finite fields.
The following truth tables define two more alternate finite fields GF(4).
The functions sc4a (addition) and m4a (multiplication) form a field: requirements of commutativity, associativity and distributivity are met. There is a neutral element ‘0’ in the multiplication so that 0*x=x for each element in the field. There is also a zero element (which is ‘1’) so that a+(−a)=1 and a+1=a. Furthermore the inverse of every multiplication is also in the field (0→0), (2→3) and (3→2) and 2*3=0 and 3*2=0. Furthermore, every power of an element of the field is also in the field: X2=X*X so that 2*2=3 and 3*3=2, etc.
Yet another alternate finite field GF(4) is defined by:
The functions sc4b (addition) and m4b (multiplication) form a field: requirements of commutativity, associativity and distributivity are met. There is a neutral element ‘0’ in the multiplication so that 0*x=x for each element in the field. There is also a zero element (which is ‘2’) so that a+(−a)=2 and a+2=a. Furthermore the inverse of every multiplication is also in the field (0→0), (1→3) and (3→1) and 1*3=0 and 3*1=0. Furthermore, every power of an element of the field is also in the field: X2=X*X so that 1*1=3 and 3*3=1, etc.
As an example a multiplication of two polynomials over GF(n) defined by sc4a and m4a is provided: (2*x+3)*(3*x+2)=2*3*x2+(3*3+2*2)*x+2*3=0*x2+0*x+0. Keeping in mind that ‘0’ in this field is the neutral element. In a similar manner one may conduct a polynomial division. For instance add 0*x+0 to the above polynomial product, which will create 0*x2+0*x+0+0*x+0=0*x2+1*x+1=0*x2 as 1 is the ‘0’ element. Dividing 0*x2 by (2*x+3) will generate 3*x+0 with a remainder 3. One can check this result by evaluating (2*x+3)*(3*x+0)+remainder which will generate 0*x2.
In one embodiment of the present invention at least one of the functions or inverters used in a coder during coding is changed from being defined in a first alternate finite field to being defined in a second alternate finite field. For instance use the scrambler and descrambler of
We will turn our attention now to alternate finite fields for n>4. It has been shown above that one can a finite field with addition such as sc81 and sc82 and multiplication over GF(8) by a primitive polynomial for instance implemented in a 3-stage LFSR. The number of additions that establish a field combined with a standard multiplication such as above provided multiplication m81 in the n=8 case will increase for n=2m and m>3. For m=4 there are 4 generator polynomials and for m=5 there are 6 and for m=8 there are 34 generator polynomials according to Lin and Costello's Error Control Coding. Each of the additions in these polynomial fields has the ‘standard’ multiplication. The additions and inverters related to the multiplication in such finite fields can be used in coders and decoders as provided herein. It is believed to be a novel aspect that different additions as generated by primitive or minimal polynomials can be used in coders, including reversible coders that are provided herein. It is a further aspect of the present invention that coders and/or decoders provided herein apply inverters or a multiplication defined over the field, which in these cases is known as an extension field. These different additions can also be modified or provided with inverters that are not defined over the finite field.
It has been shown above that addition sc83 is associative, it has a neutral element (0) it is commutative and it is distributive with m82 which also has a neutral element and a zero element. The addition is also self reversing. Furthermore the multiplication has for each multiplier an inverse in the field. Accordingly, sc83 and m82 form an alternate finite field GF(8) in which all of the coders and decoders as already described herein are enabled.
The following truth tables are of combinations of additions and multiplications that establish an alternate finite field over GF(8). One such combination is:
The functions sc8a and m8a establish an alternate finite field over GF(n) with n=8 and can be applied in the coders and decoders as described herein. One can see that m8a is not the traditional multiplication over GF(8).
Another combination that defines an alternate finite field GF(n) with n=8 is:
The functions sc8b and m8b establish an alternate finite field over GF(n) with n=8 and can be applied in the coders and decoders as described herein. One can see that m8b is not the traditional multiplication over GF(8) and is also different from m8a.
All neutral elements in the above addition are ‘0’ (a+(−a)=0) and in the multiplication is 1 (a*1=a).
There are several ways to find the appropriate addition and corresponding multiplication functions by using the required properties of the functions. For instance, one may require that the addition is self reversing. In that case each column and row in the truth table of the addition is a self reversing n-state inverter. Furthermore, one may require that all additions have the field characteristic 2 or that (a+(−a))=e, wherein e is the zero element. A requirement of a field is the existence of e so that a+e=a. This means that at least one column and row are the identity. Communitivity also limits the construction. For each row selected in a truth table the next row selection becomes more restricted as the rows and columns are symmetric around the diagonal of the truth table.
Once one has selected the rows or columns and arranged them in a commutative table, the next check is associativity. After finding a proper addition, a next step is to find a corresponding multiplication. One can limit a search for appropriate rows or columns in a multiplication truth table by first limiting all to be considered n-state inverters to the reversible inverters that are distributive with the addition. The multiplication is also commutative further limiting a search for appropriate n-state inverters. A further limitation is that none of the inverters that are considered for an addition or multiplication should have an identical symbol in an identical position.
The earlier provided examples of alternate finite fields over GF(n) with n=8 have as neutral element ‘0’. In the 4-state case it was already shown that one can also generate an alternate finite field with neutral element ‘3’ or ‘2’ or ‘1’. The same applies for other alternate finite fields, for instance for n=8. For instance, one can construct at least one alternate finite field over GF(8) with neutral element 5. The truth tables of the addition and multiplication that define this field are provided next.
The following illustrative example shows the truth tables of the addition and multiplication that define an alternate finite field GF(8) with neutral element ‘7’.
The following illustrative example shows the truth tables of the addition and multiplication that define an alternate finite field GF(8) with neutral element ‘3’.
The following illustrative example shows the truth tables of the addition and multiplication that define another alternate finite field GF(8) with neutral element ‘3’.
The above shows that there are different alternate fields based on the same addition but with different multiplications.
In accordance with an aspect of the present invention a decoder is provided to a Reed Solomon coder that is enabled to detect at least one n-state symbol in error. A diagram of an illustrative encoder 4000 is shown in
Assume that the sequence of n-state symbols contains 4 n-state symbols [x1 x2 x3 x4], though more symbols may be entered. The shift register starts with an initial content [s1 s2]. Assume that sc is an addition ‘+’ over an alternate finite field GF(n) and inverters inv1 and inv2 are constant multipliers ‘a’ and ‘b’ in the alternate finite field. This means that all functions are associate, distributive and commutative and the ‘+’ herein is self reversing. The following table shows the calculated states of the shift register starting with [s1 s2] as x1 and x2 are entered, as developed by executing the functions that are implemented in the coder.
One can see that the expressions in each state as the FSR advances in processing greatly accumulate in terms. One can take at least two approaches in showing the individual states of the FSR at each clock cycle: show the evaluated state by performing the expressions for each cycle. However, this requires the actual states of symbols. In an embodiment of the present invention one provides the coefficients of the dependent terms like s1, s2, x1, x2, x3 and x4 etc. The coefficient of a term containing for instance s1 does not depend on any other term, but only on the functions such as additions and multiplications. The end state of the shift register is then dependent on s1, s2, x1, x2, x3 and x4 and can be expressed as c1*s1+c2*s2+c3*x1+c4*x2+c5*x3+c6*x4 and can be represented as [c1 c2 c3 c4 c5 c6]. During processing a term c5*x3 can be achieved by composite processing. As an illustrative example c5*x3=(t1*x3+t2*x3)*t4. Because of properties of the functions in the alternate finite field one can simply apply multiplication and addition to calculate c5=t4*(t1+t2).
The simplest way to represent the states of the shift register is to represent each shift register as dependent upon the variables s1, s2, x1, x2, x3 and x4. For instance the initial content of the first shift register element in
The end state of the first shift register element is determined by: 3*s1+3*s2+0*x1+2*x2+2*x3+1*x4. So, if the shift register's initial state was [3 3] and x=[0 1 2 3] then the end state of the first shift register element is [3*3+3*3+0*1+2*1+2*2+1*3]=[3+3+1+5+6+3]=0.
As a further aspect of the present invention a coder such as provided in
All the steps as described above can easily be performed by a processor. If one performs the reverse steps (or down direction) starting with the states as determined in the forward direction (or up direction) then one will arrive at initial shift register state [3 3 3 3 3 3] and [3 3 3 3 3 3] as is to be expected.
If no errors have occurred, all the shift register states going up have to be identical to the shift register states going down or in reverse. As a further aspect of the present invention corresponding states going up and down are compared. Because addition in the alternate finite field is identical to subtraction one may add corresponding states. The sum of corresponding states then has to be the all zero elements or [3 3 3 3 3 3]. The sum (or subtraction) of all corresponding states is shown in the following table.
Because it is known that all comparative states are the zero state (or state 3 in this case) one can now determine if a received symbol was in error. One can see that each comparative state has at least one component that is in state 3. This means that no matter what state that component is, the comparative state is not influenced by the state of such component. For instance comparative state of sr1 at t=1 the comparative state is [2 2 3 0 1 0] and the symbol x1 contributes 3, so it does not depend upon x1. This also means that if x1 is received in error, then the comparative state of sr1 will still be 3 if all other symbols were correct.
As an illustrative example assume that what is received is [s1 s2 x1 x2 x3 x4]=[1 7 0 1 2 3]. Entering these states in the comparative table and evaluating the expressions will lead to:
One may conclude that if only one error can occur, then based on this evaluation no error has occurred.
Assume that what is received is [s1 s2 x1 x2 x3 x4]=[1 7 7 1 2 3]. Entering these states in the comparative table and evaluating the expressions will lead to:
Because there are comparative states that are not 3 there is a symbol in error. Because sr1 at t=1 is state 3 it can be determined that x1 as received is in error.
As only x1 is in error, the end state of sr1 is not in error. Recall that [s1 s2 x1 x2 x3 x4]=[1 7 7 1 2 3] was received. Thus for instance comparative state sr1 at t=4 should be 3 or: 0*s1+3*s2+0*x1+5*x2+6*x3+3*x3=3. Or: 0*x1=0*1+3*7+5*1+6*2+3*3=1+3+7+4+3=0, which was the correct state of x1.
The outcome of the comparative states depends on the selected inverters. In one embodiment of the present invention one creates a computer program, for instance in Matlab® of The Mathworks of Natick, Mass. that implements the up and down version of an FSR and determines the comparative states based on different inverters. Preferably at least one inverter is defined by a multiplication over the alternate finite field GF(n) and at least one function sc is defined by the alternate finite field. Based on a selected inverter one can review the comparative states and determine which configuration is most convenient to determine at least one symbol in error.
In accordance with a further aspect of the present invention an FSR with at least three (3) shift register elements is created to determine three check symbols and send a word of a plurality of data symbols and the at least three check symbols to a receiving device that implements the comparative states calculations as explained herein. This allows the receiving device to determine at least 2 symbols in error. How detectable symbols in error are distributed over a codeword depends on the selected inverters.
In accordance with a further aspect of the present invention a very long sequence, much longer than the number of shift register elements, can be coded this way into a word with only two or more shift register elements. The number of comparative states will increase. However, the method as provided herein will still identify a symbol in error. At least for a small number of errors that appear in a burst of consecutive errors, the herein provided methods can be arranged to provide a fast way to determine an error location and resolve the symbols in error, for instance as compared to standard Reed Solomon methods. This is especially true for detecting one or more consecutive errors in a long sequence or even a very long sequence of symbols.
In one embodiment of the present invention the up/down approach is applied to a sequence of binary symbols. For instance, a coder as illustrated in
One is reminded that 0 herein means that that symbol does not contribute to the state and 1 means it does. For t=1 one can thus express the two comparative states as sr1→(s1≠s2≠x2≠x3) and sr2 (s1≠x1≠x3≠x4). This means that if bit x1 is in error sr1 will be 0 but sr2 will be 1.
A similar result can be achieved for binary coders with 3 or more shift registers and with binary coders wherein at least one implementation of an EQUAL (=) function or an XOR function with an inverter [1 0] is used.
The above methods for error location and error correction also apply to alternate finite fields for n is smaller than 8. One example is n=4. The following provides an addition and a multiplication over an alternate finite field GF(4).
Using the configurations of
The state corresponding to t=1 is the initial state. In an example this state should be [3 3]. Assume that a word [s1 s2 x1 x2 x3 x4]=[1 2 3 1 2 0] was received. The evaluated comparative states based on the received word are:
From the earlier individual components based comparative states one can see that for t=1 (wherein the comparative state of sr1 is 3) that comparative state sr1 does not depend upon x1, while the other comparative states do. As a check one can also see that the same is the case for the end state of sr2. Accordingly x1 is in error. And one can solve, as before, x1 by solving for instance the expression that determines the comparative end state for sr1. The expression is 0*s1+3*s2+2*x1+0*x2+2*x3+2*x4=3. Or 2*x1=0*s1+3*s2+0*x2+2*x3+2*x4. The word [1 2 3 1 2 0] was received or: 2*x1=0*1+3*2+0*1+2*2+O*0=1+3+1+1+1=3. Or x1=2−1*3=3. Thus x1=3.
In the above alternate finite fields of order n=2p have been disclosed. As illustrative examples self reversing additions over such fields have been provided. As is known to one of ordinary skill a field can also be over n is an odd number. In particular prime fields wherein n is prime or Zn are of interest. These and other fields are of interest in certain coders such as Elliptic Curve Coders. In many of these cases the ‘normal’ field is usually defined by using the modulo-n addition and the modulo-n multiplication. In accordance with an aspect of the present invention an alternate finite field is created over GF(n) wherein n is prime. As an example an alternate finite field over GF(5) is provided that is defined by the following addition and multiplication.
The functions sc5a is commutative, associative, it has a ‘0’ element (4) so that “x sc5a 4=x” and it is distributive with m5a which has a zero element 4 and a neutral element ‘0’ and which function is also commutative and associative. Furthermore, each multiplier has an inverse that is also in the alternate finite field: 0 has itself as inverse, the inverse of 1 is 2, the inverse of 2 is 1, and the inverse of 3 is 3.
The following table provides an addition and multiplication that establish an alternate finite field GF(5).
Each multiplier has an inverse in the field: 0 is the identity; 1 is self reversing; 2 has 4 as inverse and 4 has 2 as inverse.
Other alternate finite fields over GF(5) can also be constructed with 0 as identity element and 1 or 2 as the neutral element.
The following tables provides additions and multiplications that establish an alternate finite field over GF(7).
All multipliers are also in the alternate finite field.
The following tables also establish an alternate finite field GF(7).
Again, all multipliers not being the zero element have an inverse in the field.
The following 3-valued or ternary function establishes a standard finite field GF(3).
One can easily check that the following 3-valued or ternary functions also establish an alternate finite field.
One can generate the states for an n-state extension field with n=32 with a 2-stage FSR 6000 with elements 6003 and 6004 with one of the above 3-state additions and an inverter being one of the inverters in the field in a sequence generator as shown in
One way to generate an alternate field over GF(9) is to for instance determine that the new ‘zero’ or neutral element of the alternate field is 5. This means that ‘a+5=a’ or: the row and column corresponding to element 5 should be [0 1 2 3 4 5 6 7 8]. A way to achieve that is to invert the whole truth table of sc9 with the inverse of the column or row of element 5 because 5−1(5)=e. This means that the new column of element 5 in the inverted truth table should be [5 0 7 6 3 1 4 8 2]−1=[1 5 8 4 6 0 3 2 7]. The functions sc9a generated by inverting sc9 with the above inverter will create:
One should first check if sc9a is associative. One can create m9a by first setting column and row of 5 to all 5 (as this is now the neutral element). Furthermore, one can determine all reversible 9-state inverters that are distributive with sc9a and construct the truth table m9a from the compliant inverters. A simple computer program will demonstrate that sc9a and m9a are distributive. There is a zero element, the multiplication has an identity (0), all non-zero elements in the field have an inverse that is also in the field, the functions are commutative. Accordingly, sc9a and m9a establish an alternate finite field GF(9). Other alternate finite fields can be constructed in a similar way.
Galois Field (or finite field) arithmetic is widely used in cryptography. The applied fields can be for instance a field GF(p) with p being prime, or extension fields GF(pm) with p being prime and m>1, wherein p preferably is 2, or composite fields GF((pm)r) with p being prime and m and r>1, or a prime field such as a Mersenne prime field GF(n) with n≈pm and preferably n≈2m. For instance Odd Characteristic Extension Fields including Optimal Extension Fields are known that are defined over GF(n)=GF(2m±c) as disclosed for instance in U.S. Pat. No. 7,069,287 issued on Jun. 27, 2006 to Paar et al. which is incorporated herein by references. One application of finite field arithmetic is in Elliptic Curve cryptography, wherein product symbols based on an elliptic curve over a finite field is generated from the to be coded symbols and random numbers. How to apply a Galois Field in elliptic curve cryptography is also disclosed in U.S. Pat. No. 5,351,297 issued on Sep. 27, 1994 to Miyaji et al. which is incorporated herein by reference. The use of binary fields or binary extension fields in elliptic curve cryptography is disclosed in U.S. Pat. No. 6,721,771 issued on Apr. 13, 2004 to Chang which is incorporated herein by reference. It has been shown already above that alternate finite fields exists for binary, binary extension fields and prime fields and prime extension finite fields. Any field (if it is a traditional or an alternate field) as is known in the art has a minimal set of common properties. However, where at least one class of alternate finite fields differ from traditional finite fields is that the neutral or ‘zero’ element is not 0. Name the neutral element ‘e’ and ‘a’ is any element in a finite field not being ‘e’ then ‘e’ is defined as ‘a+e=a’ with ‘+’ being the addition over the field and wherein the neutral element e′ is not 0 in at least one class of alternate finite fields. A parallel definition in the alternate finite field is related to the multiplication ‘*’ over the finite field. Herein ‘e*a=e’ for all states of ‘a’ including all states not being ‘e’ and wherein ‘e’ is not ‘0’. As the same field properties to traditional finite fields apply to alternate finite fields one may define an elliptic curve over an alternate finite field and develop the cryptography over that elliptic curve in a similar way as in the traditional finite field but now by applying the alternate finite field. In general one applies finite field arithmetic by using a modulo-polynomial calculation. However, a much faster way is to either store the truth table or calculate the elements of the truth table from a known inversion as was explained above. This allows for very fast calculations in binary logic if one so desires. Thus an embodiment is provided of an elliptic curve encoder and a corresponding decoder that applies addition and multiplication (and division when required) over an alternate finite field.
An encoder is provided that modifies the statistical distribution of symbols in a coded message as disclosed in U.S. patent Ser. No. 7,659,838 issued on Feb. 9, 2010 to Lablans, which is incorporated herein by reference. In one embodiment of the present invention as illustrated in
The above approaches also apply to the generation of other classes of alternate fields GF(qp) with q≧2 and p≧1 or p≧2.
An alternate finite field GF(n) is not a classical finite field. The existing literature in Field Theory uses in general 0 as the neutral element or as the zero element ‘e’ of a field so that ‘a+e=e’. At least one class of an alternate finite field GF(n) herein is defined as the field GF(n) defined by the addition scn wherein an element not represented by the field element 0 is the neutral element and by a corresponding multiplication. It is noted that a field can be defined by a single addition and one of a plurality of possible multiplications.
In accordance with an aspect of the present invention an implementation of at least one addition over an alternate finite field GF(n) and at least one inverter defined by a multiplication over an alternate finite field GF(n) with n≧3 is applied in an encoder as provided herein.
In accordance with an aspect of the present invention an implementation of at least one addition over an alternate finite field GF(n) and at least one inverter defined by a multiplication over an alternate finite field GF(n) with n>3 is applied in an encoder as provided herein.
In accordance with an aspect of the present invention an implementation of at least one addition over an alternate finite field GF(n) and at least one inverter defined by a multiplication over an alternate finite field GF(n) with n>4 is applied in an encoder as provided herein.
In accordance with an aspect of the present invention an implementation of at least one n-state function which is defined by a truth table that is a reduction of an addition over an alternate finite field GF(n) and at least one inverter defined by a multiplication over an alternate finite field GF(n) with n≧3 is applied in an encoder as provided herein.
In accordance with an aspect of the present invention an implementation of at least one n-state function which is defined by a truth table that is a reduction of an addition over an alternate finite field GF(n) and at least one inverter defined by a multiplication over an alternate finite field GF(n) with n≧3 is applied in an encoder as provided herein.
In accordance with an aspect of the present invention an implementation of at least one n-state function which is defined by a truth table that is a reduction of an addition over an alternate finite field GF(n) and at least one inverter defined by a multiplication over an alternate finite field GF(n) with n>3 is applied in an encoder as provided herein.
In accordance with an aspect of the present invention an implementation of at least one n-state function which is defined by a truth table that is a reduction of an addition over an alternate finite field GF(n) and at least one inverter defined by a multiplication over an alternate finite field GF(n) with n>4 is applied in an encoder as provided herein.
In accordance with an aspect of the present invention an alternate binary finite field is defined by an addition being the EQUAL (‘=’) function and a multiplication being the OR function. Extension fields created from the EQUAL and the OR function from primitive or minimal polynomials may also be called alternate finite fields. However, they may also be considered as a different type of alternate finite field compared to those that cannot be generated from primitive or minimal polynomials only.
In accordance with an aspect of the present invention an encoder that is provided in accordance with an aspect of the present invention is provided with a corresponding decoder.
In accordance with an embodiment of the present invention an encoder and a corresponding decoder use at least an implementation of an addition over an alternate finite field GF(n). In such an embodiment inverters may be used or the addition may be modified in accordance with an inverter. In a further embodiment an inverter defined by a multiplication defining the alternate finite field GF(n) is required or an implementation of an addition in accordance with an inverter over the alternate finite field is required.
In some cases only illustrative examples of a 4-state or an 8-state or an n-state encoder and or decoder is provided. It is fully contemplated that similar encoders and decoders in any of the alternate finite fields GF(n) can easily be constructed by one of ordinary skill without undue experimentation. Any additional effort may come from the increased number of states of GF(n>n1) if n1 is greater than n and not from different principles.
In accordance with a further aspect of the present invention the here provided methods of encoding and decoding are used in a system, such as a communication system. Such a communication system may be a wired system or a wireless system. Such a system may be used for data transmission, telephony, video or any other type of transfer of information. A diagram of such a system is provided in
At the receiving side a receiver 1107 may receive, amplify, and demodulate the signal coming from 1103 and provide a digital signal to a decoder 1104. The decoder 1104 applies the methods provided herein to decode symbols including correcting symbols in error. A decoded and/or error corrected signal is then provided to a target 1105. Such a target may be a radio, a phone, a computer, a tv set or any other device that can be a target for an information signal. A coder 1102 may also provide additional coding means, for instance to form a concatenated or combined code. Additional information, such as synchronization or ID information, may be inserted during the transmission and/or coding process.
In accordance with another aspect of the present invention the here provided methods and apparatus for coding including error correcting coding and decoding including error correcting decoding of signals can also be applied for systems and apparatus for storage of information. For instance data stored on a CD, a DVD, a magnetic tape or disk or in mass memory in general may benefit from error correcting coding. A system for storing symbols coded in accordance with an aspect of the present invention is shown in diagram in
The methods and apparatus here provided can be implemented using a general processor, a dedicated signal processor or customized logic. N-valued symbols may be processed as binary words, being created from n-valued symbols by Analog/Digital converters. After being processed n-valued signals may be created from binary words by applying Digital/Analog converters. Switching functions may be created as customized n-valued circuits. For instance U.S. Pat. No. 6,133,754 by Olson, issued Oct. 17, 2000 entitled “Multiple-valued logic circuit architecture; supplementary symmetrical logic circuit structure (SUS-LOC)” discloses embodiments of n-valued CMOS switches. In U.S. patent application, application Ser. No. 11/000,218 filed Nov. 30, 2004 entitled “Single and composite binary and multi-valued logic functions from gates and inverters” which is incorporated herein by reference in its entirety, it is shown how n-valued logic circuits can be created. N-state logic embodiments, for instance using look-up tables are also contemplated.
It has been shown in for instance U.S. Published Patent Publication Ser. No. 2007009160 to Lablans published on May 3, 2007 which is incorporated herein by reference in its entirety that an FSR, with may be part of a scrambler or a descrambler is implemented in an addressable memory and using an implementation of an n-state switching function. In one embodiment of the present invention an FSR implemented with an addressable memory applies an implementation of an addition over an alternate finite field, or an implementation of an addition over an alternate finite field and an inverter defined by a multiplication over an alternate finite field, or an implementation of a single truth table of an addition over an alternate finite field modified by an inverter defined by a multiplication over an alternate finite field.
In some encipherment applications security comes from large finite fields GF(n), preferably with n being prime and in certain cases with n≈2p to facilitate binary execution. Elliptic Curve Coding coders and AES coders are an example of that. In accordance with an aspect of the present invention instead of n being a large prime, n can be a much smaller integer but with many different alternate finite fields are used. For instance n=251 (which can be represented by 8 bits) has hundreds of alternate finite fields. Furthermore, there are different alternate finite fields having the same addition but different multiplications as was shown herein. In a coder and a decoder instead of one large finite field or one large alternate finite field many different smaller alternate finite fields are applied. And rather than calculating a state in a finite field by applying complex Galois field or polynomial arithmetic the states are stored in an addressable memory, which makes processing much faster. Additional security is introduced by determining which alternate finite field to apply for instance based on a key or a pseudo-random sequence of symbols. In a further embodiment of the present invention, the order of alternate finite fields is changed per message, per time period or by any other pre-determined parameter that can be synchronized between sender and receiver.
It is again noted that a finite field and an alternate finite field are defined by an addition and a multiplication. In one embodiment of the present invention it is a requirement that an encoder or a corresponding decoder applies at least an implementation of an addition over an alternate finite field. This automatically requires that a multiplication over the alternate finite field also exists, even if such multiplication or an inverter defined by such multiplication is not used. This means that an addition over a classical field GF(6) does not exist. Such an addition conceivably would be a modulo-6 addition. However, no set of multiplications in combination with the modulo-6 addition exists to create a finite field. Accordingly, an addition over a finite field, be it a classical field or a class of alternate fields, requires a corresponding multiplication.
As an example of a small alternate finite field that defines a group over an elliptic curve an illustrative example will be provided for n=8 which will be applied to an example as provided on the website of Certicom® of Mississauga, Canada with URL of pages <URLwww.certicom.com/index.php/44-quiz-3> and <URLwww.certicom.com/index.php/44-quiz-3-solutions>. The page defines a field GF(8) defined by the polynomial x3+x+1 and provides an elliptic curve y2+xy=x3+g2x2 g6. Rather than working in binary represented states, the truth table of classical addition and multiplication over this field can be provided as follows:
The curve then should be written as y2+xy=x3+3x2+7. One can easily check that the following points in the field lie on the curve: (2,0) and (2,2), (4,5) and (4,7) and (0,4) as was provided in the Certicom® example. The points (1,0) and (1,1), (6,0) and (6,6) among others also lie on the curve. The coordinates of 2P of P=(4,1) can be determined as (5,2). As the correct solution for developing 2P one should apply the formula yR=s(xP+xR)+xR+yP, which leads to 2P=(5,2).
In an alternate scenario one uses the alternate finite field defined by:
One curve is defined as y2+xy=x3+x2+4. The terms without coefficient actually have coefficient 0 in accordance with the field and the curve over the alternate finite field is 0*y2+0*xy=0*x3+0*x2+4. Points in the alternate finite field that lie on the curve are: (0,5) and (0,7); (1,0) and (1,2); (4,1) and (4,5) and (3,1). These points are generated by evaluating all points of the finite field and checking if they are one the curve. One can easily check that for all generated points on the curve (−P)=(xP, xP+yP) when P=(xP, yP) wherein ‘+’ is sc8e2. Determining 2P when P is (4,1) using the proper addition and multiplication rules over the alternate finite field will lead to: 2P=(0,6). Accordingly, it has been shown that the calculations as required for elliptic curve coding in a finite field can also be performed in an alternate finite field.
In one embodiment of the present invention an encoder or a decoder includes an implementation of a multiplication over an alternate finite field. If a constant multiplier or an equivalent inverter is required one can provide a constant input symbol on at least one input of such a multiplication which then in effect implements a constant multiplier.
It has been provided above that alternate finite fields with zero-elements not being 0 can be applied for instance in coding, decoding, encryption and decryption purposes in accordance with one or more aspects of the present invention. A test for an alternate finite field GFa(n) is to check the existence of a zero-element z, so that z+i=i and z*i=z, for each element i of the alternate finite field and a neutral element e exits so that e+e=z and e*i=e for each element of the alternate finite field and all associative and distributive properties apply in the alternate finite field. For instance (i1+i2)+i3=(i1+i3)+i2; (i1*i2)*i3=(i1*i3)*i2; and i3*(i1+i2)=i3*i1+i3*i2, wherein ‘+’ and ‘*’ are the addition and the multiplication over the alternate finite field.
It would be beneficial if a large number of alternate finite fields can be generated at will. This allows for instance n-state symbols to be generated in a code or for encryption to apply one of different alternate finite fields. Correct decoding and/or decryption then requires application of the same alternate finite field, which contributes to security of a code or encryption. It is noted that alternate finite fields are isomorphic to the finite fields that are for instance extension fields or composite fields. By having a different zero element in different alternate finite fields, there is no clear bijection between field elements. In other words, one cannot simply try different field element substitutions to find an alternate finite field.
In accordance with an aspect of the present invention a method is provided to create a plurality of different alternate finite fields from a given finite field. The steps of such a method are illustrated in
The inverter ‘rinv1’ that inverts ‘inv1’ back to identity must also be determined. For instance one can generate all 8-state 40320 reversible inverters, including identity. Select one inverter ‘inv1’ for instance inv1=[5 7 1 2 4 3 0 6] as illustrated in step 3601. Determine the reversing 8-state inverter ‘rinv1’ from ‘inv1’ as illustrated in step 3603. The inversion of the above example is rinv1=[6 2 3 5 4 0 7 1].
In accordance with steps 3605 and 3607 the rows and columns of the truth table of a given addition and multiplication over GF(n) are modified in accordance with the inverter ‘inv1’ followed by a substitution of all the states by inversion with ‘rinv1’.
The steps are further illustrated by
An example is illustrated in
There are thus 40,319 different alternate finite fields that can be generated from a single finite field over GF(8). The number of possible reversible n-state inverters depends on n! (n factorial). That means that for GF(256) one can find over 10100 or over a googol of alternate finite fields. In accordance with an aspect of the present invention a first n-state symbol is generated or transformed using an addition and a multiplication over a first alternate finite field GFa(n) and a second n-state symbol is generated or transformed using an addition and a multiplication over a second alternate finite field GFa(n). A receiver is familiar with which alternate fields are applied and applies or recovers the first and the second n-state symbols. In accordance with an aspect of the present invention at least one alternate finite field has a zero element not being zero. In accordance with an aspect of the present invention at least both alternate finite fields have a zero element not being zero.
In accordance with one or more aspects of the present invention, the addition and multiplication over an alternate finite field GFa(n) with n>2 are applied in one or more of the applications, inventions or embodiments enclosed herein or incorporated herein by reference, including but not limited to n-state methods and devices with n>3 or with n>7: scramblers and descramblers, shift register based scramblers and descramblers, FSRs, sequence generators, Gold sequence generators, sequence detectors, correlation circuits, convolutional coders and decoders, Reed-Solomon coders or any other error-correcting coder and decoder, encryption and decryption devices and Galois Field arithmetical methods and devices.
In one embodiment of the present invention, an addition and a multiplication over an n-state alternate finite field GFa(n) are generated from an addition and multiplication of a given finite field GF(n). A given finite field may be an extension field, such as a binary extension field indicated by GF(n=2k). Elements of such an extension fields and their order can be determined by using a binary FSR of k shift register elements determined by a primitive polynomial of degree k. The addition of two elements over such an extension field can be determined by individual XORing of the bits in the binary representation of two n-state elements. The multiplication can be determined by shifting (n−1) elements as shown in the multiplication table of
In one embodiment of the present invention the alternate finite field is determined relative to the given finite field by the method depicted in
In one embodiment of the present invention the alternate finite field is determined relative to the given finite field by the method depicted in
In one embodiment of the present invention the alternate finite field is determined relative to the given finite field by the method depicted in
In one embodiment of the present invention the alternate finite field is determined relative to the given finite field by the method depicted in
In one embodiment of the present invention the alternate finite field is determined relative to the given finite field by the method depicted in
In one embodiment of the present invention the alternate finite field is determined relative to the given finite field by the method depicted in
In one embodiment of the present invention the alternate finite field is determined relative to the given finite field by the method depicted in
The inventor has provided in earlier cited U.S. patent application Ser. No. 13/846,296 a novel type of shift register based coders, scramblers and decoders and descramblers that are provided with a second sequence of external data, as a key sequence. In another embodiment thereof, the scramblers can be operated in a public and a private mode. In accordance with an aspect of the present invention the shift register based devices and methods are implemented using at least one addition and one multiplication over an alternate finite field GFa(n).
It is noted that all n-state finite fields are isomorphic. It is common to define a binary extension field based on the XOR or modulo-2 addition. For reference purposes a given finite field may (but is not required) to be related to a modulo-n addition if n is prime or to a modulo-p addition if n=pk or if n is a composite field wherein n is factorized in p. All modulo-k additions (and multiplications) have 0 as the zero-element. This is useful to distinguish between a given finite field and an alternate finite field. One should be aware that there are thus alternate fields with the zero element being 0, but wherein no relation or no direct relation exists with modulo-n or modulo-p addition.
Finite field functions are presently implemented in XOR functions. In accordance with an aspect of the present invention one or more functions over an alternate finite field, be it an addition, a multiplication or a multiplier modified addition are retrievably stored in a physical memory device, wherein each element in a table can be addressed and retrieved. A memory device can be an electrical device, an optical device, a magnetic device or any other device that is configured to store an n-state truth table and wherein each n-state symbol can be stored, addressed and retrieved.
A division over a finite field is the reverse of a multiplication over that field. It has been show earlier and it can be easily checked that a constant multiplier over a finite field can be represented by its equivalent n-state inverter, for instance represented by the corresponding column or row in the truth table of the multiplication. A division is a reversal of a multiplication. A constant division can also be represented by its equivalent n-state inverter, for instance represented by the corresponding column or row in the truth table of the multiplication. That is: the reversing inverter of a multiplication is also a row or a column in the truth table of the multiplication. Accordingly, a multiplication over a finite field also defines a division over a finite field. Similarly, an addition over a finite field also defines a subtraction over the finite field.
Many coders and encryption devices, including processors configured to perform coding and encryption as well as decoding and decryption, apply finite field arithmetic, which is also known as galois field arithmetic. In accordance with an aspect of an aspect of the present invention an alternate galois field arithmetic device is provided that performs a galois field addition and a multiplication, or a galois field addition and a division, or a galois field subtraction and a multiplication, or a galois field subtraction and a division over an alternate finite field wherein a zero element is not 0. Because all finite field arithmetical rules apply to operations over an alternate finite field a valid result will be generated. However, that result will include an n-state symbol that is different then if the galois field operation was operated with a standard finite field.
In a further embodiment of the present invention the alternate galois field arithmetic device is applied in error correcting coding and decoding, error detection and encryption and decryption.
In one embodiment of the present invention alternate finite field addition, and/or subtraction and/or multiplication and/or division are applied to process a sequence of n-state symbols with n>2, n>3 and n>7. A sequence herein is a sequence of at least n-state symbols, if needed represented in bits. In one embodiment of the present invention, a sequence includes at least two words of n-state symbols. A processor processes in that case a word as a block. In one embodiment of the present invention a processor processes a sequence of n-state symbols continuously, or in a streaming manner.
In accordance with an aspect of the present invention a device such as a processor, a coder, a decoder, an encryption or decryption device applies functions of different alternate finite fields to process a sequence of n-state symbols. That is: a first n-state symbol or a first block of n-state symbols in a sequence of n-state symbols is processed by functions defined over a first finite field. A second n-state symbol or a second block of n-state symbols in a sequence of n-state symbols is processed by functions defined over a second finite field which with respect to the first finite field is an alternate finite field.
In one embodiment of the present invention an alternate finite field may be created by a reversible inverter as provided earlier, wherein 0 is the zero element, but one or more other elements of the inverter invert a state. One can thus apply different alternate finite fields with zero element 0, which still make correct decoding or decryption very difficult unless the details of the alternate finite field are known.
In one embodiment of the present invention functions (addition, multiplication, division, subtraction) of two or more different alternate finite fields including at least one alternate finite field with a zero element not 0 are applied to process two or more n-state symbols or two or more blocks of n-state symbols. When sufficient unpredictable changes for an uninformed party takes place to switch between a plurality of alternate finite fields, then code breaking or cryptanalysis of the received sequence of n-state symbols processed in the above manner will become highly unlikely.
The 26 letters in for instance the western alphabet including capital letter, space and special characters and digits can be coded by a word of 7 bits. Each 7 bit word forms a 128-state symbol. In general one has an additional bit in the word to form a byte of 8 bits. A word of 8 bits forms a 256-state symbol. In accordance with an aspect of the present invention a sequence of k-state symbols or of blocks of k-state symbols with k<n is processed by a device such as a processor by applying a finite field GF(k) and a second finite field GF(n). In one embodiment of the present invention, both alternate finite fields have a zero element not being 0.
One problem would be that processing of k-state symbols over a field GF(k) will generate k-state symbols while processing of k-state symbols over a field GF(n) will generate n-state symbols giving away information about the applied field. In accordance with an aspect of the present invention the k-state symbols after processing are modified to n-state symbols, for instance via a substitution table or in another way. For instance a 128-state symbols can be processed by a prime field or an alternate of such a field by taking the 7 bit representation of the symbol and add a bit to make an 8-bit symbol. One can then use the decimal value of the 8-bit word with an addition and multiplication over a field GF(p with k<p). For instance GF(137), GF(199), GF(251) could be used to generate the required alternate field. Assume and alternate finite field GFa(137) is applied on the k-state symbol with k=128. This will generate 137 state symbols. One can generate from the 137 state symbols 256 state symbols by using a relevant substitution method. For instance a substitution table or by applying a 256-state LFSR scrambler.
There is a distinction in the art between the concepts of (1) coding, (2) encryption and (3) hashing. Coding may technically apply to error performance and detectability in signal transmission. Encryption is related to security and keeping secrecy of a message. Coding and encryption processes are reversible by a process named respectively decoding and decryption. Hashing in general refers to a (usually non-reversible) transformation process, for instance to indicate a possible change in status. Hashing can be achieved via a finite field. The concepts of (1) coding, (2) encryption and (3) hashing are covered herein by the name “coding” unless it is specifically named differently or it is clear from its context that either coding or encryption specifically is intended. The term decoding is therefor intended to mean both decoding and decryption unless specifically mentioned otherwise.
The following patent applications, including the specifications, claims and drawings, are hereby incorporated by reference herein, as if they were fully set forth herein: (1) U.S. Non-Provisional patent application Ser. No. 10/935,960, filed on Sep. 8, 2004, entitled TERNARY AND MULTI-VALUE DIGITAL SCRAMBLERS, DESCRAMBLERS AND SEQUENCE GENERATORS; (2) U.S. Pat. No. 7,002,490 by Lablans, issued Feb. 21, 2006, entitled TERNARY AND HIGHER MULTI-VALUE SCRAMBLERS/DESCRAMBLERS; (3) U.S. patent application Ser. No. 11/000,218, filed Nov. 30, 2004, entitled SINGLE AND COMPOSITE BINARY AND MULTI-VALUED LOGIC FUNCTIONS FROM GATES AND INVERTERS; (4) U.S. Provisional Patent Application No. 60/599,781, filed Aug. 7, 2004, entitled MULTI-VALUED DIGITAL INFORMATION RETAINING ELEMENTS AND MEMORY DEVICES; and (5) U.S. patent application Ser. No. 11/566,725 filed Dec. 5, 2006, entitled ERROR CORRECTING DECODING FOR CONVOLUTIONAL AND RECURSIVE SYSTEMATIC CONVOLUTIONAL ENCODED SEQUENCES.
Devices and methods disclosed herein in accordance with an aspect of the present invention are applied in data storage systems and storage devices enabled to store, retrieve and output data and are provided as an aspect of the present invention.
Devices and methods disclosed herein in accordance with an aspect of the present invention are provided in data communication systems and devices enabled to either process and output data signals for transmission or to receive, to process and to present the original data signals. Also a communication system is provided in accordance with an aspect of the present invention, including sending and receiving processors applying methods and devices provided herein.
Usually the term Linear Feedback Shift Register is used for the type of scramblers, descramblers and sequence generators as used herein. The term Linear herein may be confusing as it may refer to the sequential organization of shift register elements or the linearity of Boolean binary feedback functions. The term Feedback Shift Register (FSR) is used herein which means a shift register with sequential storage elements with a feedback loop with one or more feedback functions, wherein symbol stored in a downstream position in a shift register is modified in accordance with at least one feedback function or switching function and fed back into an upstream shift register element.
A shift register with feedback, either in Galois or Fibonacci configuration can be applied as a reversible scrambler as for instance illustrated in
In the interest of simplicity, it may seem preferable to perform all operations as described herein over a finite field GF(n), being alternate or not. However, in the case of sequence generation, the 2-input functions defined by the addition over a field and the inverters defined by the multiplication over the field in an n-state FSR will not generate all desirable sequence. For instance, a configuration as shown in
In general, an open connection in a tap is indicated in a finite field by the zero element or in a standard field by [0 0 0 0]. As described herein a zero element may be any inverter [p p p . . . p] with p complying with an n-state switching table. For instance an open connection in a 4-state device can be represented by the inverter [0 0 0 0]. One may also use in effect the inverters [1 1 1 1], [2 2 2 2] and [3 3 3 3] in a tap. As described in U.S. application Ser. No. 13/831,394, which is incorporated herein by reference, a sequence generator can be constructed from a plurality of inverters of which the ones are selected that, when applied in a configuration as in
While there have been shown, described and pointed out fundamental novel features of the invention as applied to preferred embodiments thereof, it will be understood that various omissions and substitutions and changes in the form and details of the device illustrated and in its operation may be made by those skilled in the art without departing from the spirit of the invention. It is the intention, therefore, to be limited only as indicated by the scope of the claims appended hereto.
This application is a continuation-in-part of U.S. patent application Ser. No. 14/622,860 filed on Feb. 14, 2015, which is a continuation of U.S. patent application Ser. No. 14/064,089 filed on Oct. 25, 2013, which is a continuation-in-part of U.S. patent application Ser. No. 12/952,482 filed on Nov. 23, 2010, now abandoned, which is a continuation-in-part of U.S. patent application Ser. No. 11/555,730 filed on Nov. 2, 2006, now abandoned, which are all incorporated herein by reference. U.S. patent application Ser. No. 12/952,482 is also a continuation-in-part of U.S. patent application Ser. No. 11/618,986 filed on Jan. 2, 2007, now abandoned, which is a continuation-in-part of U.S. patent application Ser. No. 10/935,960 filed on Sep. 8, 2004, now U.S. Pat. No. 7,643,632, which claims the benefit of U.S. Prov. Patent Appl. Ser. No. 60/547,683 filed on Feb. 25, 2004. U.S. patent application Ser. No. 12/952,482, now abandoned, is also a continuation-in-part of U.S. patent application Ser. No. 11/679,316 filed on Feb. 27, 2007, now U.S. Pat. No. 7,865,806, which claims the benefit of U.S. Prov. Appl. No. 60/779,068, filed Mar. 3, 2006. U.S. patent application Ser. No. 12/952,482, now abandoned, is also a continuation-in-part of U.S. patent application Ser. No. 11/566,725 filed on Dec. 5, 2006, now U.S. Pat. No. 7,877,670, which claims the benefit of U.S. Prov. Patent Appl. Ser. No. 60/742,831, filed Dec. 6, 2005. U.S. patent application Ser. No. 12/952,482, now abandoned, is also a continuation-in-part of U.S. patent application Ser. No. 11/680,719 filed on Mar. 1, 2007, now U.S. Pat. No. 7,865,807, which claims the benefit of U.S. Prov. Appl. No. 60/779,068, filed Mar. 3, 2006. U.S. patent application Ser. No. 12/952,482, now abandoned, is also a continuation-in-part of U.S. patent application Ser. No. 11/534,777 filed on Sep. 25, 2006, now U.S. Pat. No. 7,930,331, which claims the benefit of U.S. Prov. Patent Appl. Ser. No. 60/720,655, filed Sep. 26, 2005. U.S. patent application Ser. No. 12/952,482, now abandoned, is also a continuation-in-part of U.S. patent application Ser. No. 12/400,900 filed on Mar. 10, 2009 which is a continuation-in-part of U.S. patent application Ser. No. 11/680,719 filed on Mar. 1, 2007, now U.S. Pat. No. 7,865,807, which claims the benefit of U.S. Prov. Patent Appl. Ser. No. 60/779,068 filed on Mar. 3, 2006. The application U.S. patent application Ser. No. 12/400,900 filed on Mar. 10, 2009 also claims the benefit of U.S. Prov. Patent Appl. Ser. No. 61/035,563 filed on Mar. 11, 2008. U.S. patent application Ser. No. 12/952,482, now U.S. Pat. No. 7,865,807, is also a continuation-in-part of U.S. patent application Ser. No. 12/642,916 filed on Dec. 21, 2009, now U.S. Pat. No. 7,864,087, which is a continuation and claims the benefit of U.S. patent application Ser. No. 12/188,261, filed on Aug. 8, 2008, now U.S. Pat. No. 7,659,839, which claims the benefit of U.S. Prov. Patent Appl. Ser. No. 60/956,024 filed on Aug. 15, 2007. U.S. patent application Ser. No. 12/952,482, now abandoned, is also a continuation-in-part of U.S. patent application Ser. No. 12/827,465 filed on Jun. 30, 2010, now U.S. Pat. No. 7,924,176, which is a continuation and claims the benefit of U.S. patent application Ser. No. 12/330,255 filed on Dec. 8, 2008, now U.S. Pat. No. 7,772,999, which claims the benefit of U.S. Prov. Patent Appl. Ser. No. 61/012,548 filed on Dec. 10, 2007. U.S. patent application Ser. No. 12/952,482, now abandoned, is also a continuation-in-part of U.S. patent application Ser. No. 12/868,874 filed on Aug. 26, 2010, now U.S. Pat. No. 7,864,079, which is a continuation and claims the benefit of U.S. patent application Ser. No. 12/264,728 filed on Nov. 4, 2008, now abandoned, which is a continuation of U.S. patent application Ser. No. 10/912,954 filed on Aug. 6, 2004 now U.S. Patent Ser. No. 7,505,589 and of U.S. patent application Ser. No. 10/936,181 filed Sep. 8, 2004, now U.S. Pat. No. 7,002,490. Both patent application Ser. Nos. 10/912,954 and 10/936,181 claim the benefit of U.S. Prov. Patent Appl. No. 60/501,335, filed on Sep. 9, 2003. This patent application is also a continuation-in-part of U.S. patent application Ser. No. 12/980,504 filed on Dec. 29, 2010, now U.S. Pat. No. 8,577,026. This patent application is also a continuation-in-part of U.S. patent application Ser. No. 13/103,300 filed on May 9, 2011, now U.S. Pat. No. 8,645,803. This patent application is also a continuation-in-part of U.S. patent application Ser. No. 13/846,296 filed on Mar. 18, 2013. This patent application is also a continuation-in-part of U.S. patent application Ser. No. 13/831,394 filed on Mar. 14, 2013. All of the above U.S. Patent Applications and U.S. Patents are incorporated herein by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| 60733308 | Nov 2005 | US | |
| 60547683 | Feb 2004 | US | |
| 60779068 | Mar 2006 | US | |
| 60742831 | Dec 2005 | US | |
| 60779068 | Mar 2006 | US | |
| 60720655 | Sep 2005 | US | |
| 60779068 | Mar 2006 | US | |
| 61035563 | Mar 2008 | US | |
| 60956024 | Aug 2007 | US | |
| 61012548 | Dec 2007 | US | |
| 61332974 | May 2010 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 14064089 | Oct 2013 | US |
| Child | 14622860 | US | |
| Parent | 12188261 | Aug 2008 | US |
| Child | 12642916 | US | |
| Parent | 12330255 | Dec 2008 | US |
| Child | 12827465 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 14622860 | Feb 2015 | US |
| Child | 14975841 | US | |
| Parent | 12952482 | Nov 2010 | US |
| Child | 14064089 | US | |
| Parent | 11555730 | Nov 2006 | US |
| Child | 12952482 | US | |
| Parent | 11618986 | Jan 2007 | US |
| Child | 12952482 | US | |
| Parent | 10935960 | Sep 2004 | US |
| Child | 11618986 | US | |
| Parent | 11679316 | Feb 2007 | US |
| Child | 12952482 | US | |
| Parent | 11566725 | Dec 2006 | US |
| Child | 12952482 | US | |
| Parent | 11680719 | Mar 2007 | US |
| Child | 12952482 | US | |
| Parent | 11534777 | Sep 2006 | US |
| Child | 12952482 | US | |
| Parent | 12400900 | Mar 2009 | US |
| Child | 12952482 | US | |
| Parent | 11680719 | Mar 2007 | US |
| Child | 12400900 | US | |
| Parent | 12642916 | Dec 2009 | US |
| Child | 12952482 | US | |
| Parent | 12827465 | Jun 2010 | US |
| Child | 12952482 | US | |
| Parent | 12980504 | Dec 2010 | US |
| Child | 14064089 | US | |
| Parent | 13103300 | May 2011 | US |
| Child | 12980504 | US | |
| Parent | 13846296 | Mar 2013 | US |
| Child | 13103300 | US | |
| Parent | 12868874 | Aug 2010 | US |
| Child | 12952482 | US | |
| Parent | 13846296 | Mar 2013 | US |
| Child | 12868874 | US | |
| Parent | 13831394 | Mar 2013 | US |
| Child | 13846296 | US |
