Patent Application
20230188138
This application claims the benefit of and priority to Indian Patent Application Number 202141053004, which was filed on Nov. 18, 2021, and is hereby incorporated by reference in its entirety.
This disclosure relates generally to Controller Area Network (CAN) devices and, more particularly, to methods and apparatus to balance propagation delay and bus emissions in transceivers.
CAN refers to a vehicle standard that connects various Electronic Control Units (ECUs) to one another. Through CAN, vehicle systems controlled by an ECU exchange information over a wiring system known as a CAN bus. This contrasts with older vehicles that do not use a CAN bus, which rely on complex wiring between specific ECUs for vehicle systems to share information. High-speed CAN networks are implemented with two wires and allow communications at transfer rates up to 1 Mbit/s. Flexible Data-Rate CAN networks may allow for higher data rates. Low-speed/fault-tolerant CAN networks are also implemented with two wires, can communicate with devices at rates up to 125 kbit/s, and offer transceivers with fault-tolerant capabilities. Single-wire CAN interfaces can communicate with devices at rates up to 33.3 kbit/s (88.3 kbit/s in high-speed mode). Typical single-wire devices applications include comfort devices such as seat and mirror adjusters.
Over time, updates to the CAN bus standard allow for increased functionality, bandwidth, and robustness.
An example apparatus includes first inverter circuitry to invert the input voltage and produce a first inverted voltage; second inverter circuitry to invert the first inverted voltage and produce a second inverted voltage at a rate based on a first current controlled transistor; third inverter circuitry to invert the second inverted voltage and produce a third inverted voltage at a rate based on a second current controlled transistor; and fourth inverter circuitry to invert the third inverted voltage and produce an output voltage, wherein the output voltage matches the input voltage.
In general, the same reference numbers or other reference designators are used throughout the drawing(s) and accompanying written description to refer to the same or similar (functionally and/or structurally) features. The figures are not to scale.
One example of an updated CAN standard is referred to as Signal Improvement Capability (CAN-SIC). The CAN-SIC standard allows for more complex network topologies at higher communication bit rates than previous CAN standards.
To send information over and receive information from a CAN bus, an ECU includes transceiver circuitry. Transceiver circuitry receives an analog input signal from the CAN bus and converts the analog signal into a digital signal. The transceiver circuitry uses a high supply voltage to represent a ‘1’ bit (e.g., a logic “high”) in the digital input signal, and a low supply voltage to represent a ‘0’ bit (e.g., a logic “low”) in the digital input signal. In transceiver circuitry using the CAN-SIC standard, the high supply voltage may be any value between +1.7 Volts (V) and +5.5 V. Similarly, the low supply voltage in transceiver circuitry using the CAN-SIC standard may be a value at or near 0 V. The exact value of the low supply voltage may be dependent on an amount of noise experienced on the CAN bus. In other examples, the high supply voltage may have different upper bound and lower bound voltages.
The value of the high supply voltage affects bus emissions corresponding to the transceiver circuitry. For example, transceiver circuitry contains logical output buffers to store a number of digital bits before transferring them to processor circuitry. When a memory in the digital buffer changes to store a different bit (e.g., a transition from a ‘1’ bit to a ‘0’ bit or vice versa), the transition causes electromagnetic emissions on the CAN bus, which in turns disrupts the signal integrity of information on the bus. The amount of electromagnetic emissions caused by bit transitions in the logical output buffers is directly proportional to how quickly the bit transition occurs, which in turn is directly proportional to the high supply voltage. As a result, a high supply voltage near +5.5 V will result in faster bit transitions and more emissions on the CAN bus than when the high supply voltage is near +1.7 V.
The value of the high supply voltage also effects a propagation delay corresponding to the transceiver circuitry. Propagation delay refers to the amount of time it takes for an example transceiver circuitry to receive a number of digital bits from processor circuitry, convert the digital bits into an analog signal, send the analog signal over the CAN bus, receive (e.g., by a receiver or another transceiver) the same analog signal, convert the analog signal back into the digital bits, and provide the digital bits to processor circuitry. An example transceiver circuit using the CAN-SIC standard is required to have a propagation delay of 190 nanoseconds (ns). Because the high supply voltage is directly proportional to the rate at which bit transitions in the logical output buffer, a high supply voltage near +1.7 V will result in a larger propagation delay than a high supply voltage near +5.5 V. As a result, transceiver circuitry with a high supply voltage near +1.7 V may be unable to satisfy the propagation delay requirements of the CAN-SIC standard.
A logic output buffer of some examples herein can mitigate emissions on the CAN bus and satisfy the propagation delay requirements of the CAN-SIC standard, regardless of whether high supply voltage is +1.7 V, +5.5 V, or some voltage in between. Example logic output buffer circuitry includes inverter circuitry with transistors that have sufficient power ratings to increase the rate of bit transitions and satisfy the propagation delay requirement when the high supply voltage is near +1.7 V. Example logic output buffer circuitry also includes example current controlled transistors to conditionally increase a load experienced by the inverter circuitry when the high supply voltage is above a threshold voltage (i.e., when the high supply voltage is near +5.5 V), thereby decreasing the rate of bit transitions and mitigating emissions.
The vehicle 100 of
Each of the ECUs 102 of
The CAN bus 104 of
The processor circuitry 202 of
The transceiver circuitry 204 of
The TXD pin 302 of
The driver circuitry 322 of
In the illustrative example of
The driver circuitry 322 produces an analog signal based on information received by the mode select circuitry 324 of
The analog signal produced by the driver circuitry 322 is transmitted to the CAN bus 104 via the CANH pin 314 and CANL pin 312 of
The example Schottky diode 336 of
The example Schottky diode 340 protects the GND pin 304 from high negative voltages on the CAN bus. For example, if the CANL pin 312 experiences a voltage that is less than 0 V, the example Schottky diode 340 may become reverse biased and prevent the high negative voltage and potentially large current experienced on the CANL pin 312 from reaching the GND pin 304. Similarly, if a high voltage is experienced on the CANL pin 312, the transistor 342 may become reversed biased and prevent a large current from flowing to the GND pin 304.
The receiver circuitry 328A - 328B of
The receiver circuitry 328A and 328B may amplify a voltage difference to resolve the signal. For example, when the example transceiver circuitry 204 is not in standby mode and the difference between the voltage difference between the CANH pin 314 and CANL pin 312 is greater than or equal to +0.9 V, the receiver circuitry 328A may set the RXD pin 308 to 0 V to represent a digital ‘0’ bit. Similarly, when not in standby mode, the receiver circuitry 328A may set the RXD pin 308 to the high supply voltage to represent a digital ‘1’ bit when the difference between the voltage difference between the CANH pin 314 and CANL pin 312 is less than or equal to +0.5 V. In such examples, the receiver circuitry 328A may consider a voltage difference between the CANH pin 314 and CANL pin 312 that is greater than +0.5 V and less than +0.9 V as undefined. In other examples when the example transceiver circuitry 204 is in standby mode, the example receiver circuitry 328B may set the RXD pin 308 to a digital ‘1’ bit until a remote wake event occurs.
In the illustrative example of
The MUX circuitry 332 of
The example logic output buffer circuitry 334 of
When the bits provided by the MUX circuitry 332 to the example logic output buffer circuitry 334 change, the resulting bit transitions in the logic output buffer circuitry 334 causes noise within the high supply voltage signal for a period of time. In some examples, the noise may be referred to as a voltage bounce. Because the high supply voltage and low supply voltage used by the logic output buffer circuitry come from the same pins that are also used by the driver circuitry 322 (e.g., the VCC pin 306 and the GND pin 304), this voltage bounce is also transferred to the driver circuitry 322 and sent over the CAN bus 104 as a form of electromagnetic emissions. The example logic output buffer circuitry 334 mitigates the amount of electromagnetic emissions while also meeting the propagation delay requirement for CAN-SIC standards. In some examples, the example logic output buffer circuitry 334 may additionally or alternatively satisfy an electromagnetic emissions threshold corresponding to the CAN bus 104.
The example logic output buffer circuitry 334 is implemented by a sequence of CMOS inverter circuits and is configured so that the DOUT voltage 416 matches the DIN voltage 414. Hence, a change in the DIN voltage 414 corresponds to the same change in the DOUT voltage 416. In doing so, the example logic output buffer circuitry 334 does not lose or distort the data encoded in the DIN voltage 414. In some examples, the DIN voltage 414 may be referred to as an input data signal.
A CMOS inverter circuit is composed of a PMOS transistor and an NMOS transistor connected in parallel. Both drain terminals of the PMOS and NMOS transistor connect to form an output signal, while the source terminal of the PMOS transistor is connected to the VCC pin 306 (shown as Vdd in
The gate of the PMOS transistor MP0 408A receives a first branch signal, while the gate of the NMOS transistor MN0 408B receives a separate second branch signal. By separating the input to the fourth CMOS circuitry 408, the logic output buffer circuitry 334 prevents a short circuit occurring between the VCC pin 306, RXD pin 308, and GND pin 304 when a bit transition occurs. In some examples, the use of two separate inputs instead of a single input from a common node may be referred to as a “break before make” architecture. After the first CMOS inverter circuitry 402 receives the DIN voltage 414 from the MUX circuitry 332 and produces the first inverted voltage, the logic output buffer circuitry 334 splits the first inverted voltage into a first branch and a second branch at the first inverted node 436. In some examples, the first inverted voltage may be referred to as a first inverted data signal. In the first branch, data travels through the second CMOS inverter circuitry 404, GATE_MP1 438, the third CMOS inverter circuitry 406, GATE_MP0 440, and MP0 408A in the fourth CMOS inverter circuitry 408. In the second branch, the same data travels through the fifth CMOS inverter circuitry 410 to the sixth CMOS inverter circuitry 412 to the gate terminal of MN0 408B in the fourth CMOS inverter circuitry 408.
To ensure that the transceiver circuitry 204 meets the propagation delay requirement for CAN-SIC devices, the PMOS and NMOS transistors of the example logic output buffer circuitry 334 may be implemented with sufficient drive strength to support the propagation delay requirement even when bit transitions are slow (e.g., when the high supply voltage is at or near +1.7 V). As used herein, drive strength refers to a relationship between the output voltage and output current of a CMOS transistor. The size of transistors in the example logic output buffer circuitry 334 may be larger than previous implementations of logic output buffer circuitry 334 that did not use the CAN-SIC standard. These larger transistors may exhibit a higher drive strength by supplying a desired output current faster than previous implementations. In some examples, the example logic output buffer circuitry 334 experienced 25 ns of the 190 ns propagation delay requirement, which satisfies the 34 ns target delay for logic output buffers in CAN-SIC devices. In such previous implementations, replacing the existing transistors with higher drive strength equivalents may result in the previous implementation meeting the propagation delay for CAN-SIC. However, the replaced transistors would also cause increased electromagnetic emissions when the high supply voltage is near or at +5.5 V.
To meet the propagation delay for CAN-SIC and minimize electromagnetic emissions on the CAN bus 104, the example logic output buffer circuitry 334 of
The supply divider circuitry 418 of
The first divider voltage is provided to the gate terminal of MN4 420. As a result, MN4 420 may be considered an implementation of a current controlled transistor, as current can only pass from the source terminal to the drain terminal when the first divider voltage meets a MN4 threshold voltage. The first divider voltage may meet the MN4 threshold voltage if the first divider voltage is greater or equal to the MN4 threshold voltage.
The MN4 threshold voltage may be a pre-determined value based on the power rating of MN4 420. In some examples, the MN4 threshold voltage may be approximately +0.7 V. In examples where the high supply voltage is at or near +5.5 V, the first divider voltage may be greater than the MN4 threshold voltage. Conversely, in examples where the high supply voltage is at or near +1.7 V, the first divider voltage may be less than the MN4 threshold voltage. Furthermore, in examples where the first divider voltage is greater than the MN4 threshold voltage, the amount of current that passes through MN4 420 is proportional to the magnitude of the voltage difference between the first divider voltage and the MN4 threshold voltage. This affects the rate at which the second inverted node (i.e., GATE_MP1 438) changes voltage, as the rate is dependent on the total amount of current that is provided to MP1 406A. In some examples, the voltage at GATE_MP1 438 may be referred to as a second inverted data signal.
For example, suppose that the high supply voltage is at or near +5.5 V, and that DIN voltage 414 includes a bit transition from a ‘0’ bit to a ‘1’ bit. As a result, the voltage at the first inverted node 436 transitions from a ‘1’ bit to a ‘0’ bit and GATE_MP1 438 transitions from a ‘0’ bit to a ‘1’ bit during the bit transition. In previous implementations of logic output buffer circuitry, current would travel from Vdd, through MP2 404A, and only a first amount of current would travel through MN2 404B as the remaining current would travel to the third CMOS inverter circuitry 406 and affect the speed at which GATE_MP1 438 transitions from 0 V to the high supply voltage. When the same example is implemented in the example logic output buffer circuitry 334 of
The second divider voltage is provided to the gate terminal of MP4 422. As a result, MP4 422 may also be considered an implementation of a current controlled transistor, as current can only pass from the source terminal to the drain terminal when the difference between the high supply voltage and the second divider voltage meets a MP4 threshold voltage (e.g., Vdd - SUPDIV
The MP4 threshold voltage may be a pre-determined value based on the power rating of MP4 422. In some examples, the MN4 threshold voltage may be approximately +0.7 V. In examples where the high supply voltage is at or near +5.5 V, both Vdd and the second divider voltage may be sufficiently high such that Vdd -SUP_DIV_P ≥ VThMP4 . Conversely, in examples where the high supply voltage is at or near +1.7 V, both Vdd and the second divider voltage may be sufficiently low such that Vdd - SUPDIV
In the foregoing example where the high supply voltage is at or near +5.5 V and DIN voltage 414 includes a bit transition from a ‘0’ bit to a ‘1’ bit, the rate at which GATE_MP1 438 transitions from a ‘0’ bit to ‘1’ bit was slower than previous implementations of logic output buffer circuitry due to MN4 420. In the same example, the voltage at GATE_MP0 440 changes from a ‘1’ bit to a ‘0’ bit during the bit transition. Without the presence of additional circuitry to conditionally slow bit transitions, the transition of GATE_MP1 438 from ‘0’ bit to ‘1’ bit would cause current to travel from Vdd through MP1 406A and only through MN1 406B before reaching the GND pin 304 and causing the voltage at GATE_MP0 440 to fall to a ‘0’ bit. In the example logic output buffer circuitry 334 of
The addition of current controlled transistors MN4 420 and MP4 422 helps reduce the total amount of current provided to MP0 408A and slows bit transitions when the high supply voltage is at or near +5.5 V. While this current draw is advantageous during bit transitions to reduce bounce on the VCC pin 306 and mitigate electromagnetic emissions on the CAN bus 104, current would not be fully utilized if MN4 420 and MP4 422 stayed enabled when a bit transition is not occurring. Furthermore, if the current controlled transistors were permanently enabled, then the voltages for GATE_MP0 440 and GATE_MP1 438 would be unable to fully transition to the required voltage (e.g., the voltage required to represent a ‘0’ bit or a ‘1’ bit) during a bit transition because some of the current required to make the full transition would be travelling through the current controlled transistor.
To prevent unused current when a bit transition is not occurring and to allow GATE_MP1 438 and GATE_MP0 440 to fully transition to the required voltage during a bit transition, the example logic output buffer circuitry 334 implements MN5 424 and MP5 426 as switch circuitry to conditionally disable MN4 420 and MP4 422 once the voltage at the relevant gate nears its desired voltage. In the foregoing example, where the high supply voltage is at or near +5.5 V, the DIN voltage 414 transitions from a ‘0’ bit to a ‘1’ bit, the voltage at GATE_MP1 438 transitions from a ‘0’ bit to a ‘1’ bit, the voltage at GATE_MP0 440 transitions from a ‘1’ bit to a ‘0’ bit, and both MN5 424 and MP5 426 begin the bit transition enabled. This allows MN4 420 and MP4 422 to function as current controlled transistors and slow the bit transition rate as described previously. As the bit transition concludes, the voltage at GATE_MP0 440 meets a trigger threshold voltage. The voltage at GATE_MP0 440 may meet the trigger voltage if the voltage at GATE_MP0 is less than or equal to the trigger threshold voltage.
In some examples, the trigger threshold voltage is a pre-determined value that is near 0 V but not equal to 0 V. Once the GATE_MP0 440 voltage is below the trigger threshold voltage, it causes the Schmitt trigger circuitry 432 to produce a digital ‘0’. This low supply voltage is provided to the gate terminal of MN5 424, which disables the transistor and prevents current from travelling from GATE_MP1 438 through MN4 420 and to the GND pin 304. This allows the voltage at GATE_MP1 438, which is near but not at the high supply voltage when MN5 424 is disabled, to fully transition to the high supply voltage without any current leakage.
Similarly, in the foregoing example, the high supply voltage provided by the Schmitt trigger circuitry 432 is inverted by the seventh CMOS inverter circuitry 434, which results in the high supply voltage being provided to the gate terminal of MP5 426. This high supply voltage disables MP5 426 and prevents additional current from travelling through MP4 422. As a result, the voltage at GATE_MP0 440 is allowed to fully transition to the low supply voltage without current leakage. Finally, R0 428 and C0 430 act as a filter to prevent any noise in the voltage at GATE_MP0 440 from erroneously activating the Schmitt trigger circuitry 432 before the voltage at GATE_MP0 440 falls below the trigger threshold voltage.
The example logic output buffer circuitry 334 of
The example logic output buffer circuitry 334 of
The processor platform 500 of the illustrated example includes processor circuitry 512. The processor circuitry 512 of the illustrated example is hardware. For example, the processor circuitry 512 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and/or microcontrollers from any desired family or manufacturer. The processor circuitry 512 may be implemented by one or more semiconductor based (e.g., silicon based) devices.
The processor circuitry 512 of the illustrated example includes a local memory 513 (e.g., a cache, registers, etc.). The processor circuitry 512 of the illustrated example is in communication with a main memory including a volatile memory 514 and a non-volatile memory 516 by a bus 518. The volatile memory 514 may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and/or any other type of RAM device. The non-volatile memory 516 may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory 514 and/or 516 of the illustrated example is controlled by a memory controller.
The processor platform 500 of the illustrated example also includes interface circuitry 520. The interface circuitry 520 may be implemented by hardware in accordance with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a near field communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and/or a Peripheral Component Interconnect Express (PCIe) interface.
In the illustrated example, one or more input devices 522 are connected to the interface circuitry 520. The input device(s) 522 permit(s) a user to enter data and/or commands into the processor circuitry 512. The input device(s) 522 can be implemented by, for example, an audio sensor, a temperature sensor, a microphone, a camera (still or video), a sensor system to capture other vehicle information, a keyboard, a button, a mouse, a touchscreen, a track-pad, a trackball, and/or a voice recognition system.
One or more output devices 524 are also connected to the interface circuitry 520 of the illustrated example. The output device(s) 524 can be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touchscreen, etc.), a vehicle system, and/or a speaker. The interface circuitry 520 of the illustrated example, thus, typically includes a graphics driver card, a graphics driver chip, and/or graphics processor circuitry such as a GPU.
The interface circuitry 520 of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and/or a network interface to facilitate exchange of data with external machines (e.g., computing devices of any kind) by a network 526. The communication can be by, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-site wireless system, a cellular telephone system, an optical connection, etc.
The processor platform 500 of the illustrated example also includes one or more mass storage devices 528 to store software and/or data. Examples of such mass storage devices 528 include magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, redundant array of independent disks (RAID) systems, solid state storage devices such as flash memory devices and/or SSDs, and DVD drives.
The machine executable instructions 532 may be stored in the mass storage device 528, in the volatile memory 514, in the non-volatile memory 516, and/or on a removable non-transitory computer readable storage medium such as a CD or DVD.
The logic output buffer circuitry 600 of
From the foregoing, it will be appreciated that example systems, methods, apparatus, and articles of manufacture have been disclosed that meet the propagation delay requirement for CAN-SIC transceivers and mitigate CAN bus emission regardless of the high supply voltage value. Disclosed systems, methods, apparatus, and articles of manufacture improve the efficiency of using a computing device by conditionally slowing the bit transition of logic output buffer circuitry when the high supply voltage is at or near +5.5 V. Disclosed systems, methods, apparatus, and articles of manufacture are accordingly directed to one or more improvement(s) in the operation of a machine such as a computer or other electronic and/or mechanical device.
Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly that might, for example, otherwise share a same name.
As used herein “substantially real time” refers to occurrence in a near instantaneous manner recognizing there may be real world delays for computing time, transmission, etc. Thus, unless otherwise specified, “substantially real time” refers to real time +/- 1 second.
As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.
As used herein, “processor circuitry” is defined to include (i) one or more special purpose electrical circuits structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and/or (ii) one or more general purpose semiconductor-based electrical circuits programmed with instructions to perform specific operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of processor circuitry include programmed microprocessors, Field Programmable Gate Arrays (FPGAs) that may instantiate instructions, Central Processor Units (CPUs), Graphics Processor Units (GPUs), Digital Signal Processors (DSPs), XPUs, or microcontrollers and integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of processor circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more DSPs, etc., and/or a combination thereof) and application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of the processing circuitry is/are best suited to execute the computing task(s).
The term “couple” is used throughout the specification. The term may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, in a first example device A is coupled to device B, or in a second example device A is coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal provided by device A.
In this description, the term “and/or” (when used in a form such as A, B and/or C) refers to any combination or subset of A, B, C, such as: (a) A alone; (b) B alone; (c) C alone; (d) A with B; (e) A with C; (f) B with C; and (g) A with B and with C. Also, as used herein, the phrase “at least one of A or B” (or “at least one of A and B”) refers to implementations including any of: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.
A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or re-configurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.
As used herein, the terms “terminal”, “node”, “interconnection”, “pin” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component.
While the use of particular transistors are described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, a metal-oxide-silicon FET (“MOSFET”) (such as an n-channel MOSFET, nMOSFET, or a p-channel MOSFET, pMOSFET), a bipolar junction transistor (BJT - e.g. NPN or PNP), insulated gate bipolar transistors (IGBTs), and/or j unction field effect transistor (JFET) may be used in place of or in conjunction with the devices disclosed herein. The transistors may be depletion mode devices, drain-extended devices, enhancement mode devices, natural transistors or other type of device structure transistors. Furthermore, the devices may be implemented in/over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).
While certain elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term “integrated circuit” means one or more circuits that are: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board.
Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means +/- 10 percent of the stated value, or, if the value is zero, a reasonable range of values around zero. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.
The following claims are hereby incorporated into this Detailed Description by this reference. Although certain example systems, methods, apparatus, and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, methods, apparatus, and articles of manufacture fairly falling within the scope of the claims of this patent.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202141053004 | Nov 2021 | IN | national |
