Patent Grant
11693633
This disclosure relates generally to programmable computing devices and more particularly, to methods and apparatus to detect and annotate backedges in a dataflow graph.
A processor, or set of processors, execute(s) instructions from an instruction set (e.g., an instruction set architecture (ISA)). The instruction set is the part of the computer architecture related to programming, and generally includes native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O) information. Instructions may be macro-instructions provided to a processor for execution, and/or may be micro-instructions generated by a processor based on decoding macro-instructions.
The figures are not to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts.
Descriptors “first,” “second,” “third,” etc. are used herein when identifying multiple elements or components which may be referred to separately. Unless otherwise specified or understood based on their context of use, such descriptors are not intended to impute any meaning of priority, physical order or arrangement in a list, or ordering in time but are merely used as labels for referring to multiple elements or components separately for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for ease of referencing multiple elements or components.
Examples disclosed herein latency-balance a dataflow graph (e.g., cyclic dataflow graphs and/or acyclic dataflow graphs) by injecting buffers into the dataflow graph. As used herein, a dataflow graph (DFG) is a graphical representation of a computer program. A cyclic DFG is a general dataflow graph that contains cycles or loops to represent looping or iterative operations in a computer program. An acyclic DFG is a general dataflow graph that does not contain cycles or loops. DFGs may be produced by a compiler, a software framework, or written by hand. Examples disclosed herein are described in connection with DFGs generated for an example type of computer architecture known as a coarse-grained reconfigurable architecture (CGRA). CGRA-based devices include thousands of tiny reconfigurable processing elements (PEs) arranged or formed on a spatial grid and connected via on-chip reconfigurable network connections. A particular example of a CGRA is a configurable spatial accelerator (CSA) architecture developed by Intel Corporation of Santa Clara, Calif., USA. Examples disclosed herein may be used to process dataflow graphs targeted for execution on a CSA architecture, targeted for execution any other type of CGRA, and/or targeted for execution on any other type of machine architecture.
A CSA target device can be programmed by writing CSA-specific assembly instructions (e.g., using an instruction set architecture (ISA)). Examples disclosed herein may be implemented in connection with a compiler for CSA target devices that can be used to compile high-level languages such as the C programming language, the C++ programming language, the FORTRAN programming language, etc. into CSA-specific LLVM IR (Intermediate Representation) language. The term LLVM is not an acronym but is a term in itself that refers to a manner of representing code for use in compiler-based analysis and optimization. LLVM code representations are defined by the LLVM Foundation. However, examples disclosed herein may be implemented in connection with a general LLVM IR or any other suitable type of compiler IR for any other type of machine or architecture in addition to or instead of a machine-specific LLVM IR such as CSA-specific LLVM IR. The compiler can optimize and compile compiler IR code or LLVM IR code into a CSA assembly which is then used to create a DFG. During such transformation, the compiler can propagate or hold high-level program-specific information as well as programmer-specified hints to the assembly level such as loop membership, performance critical operations, throughput, etc. which can be used by subsequent tools for preparing the program for loading on a target device. For example, such subsequent tools can use the dataflow representation of the DFG to optimize the DFG by fusing suitable operations together, balancing available buffering with latency in accordance with teachings of this disclosure, mapping operations to target hardware, and placing and routing operations and storage in the target hardware. A high-level workflow representation of a compiler for CSA devices and/or any other type of CGRA devices is shown in Table 1 below.
While Table 1 above shows an example manner of organizing a compiler workflow, the example stages depicted in Table 1 can be reordered, one or more of the stages can be run multiple times in any sequence, one or more of the stages can be omitted, and/or one or more other stages can be inserted. Example latency-balancing techniques disclosed herein may be implemented in the Buffer Insertion phase of a compiler shown in Table 1 above by analyzing DFGs generated by the Operation Elaboration and Fusion phase. A DFG is formed using interconnected nodes in which each node represents an operation (e.g., a compute operation, a memory operation, a control operation, etc.) and each interconnection or arc represents a producer-consumer dataflow relationship (e.g., an input-output dependency) between two operations. For example, for two interconnected nodes forming an input-output dependency, a first node is a producer/source node and a second node is a consumer/destination/sink node. The producer/source node is the dominator node that performs a producer/source operation to produce an output that is consumed as input in the consumer/destination/sink node to perform a consumer/destination/sink operation.
A DFG defines nodes of operations and their interconnections and is used to configure PEs of CGRA devices. Different PEs of a CGRA device may be structured for different types of operations. For example, some PEs may be structured to perform integer arithmetic operations, some PEs may be structured to perform floating point arithmetic operations, some PEs may be structured to perform communication operations, and some PEs may be structured as in-fabric storage to store data. In the above example, multiple nodes of a DFG may be configured in a single PE or may be configured in different PEs depending on the types of operations of the multiple nodes. In examples disclosed herein, in-fabric storage PEs, also referred to as storage boxes, are memory (e.g., random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), etc.) used to implement buffers for use in latency-balancing DFGs. Additionally or alternatively, storage boxes can be used for other functionalities such as addressable memory. A buffer may be of any size so long as it does not exceed the capacity of the storage box from which it is allocated. The number of buffers available in a CGRA device is based on the number of storage boxes in the CGRA device because the buffers are allocated from the storage boxes.
In examples disclosed herein, a DFG includes one or more cycles or loops between start nodes and corresponding end nodes. For a corresponding set of start and end nodes there may be multiple paths between the two. Each path has a corresponding latency which is the duration of performing their respective operations between the start node and the end node. In those multiple paths is a critical path that is attributable to the longest latency between the start and end nodes relative to latencies of the other path(s) between the start and end nodes. The long latency of the critical path is due to the critical path having more operation nodes and/or longer-latency nodes than the other paths. Latency-balancing by buffering means adding storage elements (e.g., buffers) and/or processing elements on interconnecting arcs between nodes along a path between start and end nodes to make the overall storage in that path produce a path latency tolerance that is similar or equal to a latency of the critical path (e.g., a critical path latency). Contrary to conventional design principals of reducing latency in programs to increase performance, latency-balancing techniques disclosed herein add latency to paths to increase performance. As described in greater detail below, increasing a latency of one or more noncritical paths to be similar or equal to the critical path latency balances the latency between the noncritical and critical paths which increases the data processing throughput of the noncritical and critical paths.
Example latency-balancing techniques disclosed herein include two phases, namely an example backedge detection phase and an example buffer insertion phase. As used herein, a backedge in a DFG is an interconnecting arc between a child node or operation and a parent node or operation. A backedge transfers execution control from the child node to the parent node and denotes a cyclic dependency among operations in the DFG between the child and parent nodes. That is, operations or nodes form a cyclic dependency when execution of a node (e.g., an ancestor node or parent node) is dependent on output(s) from one or more successor nodes (e.g., one or more child nodes or descendent nodes). In examples disclosed herein, detection and removal of backedges is performed before buffer insertion. As such, the example backedge detection phase involves: (a) analyzing a DFG to detect backedges that form loops in a program between loop start nodes and loop end nodes, and (b) annotating the backedges in the DFG. The example buffer insertion phase involves removing the annotated backedges and analyzing the remaining paths in the DFG to determine suitable quantities of buffers to insert in noncritical paths between loop start and loop end nodes to increase data throughputs of those noncritical and critical paths between loop start and loop end nodes.
In the illustrated example of
In the example of
In the example of
Turning to the example backedge detector 102, to improve performance of the input DFG 126 which is targeted to be executed by the CGRA device 142, the backedge detector 102 analyzes the input DFG 126 to detect backedges. The example backedge detector 102 may perform such analyses using a depth-first search (DFS) technique, a breadth-first search (BFS) technique, a technique that combines Johnson's algorithm with DFS, a post-order traversal and dominator analysis technique, a manual backedge annotation technique, or any other suitable technique. Example backedge analysis techniques are described in greater detail below in connection with
In some backedge detection examples, the backedge detector 102 analyzes characteristics of the nodes o1-o6 and compares such characteristics to reference criteria to determine which nodes are connected to backedges. The example backedge detector 102 is provided with the characteristic detector 106 to store node characteristic identifiers in the memory 124 in association with nodes of the input DFG 126. For example, the characteristic detector 106 can store a node characteristic identifier in the memory 124 in association with the second node o2 of the input DFG 126. As defined herein, a node characteristic identifier represents information about an execution status of a node or a hierarchical location of a node relative to other nodes in a DFG. Example node characteristic identifiers are described below in connection with
The example backedge detector 102 is provided with the example characteristic comparator 108 to compare node characteristic identifiers with reference criteria. As defined herein, a reference criterion represents a value to which a node characteristic identifier is compared to determine whether a node corresponding to the node characteristic identifier is connected to a backedge. Example reference criteria are described below in connection with
After the backedge identifier generator 110 annotates the backedges of the input DFG 126, the example buffer inserter 104 accesses the backedge identifiers stored in the memory 124 to perform a buffer insertion process by removing backedges from the input DFG 126 and inserting buffers to generate the output DFG 132. The example buffer inserter 104 includes the example backedge filter 112 to remove backedges between nodes to generate an acyclic DFG as represented by the intermediate DFG 130. For example, the backedge filter 112 accesses a backedge identifier from the memory 124 identifying the connection arc between the second node o2 and the fifth node o5 as being a backedge 128. Based on the backedge identifier, the backedge filter 112 removes the backedge 128 between the second node o2 and the fifth node o5 of the input DFG 126. Thus, although the example input DFG 126 is cyclic because it includes a cycle formed by the backedge 128, example latency-balancing techniques disclosed herein detect and remove backedges such as the backedge 128 to remove cycles which creates acyclic DFGs (e.g., the intermediate DFG 130) before inserting buffers. In addition, although the example backedge 128 is removed from a critical path of the DFG 126, implementations of examples disclosed herein may annotate and/or remove backedges from critical paths and/or noncritical paths to perform buffer insertion. That is, examples disclosed herein may be used to make a DFG acyclic by annotating and removing all backedges regardless of whether those backedges occur on critical paths and/or noncritical paths of the DFG.
The buffer inserter 104 is provided with the example latency calculator 114 to determine critical path latencies of critical paths of DFGs. For example, the latency calculator 114 can determine a critical path latency of the critical path of the intermediate DFG 130 formed by the nodes o1-o5. The example latency calculator 114 also determines the noncritical path latency of the noncritical path formed by the nodes o1, o6, o5. In the example of
The buffer inserter 104 is provided with the example latency comparator 116 to compare the critical path latency to a latency sum of a buffer latency and the noncritical path latency. In examples disclosed herein, a buffer latency is an amount of latency introduced into a path of a DFG for each inserted buffer (e.g., one of the buffers 136, 138 of
The buffer inserter 104 is provided with the example buffer allocator 118 to insert one or more buffers in noncritical paths of DFGs based on buffer insertion analyses of acyclic, intermediate DFGs (e.g., the intermediate DFG 130). For example, the buffer allocator 118 inserts the buffer 136 in the noncritical path (e.g., nodes o1, o6, o5) of the input DFG 126 when the comparator determines that the latency sum (e.g., the sum of the buffer latency and the noncritical path latency) is less than the critical path latency of the critical path of the intermediate DFG 130. In examples disclosed herein, a capacity sum of a path or edge is at least as large as its latency sum because the capacity should be large enough to tolerate the latency (or buffers) in that path. As such, when the capacity sum of the noncritical path is less than the latency of the critical path, examples disclosed herein can add more capacity to the noncritical path so that the capacity of the noncritical path is proportional to the latency of the critical path. In such examples, the proportion is equal to the desired throughput of the part of the DFG under analysis. For examples in which a maximum throughput of one (e.g., one data token per cycle) is desired, the capacity sum of the noncritical path is made equal to the latency of the critical path. After inserting the buffer 136, the latency calculator updates the noncritical path latency to be based on the critical path being formed by nodes o1, o6, o5 and the inserted buffer 136. Subsequently, the buffer inserter 104 can use the latency comparator 116 to determine whether to insert another buffer. For example, the latency comparator 115 can compare the critical path latency of the critical path (nodes o1-o5) to a latency sum of a buffer latency and the updated noncritical path latency. If the example latency comparator 116 determines that the latency sum does not exceed the critical path latency, the buffer allocator 118 inserts another buffer 138 in the noncritical path of the input DFG 126. In this manner, the buffer inserter 104 can use the latency calculator 114 and the latency comparator 116 to determine when inserting another buffer into the noncritical path would exceed the critical path latency of the intermediate DFG 130. When the example latency comparator 116 determines that the critical path latency would be exceeded by inserting another buffer in the noncritical path, the buffer inserter 104 determines that no further buffer should be inserted into the noncritical path of the input DFG 126. Alternatively as described above, in some examples, the latency of a noncritical path is intentionally made to exceed a latency of a critical path through inserting one or more buffers in the noncritical path. In such examples, the previous noncritical path becomes the current critical path, and the previous critical path becomes a noncritical path. This may be done to facilitate latency-balancing a DFG to achieve a desired target data throughput, or due to buffer box storage granularity and latency constraints. In the example of
In some examples, the buffer allocator 118 determines that another buffer resource is not available in the target CGRA device 142 to insert a further buffer in the input DFG 126. When this happens, and the input DFG 126 is not yet latency-balanced, the buffer inserter 104 can instead insert a delay operation in the input DFG 126 to generate additional latency in the noncritical path. To accomplish such additional latency generation in the noncritical path, the buffer inserter 104 is provided with the example delay generator 120. For example, the delay generator 120 inserts a delay operation in the noncritical path when the buffer allocator 118 determines that another buffer is not available for insertion in the noncritical path to increase a similarity between the critical path latency and the noncritical path latency.
Additionally or alternatively, if the buffer allocator 118 determines that sufficient buffer resources are not available in the target CGRA device 142 to insert a sufficient number of buffer(s) in the input DFG 126 to latency-balance the DFG 126, a slackening process may be used to relax the buffer requirements for latency-balancing. Under such a slackening approach, the example buffer inserter 104 introduces a SLACK parameter into the buffer insertion analysis of the intermediate DFG 130 to decrease a target data throughput of the DFG 126 to be less than one (e.g., less than one data token per logical clock cycle). In such examples, the SLACK parameter is a multiplier of the throughput equation according to Little's Law as described below in connection with Constraint 3. By varying the SLACK parameter to reduce the target data throughput of a DFG, slackening can be used to reduce the number of buffers needed to sufficiently latency-balance the DFG such that the DFG satisfies the target data throughput. Such a slackening approach is useful when implementing examples disclosed herein in connection with CGRA devices having insufficient storage box resources to achieve a higher target data throughput. Example slackening techniques may be implemented in accordance with Constraint 3 described in greater detail below in which a SLACK constraint is multiplied by a throughput parameter of an edge (throughputi,j) to decrease the target data throughput of that edge. In some examples, slackening is implemented on a per-edge basis as each edge is analyzed for buffer insertion. In other examples, slackening is implemented on all edges of a DFG, and buffer insertion is performed after such all-edge slackening. In some examples in which buffer resources are depleted during a buffer insertion process of a DFG, any buffers inserted to that point are removed from the DFG so that the slackening process can be performed again on all edges of the DFG. The buffer insertion process is then restarted based on the original DFG (e.g., in the original state of the DFG before the previous buffer insertion process inserted any buffer(s)). Such slackening and restarting of the buffer insertion process may be repeated any number of times until the DFG is latency-balanced in accordance with a target data throughput for which sufficient buffers are available.
In the example of
Each node o1-o6 of the example DFG 126 includes one input buffer per input connection arc to hold an input data token form a preceding node. As such, since the DFG 126 of
Referring to the example of
The above examples of
A CGRA device can be synchronous or asynchronous. A synchronous CGRA device has a global clock and data moves at each logical clock cycle. Although prior techniques provide buffer insertion solutions for synchronous dataflow architectures, examples disclosed herein are useful for inserting buffers in DFGs that run on asynchronous CGRA devices. An asynchronous CGRA device often has no global clock, and the interconnecting arcs and PEs can have variable data rates which makes it more difficult to solve the buffer insertion problem. Examples disclosed herein may be employed to insert buffers in DFGs written for asynchronous CGRA devices by employing an algorithmic computational procedure to optimally insert buffers on edges (e.g., noncritical paths) in a general DFG. In addition, examples disclosed herein can be implemented in connection with asynchronous CGRA architectures and/or synchronous CGRA architectures.
Prior techniques for inserting buffers are directed to buffer insertion on directed acyclic graphs (DAGs) implemented for synchronous systems. However, most computer programs contain cycles. For example, a computer program contains cycles when it includes a “while loop” or nested loops with inner loop dependencies. Such types of loops are often present in computer programs. To perform a buffer insertion process, examples disclosed herein first perform a backedge detection and annotation process to detect backedges in input DFGs (e.g., the input DFG 126) and annotate the backedges in the DFGs. In this manner, the subsequent buffer insertion process can remove the annotated backedges from the DFGs to latency-balance the DFGs by inserting a suitable number of buffers in one or more noncritical paths.
Examples disclosed herein perform backedge detection by analyzing DFGs for dominant nodes and return paths to those dominant nodes. A node ‘x’ in a flow graph dominates node Cy′ if every path from the source node to Cy′ goes through node ‘x’. As such, every node dominates itself and the source node dominates every other node in the DFG. For example, the test condition of a while loop dominates all blocks in the body of the while loop. Similarly, the test of an if-then-else statement dominates all blocks in either branch. During analysis time, the example backedge detector 102 of the compiler 100 (
Still referring to
Examples disclosed herein leverage topology awareness capabilities of the compiler 100 to perform backedge detection and annotation. For example, the compiler 100 has complete topology information of an input program as well as the corresponding dataflow IR because the compiler 100 generates the LLVM IR from the high-level language description of the source code 402. The compiler 100 generates information describing which code belongs to a loop and what interconnect arc represents the backedge in the loop that feeds back a new value for each loop invariant. By leveraging the graph topology information of the compiler 100, as well as loop membership information, examples disclosed herein use such information to enhance capabilities of the compiler 100 to annotate backedges in the generated dataflow code. This provides effective and efficient backedge annotation and buffer insertion solutions in the compiler 100.
By detecting and annotating backedges in cyclic DFGs, examples disclosed herein enable buffer insertion to work on input DFGs that are cyclic and asynchronous. That is, by detecting and annotating backedges in DFGs in accordance with examples disclosed herein, the example compiler 100 (
At an example stage_0 504 of
Examples disclosed herein may be implemented in stage_3 510 of the workflow 500. For example, at stage_3 510, the backedge detector 102 analyzes the input DFG 126 by traversing the DFG 126 to find cycles and identify backedges in those cycles. Example techniques for analyzing the input DFG 126 for detecting and annotating backedges are described below in connection with
Examples disclosed herein may be implemented in connection with other processes that confirm all backedges of a DFG are buffered properly by users or a compiler or a smart code generator. In this manner, cycles in the DFG do not cause deadlock during execution. For purposes of examples disclosed herein, it is assumed that such proper buffering of backedges is confirmed through suitable techniques.
After marking nodes of the DFG 600 with corresponding first node characteristic identifiers during a first logical clock cycle, the backedge detector 102 performs a similar analysis on the nodes to identify their execution statuses as second node characteristic identifiers during a second logical clock cycle. Also at the second logical clock cycle, the example characteristic comparator 108 (
When the backedge detector 102 is configured to use DFS to detect backedges, the DFS analysis should start from a true source node. If the DFS is not run from a true source node, the DFS analysis may choose a backedge that is not the best backedge to remove from a dataflow program's perspective. For example, referring to the DFG 600 of
In some examples, the DFS technique may be combined with Johnson's algorithm, which is a method of finding the shortest paths between pairs of vertices (e.g., nodes) in a sparse, edge-weighted, directed graph (e.g., a DFG). Johnson's algorithm is named after Donald B. Johnson, who published the technique in a journal article titled, “Finding All The Elementary Circuits of a Directed Graph,” SIAM J. Comput., Vol. 4, No. 1, March 1975. Using DFS and Johnson's algorithm, the backedge detector 102 (
After the characteristic detector 106 labels each node with its shortest distance (e.g., depth value) from the source node, the example characteristic comparator 108 (
In other examples, techniques disclosed herein may be implemented in connection with manual backedge annotation. In such examples, programmers manually annotate backedges when they program DFGs in assembly language by inserting backedge identifiers (e.g., backedge attribute mnemonics) in the assembly code of the DFGs. The manually annotated backedges can then be removed by the buffer inserter 104 (
After annotating backedges, the example buffer inserter 104 of
Example processor-implemented algorithmic techniques that can be implemented by the buffer inserter 104 to insert buffers in DFGs can be based on the following disclosed examples. Table 2 below defines variables of the following example equations.
In Table 2 above and in examples disclosed herein, the terms buffer and storage box are used interchangeably. In addition, the terms edge, arc, connection arc, and interconnecting arc are used interchangeably. In examples disclosed herein, the dataflow architectures (e.g., CGRA, Intel's CSA, etc.) of target devices (e.g., the CGRA device 142 of
Latency Equation
If operation j has a dependency on operation i, then the latency constraint for the inter-dependent operations i and j is defined by the latency-constraint equation uj≥Wi,j+ui. If a quantity of boxi,j buffers needs to be added on a connection arc e(i,j) to latency-balance a DFG, and if each buffer has a latency k, the above latency-constraint equation is updated to be (uj−ui)≥Wi,j+k*boxi,j. The per-edge latency constraint is defined as shown in Constraint 1 below for each connection arc/edge.
∀edge(i,j)(uj−ui)≥Wi,j+k*boxi,j Constraint 1
Constraint 1 above can be implemented in the example buffer inserter 104 of
Capacity Equation
If the interconnecting arc e(i,j) of operation i and j has a throughput of throughputi,j, then according to Little's Law which states throughput=Buffer/Latency, a buffer constraint can be written as shown in Constraint 2 below.
∀edge(i,j)boxi,j*C≥throughputi,j*(uj−ui)−capacityi,j Constraint 2
If a target CGRA device does not have enough storage boxes to balance latency in a DFG, the throughput can be slackened by a given SLACK rate. As noted above, the best achievable throughput of a DFG is 1. By slackening, a desired data throughput is adjusted to be less than 1 (e.g., less than one data token per logical clock cycle). As such, the overall capacity of the storage boxes added on a connection arc e(i,j) is configured to tolerate the throughput-modulated latency (e.g., the slackened latency) minus any pre-existing capacityi,j on the connection arc e(i,j). In examples disclosed herein, all edges of a DFG can be slackened uniformly, or slackening can be performed on a per-edge basis such that throughput can be modulated differently across different edges of the DFG. To determine the amount of SLACK to add to a path, the delay generator 120 uses the SLACK constraint as defined in Constraint 3 below.
∀edge(i,j)boxi,j*C≥SLACK*throughputi,j*(uj−ui)−capacityi,j Constraint 3
Constraint 3 above can be implemented in the example delay generator 120 to determine an amount of delay or SLACK to configure in noncritical paths. In Constraint 3 above, for each edge (∀ edge(i,j)), a product of the quantity of buffers on an edge and the capacity of each buffer (boxi,j*C) is greater than or equal to the difference between: (a) the product of a generated delay (SLACK multiplier), the throughput of the edge, and the start time difference between interdependent operations i and j (SLACK*throughputi,j*(uj−ui)) and (b) the total capacity of the edge (capacityi,j). For example, the total capacity is the capacity sum of any pre-existing storage (e.g., buffer(s)) in the edge and any additional buffer(s) inserted in the edge.
Additionally or alternatively, the example delay generator 120 (
Critical Path Latency Constraint
In some examples in which it is desired to increase a latency of the critical path to facilitate latency-balancing a DFG, the example buffer inserter 104 (
usink−usource≤Wsource,sink+hopssource,sink*k Constraint 4
In Constraint 4 above, the difference between start times of the sink and source nodes (usink−usource) is less than or equal to the sum of: (a) the latency of that edge (Wsource,sink) and (b) the product of the maximum number of hops between the sink and source nodes (hopssource,sink) and the buffer latency (k).
Critical Path Latency Constraint for any I/O Pair
In some examples, a critical path latency constraint per I/O data pair can be performed to facilitate latency-balancing a DFG. A DFG can have multiple inputs and outputs. For each input-output pair in the DFG, the example buffer inserter 104 (
∀(I,O)uO−uI≤WI,O+hopsI,O*k Constraint 5
In Constraint 5 above, for each pair of input data and output data (∀ (I, O)), the difference between the start times of consuming input data and producing corresponding output data (uO−uI) at corresponding nodes is less than or equal to the sum of: (a) the latency of the corresponding edge (WI,O) and (b) the product of the maximum number of hops between the input-output data pair (hopsI,O) and the buffer latency (k).
Storage Box Budget Equations
The example buffer allocator 118 (
∀e(i,j)boxi,j≥0,∀e(i,j)Σboxi,j≤Max Storage Boxes Constraint 6
In Constraint 6 above, for each edge (∀ e(i,j)), the number of storage boxes is greater than or equal to zero, and for each edge (∀ e(i,j)), the total quantity of storage boxes on that edge (Σboxi,j) is less than or equal to the maximum quantity of storage boxes (Max Storage Boxes) available on the CGRA device.
Optimization Goal
In some examples, the buffer inserter 104 inserts a quantity of buffers that contribute towards an optimization goal to maximize data throughput of a DFG. An example of such an optimization goal is represented in Equation 1 below.
Optimized DFG Throughput=Maximize ΣSLACK*throughputi,j Equation 1
In some examples, the buffer inserter 104 can employ other optimization goals in addition to or instead of the above throughput optimization. Examples of other optimization goals include Maximize (minimum (SLACKi,j)), where SLACKi,j denotes independent SLACK applied to each edge. If a target CGRA device has unlimited storage, an example optimization goal is to minimize the quantity of storage boxes (minimizeΣboxi,j) to not exceed the critical path latency.
The example buffer inserter 104 (
Avoiding Latency in Critical Loops
In some examples, adding additional latency to a loop decreases its overall data throughput. To eliminate or substantially decrease the likelihood of adding additional latency to the original cycles, the buffer inserter 104 can be configured to add an additional constraint called Loop Latency Constraint, as represented in Constraint 7 below.
∀(loopStart,loopEnd)uloopEnd−uloopStart≤WloopStart,loopEnd+hoploopStart,loopEnd*k*LOOPloopStart,loopEnd Constraint 7
In Constraint 7 above, for each loop start node and corresponding loop end node, the difference between start times of the loop start and loop end nodes (uloopEnd−uloopStart) is less than or equal to the sum of: (a) the latency of that edge (WloopStart,loopEnd) and (b) the product of the maximum number of hops between the loop start and loop end nodes (hopsloopStart,loopEnd) and the buffer latency (k). In Constraint 7, LOOPloopStart,loopEnd is a modulation term which is set based on the criticality of the loop. If a loop is not on the critical path of the main DFG, the buffer inserter 104 sets a value of LOOPloopStart,loopEnd>1 which represents that it is permissible to increase latency of the loops of the DFG if it is needed to minimize buffering.
If the compiler 100 receives a high-level language program 1016, the example compilation process 1002 converts the high-level language program 1016 into a low-level language (e.g., assembly language) for the elaboration process 1004. If the compiler 100 receives a low-level language program 1018, the compilation process 1002 is skipped, and the example elaboration process 1004 directly receives the low-level language program 1018. The example elaboration process 1004 converts low-level language programs into DFGs (e.g., the input DFG 126 of
The example fusion process 1008 fuses, combines, or joins multiple node operations together on one PE of a target device (e.g., the CGRA device 142 of
While an example manner of implementing the backedge detector 102 and the buffer inserter 104 are illustrated in
In examples disclosed herein, the characteristic detector 106 may implement means for storing a node characteristic identifier, the characteristic comparator 108 may implement means for comparing a node characteristic identifier with a reference criterion, the backedge identifier generator 110 may implement means for generating a backedge identifier, the backedge filter 112 may implement means for removing a backedge, the latency calculator 114 may implement means for determining a critical path latency of a critical path of a DFG, the latency comparator 116 may implement means for comparing a critical path latency to a latency sum of a buffer latency and a noncritical path latency, the buffer allocator 118 may implement means for inserting a buffer in a path of a DFG, and the delay generator 120 may implement means for inserting a delay operation in a path of a DFG and/or may implement means for decreasing a target data throughput performance of a DFG (e.g., using a SLACK parameter).
Flowcharts representative of example hardware logic, machine readable instructions, hardware implemented state machines, and/or any combination thereof for implementing the example backedge detector 102 and/or the example buffer inserter 104 of
The machine readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a fragmented format, a packaged format, etc. Machine readable instructions as described herein may be stored as data (e.g., portions of instructions, code, representations of code, etc.) that may be utilized to create, manufacture, and/or produce machine executable instructions. For example, the machine readable instructions may be fragmented and stored on one or more storage devices and/or computing devices (e.g., servers). The machine readable instructions may require one or more of installation, modification, adaptation, updating, combining, supplementing, configuring, decryption, decompression, unpacking, distribution, reassignment, etc. in order to make them directly readable and/or executable by a computing device and/or other machine. For example, the machine readable instructions may be stored in multiple parts, which are individually compressed, encrypted, and stored on separate computing devices, wherein the parts when decrypted, decompressed, and combined form a set of executable instructions that implement a program such as that described herein. In another example, the machine readable instructions may be stored in a state in which they may be read by a computer, but require addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc. in order to execute the instructions on a particular computing device or other device. In another example, the machine readable instructions may need to be configured (e.g., settings stored, data input, network addresses recorded, etc.) before the machine readable instructions and/or the corresponding program(s) can be executed in whole or in part. Thus, the disclosed machine readable instructions and/or corresponding program(s) are intended to encompass such machine readable instructions and/or program(s) regardless of the particular format or state of the machine readable instructions and/or program(s) when stored or otherwise at rest or in transit.
As mentioned above, the example processes of
“Including” and “comprising” (and all forms and tenses thereof) are used herein to be open ended terms. Thus, whenever a claim employs any form of “include” or “comprise” (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within a claim recitation of any kind, it is to be understood that additional elements, terms, etc. may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase “at least” is used as the transition term in, for example, a preamble of a claim, it is open-ended in the same manner as the term “comprising” and “including” are open ended. The term “and/or” when used, for example, in a form such as A, B, and/or C refers to any combination or subset of A, B, C such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, and (7) A with B and with C. As used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, and (3) at least one A and at least one B.
The example program(s) of
Turning to the example buffer insertion phase 1104, the backedge filter 112 (
In examples in which the backedge detector 102 uses a DFS-based node analysis technique, the characteristic detector 106 sets characteristic identifiers for the nodes of the input DFG 126 for multiple logical clock cycles of the DFG 126 such that each node of the DFG 126 is assigned multiple characteristic identifiers for different execution cycles from the start of execution of the DFG 126 through completion of execution of the DFG 126. In the DFS-based node analysis technique, a node characteristic identifier is settable to: (a) an unexecuted-status identifier to indicate a node has not yet been executed during execution of the DFG, (b) an executing-status identifier indicative of a node being executing during a current logical clock cycle of the DFG, and (c) a completed-status identifier to indicate that no further executions of a node are to occur during execution of the DFG.
In examples in which the backedge detector 102 uses a BFS-based node analysis technique, the characteristic detector 106 sets characteristic identifiers for the nodes of the input DFG 126 based on their execution depth level in the DFG 126 as described above. In other examples that are not DFS-based or BFS-based node analysis techniques, the characteristic detector 106 sets characteristic identifiers for the nodes using any identification suitable for identifying nodes at which backedges occur.
The example characteristic comparator 108 (
In the BFS-based node analysis technique, the reference criterion is a depth level identifier of a source node of an edge. For example, with reference to the input DFG 126 of
When the characteristic comparator 108 confirms a backedge (block 1206), the example backedge identifier generator 110 (
After annotating the backedge at block 1208, or if the characteristic comparator 108 determines at block 1206 that a backedge is not confirmed, the backedge detector 102 determines whether there is another node to analyze (block 1210). If there is another node of the DFG 126 to analyze, control returns to block 1204. Otherwise, the process of
If the example latency comparator 116 determines at block 1306 that the latency sum (or capacity sum) is less than or equal to the critical path latency, the example buffer allocator 118 (
After the buffer insertion of block 1308 or if the latency comparator 116 determines at block 1306 that the latency sum is not less than or equal to the critical path latency, the latency comparator 116 determines whether the DFG is substantially latency-balanced (block 1310). For example, the latency comparator 116 may determine that the DFG is substantially latency-balanced when it performs a comparison the critical path latency and the buffered noncritical path latency and the comparison indicates a difference of less than one buffer latency. If the latency comparator 116 determines at block 1310 that the DFG is not latency balanced, the buffer allocator 118 determines whether all buffers available in a target device have been allocated (block 1312). The buffer allocator 118 may determine whether all buffers available in the target device have been allocated based on Constraint 6 above. For example, if the buffer allocation has not reached the maximum storage boxes available in the target CGRA device 142 (
If the buffer allocator 118 determines at block 1312 that all buffers have been allocated, the delay generator 120 (
The processor platform 1400 of the illustrated example includes a processor 1412. The processor 1412 of the illustrated example is hardware. For example, the processor 1412 can be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The hardware processor 1412 may be a semiconductor based (e.g., silicon based) device. In this example, the processor 1412 implements the example compiler 100, the example backedge detector 102, the example buffer inserter 104, the example characteristic detector 106, the example characteristic comparator 108, the example backedge identifier generator 110, the example backedge filter 112, the example latency calculator 114, the example latency comparator 116, the example buffer allocator 118, and the example delay generator 120.
The processor 1412 of the illustrated example includes a local memory 1413 (e.g., a cache). The processor 1412 of the illustrated example is in communication with a main memory including a volatile memory 1414 and a non-volatile memory 1416 via a bus 1418. The volatile memory 1414 may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®) and/or any other type of random access memory device. The non-volatile memory 1416 may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory 1414, 1416 is controlled by a memory controller.
The processor platform 1400 of the illustrated example also includes an interface circuit 1420. The interface circuit 1420 may be implemented by any type of interface standard, such as an Ethernet interface, a universal serial bus (USB), a Bluetooth® interface, a near field communication (NFC) interface, and/or a PCI express interface.
In the illustrated example, one or more input devices 1422 are connected to the interface circuit 1420. The input device(s) 1422 perm it(s) a user to enter data and/or commands into the processor 1412. The input device(s) can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a track-pad, a trackball, isopoint and/or a voice recognition system.
One or more output devices 1424 are also connected to the interface circuit 1420 of the illustrated example. The output devices 1424 can be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube display (CRT), an in-place switching (IPS) display, a touchscreen, etc.), a tactile output device, a printer and/or speaker. The interface circuit 1420 of the illustrated example, thus, typically includes a graphics driver card, a graphics driver chip and/or a graphics driver processor.
The interface circuit 1420 of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and/or a network interface to facilitate exchange of data with external machines (e.g., computing devices of any kind) via a network 1426. The communication can be via, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-site wireless system, a cellular telephone system, etc.
The processor platform 1400 of the illustrated example also includes one or more mass storage devices 1428 for storing software and/or data. Examples of such mass storage devices 1428 include floppy disk drives, hard drive disks, compact disk drives, Blu-ray disk drives, redundant array of independent disks (RAID) systems, and digital versatile disk (DVD) drives.
Machine executable instructions 1432 represented by the flowcharts of
To access memory and/or cache of a CGRA device, the array of PEs 1500 is provided with an example request address file (RAF) memory interface 1502. For example, the RAF memory interface 1502 may be used by the PEs to read external input data into nodes in a DFG from memory and/or cache and/or to write external output data from nodes of the DFG to memory and/or cache. The PEs are connected to one another via in-fabric data buses or channels as shown in
Additional details of CGRA devices (e.g., CSA devices) are disclosed in U.S. patent application Ser. No. 15/396,402, filed Dec. 30, 2016, and entitled “Processors, Methods, and Systems with a Configurable Spatial Accelerator.” U.S. patent application Ser. No. 15/396,402 is incorporated herein by reference in its entirety. Although examples disclosed herein are described in connection with CGRA devices, examples disclosed herein may additionally or alternatively be implemented in connection with other types of devices such as FPGA devices, different types of CGRA architectures, etc.
From the foregoing, it will be appreciated that example methods, apparatus and articles of manufacture have been disclosed that may be used to implement a DFG performance optimization feature of a complier (e.g., the compiler 100 of
Although prior techniques provide buffer insertion solutions for synchronous dataflow architectures, examples disclosed herein are useful for inserting buffers in DFGs that run on asynchronous CGRA devices. For example, a prior technique by Gao Guang Rong (“Gao's algorithm”) seeks to buffer a synchronous acyclic DFG. (Gao's algorithm is described in a paper entitled, “A Pipelined Code Mapping Scheme for Static Data Flow Computers,” Massachusetts Institute of Technology, Aug. 28, 1986.) However, Gao's algorithm assumes an unlimited supply of buffering and then tries to minimize buffering in a way that does not increase the critical path latency and constructs final silicon to match buffering requirements. Examples disclosed herein overcome physical constraints of CGRA device chips in which buffer storage is limited. As such, examples disclosed herein are useful to optimize latency while generating an acceptable reduced-performance solution when the limited buffer storage is exhausted. Examples disclosed herein also enable relaxing the critical path latency constraint to be able to fit limited budgets buffer resources while minimizing the overall increase in the critical path latency.
In addition, Gao's algorithm only works for synchronous DFGs that do not have cycles (e.g., directed acyclic graphs). However, many real-world DFGs do contain cycles, especially if there is a while loop or loops with arbitrarily complex inner loop dependency pattern. Therefore, examples disclosed herein are significantly more useful than prior techniques because they latency-balance DFGs that contain cycles. In addition, examples disclosed herein target DFGs that are more complex (e.g., DFGs that contain one or more cycles) than DFGs that can be processed using Gao's algorithm.
In addition, Gao's algorithm assumes a uniform data-rate of 1 and targets a synchronous dataflow architecture. However, examples disclosed herein can be applied to asynchronous dataflow architecture in which each operation can have a variable data rate throughput. Gao's algorithm only works for directed acyclic DFGs. However, examples disclosed herein handle buffer insertion for arbitrary DFGs that may contain cycles or loops.
Examples disclosed herein also consider a fundamentally asynchronous architecture in which the amount of buffering is not necessarily equivalent to the latency of the buffering. However, the prior technique of Gao's algorithm assumes latency is equivalent to buffering, which means if there is one buffer, then that will allow tolerating one unit of latency. In contrast, in DFG structures that may be latency-balanced using examples disclosed herein, buffering is elastic instead of being linear. That is, in examples disclosed herein, changes in latency are not directly related to changes in capacity/buffering. Some examples disclosed herein insert buffers only in certain discrete sizes (e.g., a size defined by capacity ‘C’). Such discrete-size storage boxes implement the buffers (e.g., buffer boxes) for insertion in DFGs in accordance with teachings of this disclosure. Each buffer box has a maximum capacity of C and adds a constant latency of k≤C cycles at the point of insertion. The prior technique of Gao's algorithm assumes buffers can be of any arbitrary size and does not have any limit of total buffers being used. Therefore, Gao's algorithm cannot be directly applied to solve a latency-balancing problem intended to a practical solution for executing a DFG on real hardware.
In addition, each connection arc or interconnect in a target CGRA device (e.g., the CGRA device 142 of
Example Performance Results
Examples disclosed herein were tested in a controlled laboratory environment. In particular, the example buffer insertion techniques disclosed herein were implemented using python with networkx and some supplemental linear programming libraries. The input DFG to the examples disclosed herein was a binary search abstract DFG which included several cycles. After creating a graphical representation of the DFG, examples disclosed herein detected, annotated, and removed backedges from the DFG, and created equations to represent the DFG structure, and performed the buffer insertion process in accordance with teachings of this disclosure based on a linear programming solver from cvxpy with a goal to minimize buffers. The output DFG program was run on an Intel CSA device (e.g., a CGRA device) using its cycle-accurate simulator using the following configurations.
Unrealistic default: All edges have a default quantity of 128 storage boxes
Realistic default without BI: All edges have a default depth of three, except 1-bit edges which have a default depth of eight (Buffer Insertion is not used).
Realistic default with BI: All edges have a default depth of three, except 1-bit edges which have a default depth of eight (Buffer Insertion is used).
The test implementation assumed that a maximum of 512 storage boxes, each with a capacity of 32 bits.
Table 3 below shows that the buffer insertion techniques disclosed herein were able to insert buffers in the cyclic DFG and match the unrealistic default performance bound.
Similar improved trends were observed for other computer kernels. For example,
The following pertain to further examples disclosed herein.
Example 1 is an apparatus to insert buffers in a dataflow graph. The apparatus of Example 1 includes a backedge filter to remove a backedge between a first node and a second node of the dataflow graph, the first node representing a first operation of the dataflow graph, the second node representing a second operation of the dataflow graph; a latency calculator to determine a critical path latency of a critical path of the dataflow graph that includes the first node and the second node, the critical path having a longer latency to completion relative to a second path that terminates at the second node; a latency comparator to compare the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency corresponding to the second path; and a buffer allocator to insert one or more buffers in the second path based on the comparison performed by the latency comparator.
In Example 2, the subject matter of Example 1 can optionally include that the first node is a source node that generates an output, and the second node is a sink node that executes after the source node and consumes an input.
In Example 3, the subject matter of any one of Examples 1-2 can optionally include that the first node receives input data, and the second node generates output data associated with the input data.
In Example 4, the subject matter of any one of Examples 1-3 can optionally include that the critical path latency is based on having a latency sum greater than the second path latency.
In Example 5, the subject matter of any one of Examples 1-4 can optionally include that the latency comparator is to compare the critical path latency to a second latency sum of the buffer latency, the second path latency, and a second buffer latency; and the buffer allocator is to not insert a second buffer in the second path when the latency comparator determines that the second latency sum exceeds the critical path latency.
In Example 6, the subject matter of any one of Examples 1-5 can optionally include that the backedge forms a loop with the critical path, and the backedge filter is to remove the backedge based on a backedge identifier stored in memory in association with a connection arc between the first node and the second node.
In Example 7, the subject matter of any one of Examples 1-6 can optionally include that the buffer is a storage box in a coarse-grain reconfigurable architecture, and the buffer latency corresponds to a logical clock cycle.
In Example 8, the subject matter of any one of Examples 1-7 can optionally include a delay generator to insert a delay operation in the second path when the buffer allocator determines that a second buffer is not available in a target device for insertion in the second path to increase a similarity between the critical path latency and the second path latency.
In Example 9, the subject matter of any one of Examples 1-8 can optionally include a delay generator to decrease a target data throughput performance of the dataflow graph using a SLACK parameter when a sufficient number of buffers are not available in a target device for insertion in the second path.
In Example 10, the subject matter of any one of Examples 1-9 can optionally include a delay generator to determine a latency on the second path between the first and second nodes by multiplying a multiplier with a throughput of the second path.
In Example 11, the subject matter of any one of Examples 1-10 can optionally include that a number of the one or more buffers inserted in the second path does not exceed a capacity of total buffers available on a target device for the second path.
Example 12 is a non-transitory computer readable storage medium comprising instructions that, when executed by a processor, cause the processor to at least: remove a backedge between a first node and a second node of a dataflow graph, the first node representing a first operation of the dataflow graph, the second node representing a second operation of the dataflow graph; determine a critical path latency of a critical path of the dataflow graph that includes the first node and the second node, the critical path having a longer latency to completion relative to a second path that terminates at the second node; compare the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency corresponding to the second path; and insert one or more buffers in the second path based on the comparison performed by the latency comparator.
In Example 13, the subject matter of Example 12 can optionally include that the first node is a source node that generates an output, and the second node is a sink node that executes after the source node and consumes an input.
In Example 14, the subject matter of any one of Examples 12-13 can optionally include that the first node receives input data, and the second node generates output data associated with the input data.
In Example 15, the subject matter of any one of Examples 12-14 can optionally include that the critical path latency is based on having a latency sum greater than the second path latency.
In Example 16, the subject matter of any one of Examples 12-15 can optionally include that the instructions, when executed by the processor, are to cause the processor to: compare the critical path latency to a second latency sum of the buffer latency, the second path latency, and a second buffer latency; and determine to not insert a second buffer in the second path when the second latency sum exceeds the critical path latency.
In Example 17, the subject matter of any one of Examples 12-16 can optionally include that the backedge forms a loop with the critical path, and the instructions, when executed by the processor, are to cause the processor to remove the backedge based on a backedge identifier stored in memory in association with a connection arc between the first node and the second node.
In Example 18, the subject matter of any one of Examples 12-17 can optionally include that the buffer is a storage box in a coarse-grain reconfigurable architecture, and the buffer latency corresponds to a logical clock cycle.
In Example 19, the subject matter of any one of Examples 12-18 can optionally include that the instructions, when executed by the processor, are to cause the processor to insert a delay operation in the second path when the buffer allocator determines that a second buffer is not available in a target device for insertion in the second path to increase a similarity between the critical path latency and the second path latency.
In Example 20, the subject matter of any one of Examples 12-19 can optionally include that the instructions, when executed by the processor, are to cause the processor to decrease a target data throughput performance of the dataflow graph using a SLACK parameter when a sufficient number of buffers are not available in a target device for insertion in the second path.
In Example 21, the subject matter of any one of Examples 12-20 can optionally include that the instructions, when executed by the processor, are to cause the processor to determine a latency on the second path between the first and second nodes by multiplying a multiplier with a throughput of the second path.
In Example 22, the subject matter of any one of Examples 12-21 can optionally include that a number of the one or more buffers inserted in the second path does not exceed a capacity of total buffers available on a target device for the second path.
Example 23 is a method to insert buffers in a dataflow graph. The method of Example 23 includes removing a backedge between a first node and a second node of the dataflow graph, the first node representing a first operation of the dataflow graph, the second node representing a second operation of the dataflow graph; determining a critical path latency of a critical path of the dataflow graph that includes the first node and the second node, the critical path having a longer latency to completion relative to a second path that terminates at the second node; comparing the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency corresponding to the second path; and inserting one or more buffers in the second path based on the comparison performed by the latency comparator.
In Example 24, the subject matter of Example 23 can optionally include that the first node is a source node that generates an output, and the second node is a sink node that executes after the source node and consumes an input.
In Example 25, the subject matter of any one of Examples 23-24 can optionally include that the first node receives input data, and the second node generates output data associated with the input data.
In Example 26, the subject matter of any one of Examples 23-25 can optionally include that the critical path latency is based on having a latency sum greater than the second path latency.
In Example 27, the subject matter of any one of Examples 23-26 can optionally include: comparing the critical path latency to a second latency sum of the buffer latency, the second path latency, and a second buffer latency; and determining to not insert a second buffer in the second path when the second latency sum exceeds the critical path latency.
In Example 28, the subject matter of any one of Examples 23-27 can optionally include that the backedge forms a loop with the critical path, and further include removing the backedge based on a backedge identifier stored in memory in association with a connection arc between the first node and the second node.
In Example 29, the subject matter of any one of Examples 23-28 can optionally include that the buffer is a storage box in a coarse-grain reconfigurable architecture, and the buffer latency corresponds to a logical clock cycle.
In Example 30, the subject matter of any one of Examples 23-29 can optionally include inserting a delay operation in the second path when the buffer allocator determines that a second buffer is not available in a target device for insertion in the second path to increase a similarity between the critical path latency and the second path latency.
In Example 31, the subject matter of any one of Examples 23-30 can optionally include decreasing a target data throughput performance of the dataflow graph using a SLACK parameter when a sufficient number of buffers are not available in a target device for insertion in the second path.
In Example 32, the subject matter of any one of Examples 23-31 can optionally include determining a latency on the second path between the first and second nodes by multiplying a multiplier with a throughput of the second path.
In Example 33, the subject matter of any one of Examples 23-32 can optionally include that a number of the one or more buffers inserted in the second path does not exceed a capacity of total buffers available on a target device for the second path.
Example 34 is an apparatus to insert buffers in a dataflow graph. The apparatus of Example 34 includes means for removing a backedge between a first node and a second node of the dataflow graph, the first node representing a first operation of the dataflow graph, the second node representing a second operation of the dataflow graph; means for determining a critical path latency of a critical path of the dataflow graph that includes the first node and the second node, the critical path having a longer latency to completion relative to a second path that terminates at the second node; means for comparing the critical path latency to a latency sum of a buffer latency and a second path latency, the second path latency corresponding to the second path; and means for inserting one or more buffers in the second path based on the comparison performed by the latency comparator.
In Example 35, the subject matter of Example 34 can optionally include that the first node is a source node that generates an output, and the second node is a sink node that executes after the source node and consumes an input.
In Example 36, the subject matter of any one of Examples 34-35 can optionally include that the first node receives input data, and the second node generates output data associated with the input data.
In Example 37, the subject matter of any one of Examples 34-36 can optionally include that the critical path latency is based on having a latency sum greater than the second path latency.
In Example 38, the subject matter of any one of Examples 34-37 can optionally include that the means for comparing the critical path latency is to: compare the critical path latency to a second latency sum of the buffer latency, the second path latency, and a second buffer latency; and determine not to insert a second buffer in the second path when the latency comparator determines that the second latency sum exceeds the critical path latency.
In Example 39, the subject matter of any one of Examples 34-38 can optionally include that the backedge forms a loop with the critical path, and the means for removing the backedge is to remove the backedge based on a backedge identifier stored in memory in association with a connection arc between the first node and the second node.
In Example 40, the subject matter of any one of Examples 34-39 can optionally include that the buffer is a storage box in a coarse-grain reconfigurable architecture, and the buffer latency corresponds to a logical clock cycle.
In Example 41, the subject matter of any one of Examples 34-40 can optionally include means for inserting a delay operation in the second path when the buffer allocator determines that a second buffer is not available in a target device for insertion in the second path to increase a similarity between the critical path latency and the second path latency.
In Example 42, the subject matter of any one of Examples 34-41 can optionally include means for decreasing a target data throughput performance of the dataflow graph using a SLACK parameter when a sufficient number of buffers are not available in a target device for insertion in the second path.
In Example 43, the subject matter of any one of Examples 34-42 can optionally include means for decreasing a target data throughput to determine a latency on the second path between the first and second nodes by multiplying a multiplier with a throughput of the second path.
In Example 44, the subject matter of any one of Examples 34-43 can optionally include that a number of the one or more buffers inserted in the second path does not exceed a capacity of total buffers available on a target device for the second path.
Example 45 is an apparatus to annotate back edges in a dataflow graph. The apparatus of Example 45 includes a characteristic detector to store a node characteristic identifier in memory in association with a first node of the dataflow graph; a characteristic comparator to compare the node characteristic identifier with a reference criterion; and a backedge identifier generator to generate a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.
In Example 46, the subject matter of Example 45 can optionally include that the reference criterion is an executing-status identifier, and the characteristic comparator is to confirm a presence of the backedge between the first and second nodes when the node characteristic identifier matches the executing-status identifier, the executing-status identifier indicative of the first node executing during a first logical clock cycle of the dataflow graph, and the characteristic comparator to compare the node characteristic identifier with the reference criterion corresponding to a second logical clock cycle of the dataflow graph.
In Example 47, the subject matter of any one of Examples 45-46 can optionally include that the node characteristic identifier is settable to: (a) an unexecuted-status identifier to indicate the first node has not yet been executed during execution of the dataflow graph, (b) the executing-status identifier, and (c) a completed-status identifier to indicate that no further executions of the first node are to occur during execution of the dataflow graph.
In Example 48, the subject matter of any one of Examples 45-47 can optionally include that the node characteristic identifier is a first depth level identifier of the first node, the reference criterion is a second depth level identifier of the second node, the characteristic comparator is to confirm a presence of the backedge based on execution control returning from a higher depth level corresponding to the second depth level identifier of the second node to a lower depth level corresponding to the first depth level identifier of the first node.
In Example 49, the subject matter of any one of Examples 45-48 can optionally include that the coarse-grain reconfigurable architecture device includes an array of processing elements interconnected by a network, the first node to be executed by a first one of the processing elements, and the second node to be executed by a second one of the processing elements.
In Example 50, the subject matter of any one of Examples 45-49 can optionally include that the characteristic detector, the characteristic comparator, and the backedge identifier generator are to operate in association with a compiler, the compiler to generate the dataflow graph based on source code in at least one of a high-level programming language or assembly programming language.
In Example 51, the subject matter of any one of Examples 45-50 can optionally include that the backedge identifier generator is to generate the backedge identifier as a backedge attribute and to store the backedge attribute in assembly code of the dataflow graph to represent the backedge in the assembly code.
Example 52 is a non-transitory computer readable storage medium comprising instructions that, when executed by a processor, cause the processor to at least: store a node characteristic identifier in memory in association with a first node of the dataflow graph; compare the node characteristic identifier with a reference criterion; and generate a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.
In Example 53, the subject matter of Example 52 can optionally include that the reference criterion is an executing-status identifier, and the instructions, when executed by the processor, are to cause the processor to: confirm a presence of the backedge between the first and second nodes when the node characteristic identifier matches the executing-status identifier, the executing-status identifier indicative of the first node executing during a first logical clock cycle of the dataflow graph; and compare the node characteristic identifier with the reference criterion corresponding to a second logical clock cycle of the dataflow graph.
In Example 54, the subject matter of any one of Examples 52-53 can optionally include that the node characteristic identifier is settable to: (a) an unexecuted-status identifier to indicate the first node has not yet been executed during execution of the dataflow graph, (b) the executing-status identifier, and (c) a completed-status identifier to indicate that no further executions of the first node are to occur during execution of the dataflow graph.
In Example 55, the subject matter of any one of Examples 52-54 can optionally include that the node characteristic identifier is a first depth level identifier of the first node, the reference criterion is a second depth level identifier of the second node, the instructions, when executed by the processor, are to cause the processor to confirm a presence of the backedge based on execution control returning from a higher depth level corresponding to the second depth level identifier of the second node to a lower depth level corresponding to the first depth level identifier of the first node.
In Example 56, the subject matter of any one of Examples 52-55 can optionally include that the coarse-grain reconfigurable architecture device includes an array of processing elements interconnected by a network, the first node to be executed by a first one of the processing elements, and the second node to be executed by a second one of the processing elements.
In Example 57, the subject matter of any one of Examples 52-56 can optionally include that the instructions are to be executed in association with a compiler, the compiler to generate the dataflow graph based on source code in at least one of a high-level programming language or assembly programming language.
In Example 58, the subject matter of any one of Examples 52-57 can optionally include that the instructions, when executed by the processor, are to cause the processor to generate the backedge identifier as a backedge attribute and to store the backedge attribute in assembly code of the dataflow graph to represent the backedge in the assembly code.
Example 59 is a method to annotate back edges in a dataflow graph. The method of Example 59 includes storing a node characteristic identifier in memory in association with a first node of the dataflow graph; comparing the node characteristic identifier with a reference criterion; and generating a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.
In Example 60, the subject matter of Example 59 can optionally include that the reference criterion is an executing-status identifier, and further include: confirming a presence of the backedge between the first and second nodes when the node characteristic identifier matches the executing-status identifier, the executing-status identifier indicative of the first node executing during a first logical clock cycle of the dataflow graph; and comparing the node characteristic identifier with the reference criterion corresponding to a second logical clock cycle of the dataflow graph.
In Example 61, the subject matter of any one of Examples 59-60 can optionally include that the node characteristic identifier is settable to: (a) an unexecuted-status identifier to indicate the first node has not yet been executed during execution of the dataflow graph, (b) the executing-status identifier, and (c) a completed-status identifier to indicate that no further executions of the first node are to occur during execution of the dataflow graph.
In Example 62, the subject matter of any one of Examples 59-61 can optionally include that the node characteristic identifier is a first depth level identifier of the first node, the reference criterion is a second depth level identifier of the second node, and further include confirming a presence of the backedge based on execution control returning from a higher depth level corresponding to the second depth level identifier of the second node to a lower depth level corresponding to the first depth level identifier of the first node.
In Example 63, the subject matter of any one of Examples 59-62 can optionally include that the coarse-grain reconfigurable architecture device includes an array of processing elements interconnected by a network, the first node to be executed by a first one of the processing elements, and the second node to be executed by a second one of the processing elements.
In Example 64, the subject matter of any one of Examples 59-63 can optionally include that the storing of the node characteristic identifier, the comparing of the node characteristic identifier with the reference criterion, and the generating of the backedge identifier are to be performed by a compiler, the compiler to generate the dataflow graph based on source code in at least one of a high-level programming language or assembly programming language.
In Example 65, the subject matter of any one of Examples 59-64 can optionally include generating the backedge identifier as a backedge attribute and to store the backedge attribute in assembly code of the dataflow graph to represent the backedge in the assembly code.
Example 66 is an apparatus to annotate back edges in a dataflow graph. The apparatus of Example 66 includes means for storing a node characteristic identifier in memory in association with a first node of the dataflow graph; means for comparing the node characteristic identifier with a reference criterion; and means for generating a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.
In Example 67, the subject matter of Example 66 can optionally include that the reference criterion is an executing-status identifier, and the means for comparing is to confirm a presence of the backedge between the first and second nodes when the node characteristic identifier matches the executing-status identifier, the executing-status identifier indicative of the first node executing during a first logical clock cycle of the dataflow graph, and the means for comparing is to compare the node characteristic identifier with the reference criterion corresponding to a second logical clock cycle of the dataflow graph.
In Example 68, the subject matter of any one of Examples 66-67 can optionally include that the node characteristic identifier is settable to: (a) an unexecuted-status identifier to indicate the first node has not yet been executed during execution of the dataflow graph, (b) the executing-status identifier, and (c) a completed-status identifier to indicate that no further executions of the first node are to occur during execution of the dataflow graph.
In Example 69, the subject matter of any one of Examples 66-68 can optionally include that the node characteristic identifier is a first depth level identifier of the first node, the reference criterion is a second depth level identifier of the second node, the means for comparing is to confirm a presence of the backedge based on execution control returning from a higher depth level corresponding to the second depth level identifier of the second node to a lower depth level corresponding to the first depth level identifier of the first node.
In Example 70, the subject matter of any one of Examples 66-69 can optionally include that the coarse-grain reconfigurable architecture device includes an array of processing elements interconnected by a network, the first node to be executed by a first one of the processing elements, and the second node to be executed by a second one of the processing elements.
In Example 71, the subject matter of any one of Examples 66-70 can optionally include that the means for storing, the means for comparing, and the means for generating the backedge identifier are to operate in association with a compiler, the compiler to generate the dataflow graph based on source code in at least one of a high-level programming language or assembly programming language.
In Example 72, the subject matter of any one of Examples 66-71 can optionally include that the means for generating the backedge identifier is to generate the backedge identifier as a backedge attribute and to store the backedge attribute in assembly code of the dataflow graph to represent the backedge in the assembly code.
Although certain example methods, apparatus and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus and articles of manufacture fairly falling within the scope of the claims of this patent.
This patent arises from a continuation of U.S. patent application Ser. No. 16/370,935, filed Mar. 30, 2019, which is hereby incorporated herein by reference in its entirety.
This invention was made with Government support under subcontract number B620873 awarded by the Department of Energy. The Government has certain rights in this invention.
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| Number | Date | Country | |
|---|---|---|---|
| 20210365248 A1 | Nov 2021 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16370935 | Mar 2019 | US |
| Child | 17341086 | US |
